1 /* SPDX-License-Identifier: GPL-2.0 2 * 3 * Copyright 2016-2020 HabanaLabs, Ltd. 4 * All Rights Reserved. 5 * 6 */ 7 8 /************************************ 9 ** This is an auto-generated file ** 10 ** DO NOT EDIT BELOW ** 11 ************************************/ 12 13 #ifndef ASIC_REG_DCORE0_VDEC0_BRDG_CTRL_MASKS_H_ 14 #define ASIC_REG_DCORE0_VDEC0_BRDG_CTRL_MASKS_H_ 15 16 /* 17 ***************************************** 18 * DCORE0_VDEC0_BRDG_CTRL 19 * (Prototype: VDEC_BRDG_CTRL) 20 ***************************************** 21 */ 22 23 /* DCORE0_VDEC0_BRDG_CTRL_CGM_DISABLE */ 24 #define DCORE0_VDEC0_BRDG_CTRL_CGM_DISABLE_VAL_SHIFT 0 25 #define DCORE0_VDEC0_BRDG_CTRL_CGM_DISABLE_VAL_MASK 0x1 26 27 /* DCORE0_VDEC0_BRDG_CTRL_IDLE_MASK */ 28 #define DCORE0_VDEC0_BRDG_CTRL_IDLE_MASK_VAL_SHIFT 0 29 #define DCORE0_VDEC0_BRDG_CTRL_IDLE_MASK_VAL_MASK 0x7 30 31 /* DCORE0_VDEC0_BRDG_CTRL_APB_CGM_CNT */ 32 #define DCORE0_VDEC0_BRDG_CTRL_APB_CGM_CNT_VAL_SHIFT 0 33 #define DCORE0_VDEC0_BRDG_CTRL_APB_CGM_CNT_VAL_MASK 0xFFFF 34 35 /* DCORE0_VDEC0_BRDG_CTRL_APB_ARB_WDOG_CNT */ 36 #define DCORE0_VDEC0_BRDG_CTRL_APB_ARB_WDOG_CNT_VAL_SHIFT 0 37 #define DCORE0_VDEC0_BRDG_CTRL_APB_ARB_WDOG_CNT_VAL_MASK 0xFFFF 38 39 /* DCORE0_VDEC0_BRDG_CTRL_GRACEFUL */ 40 #define DCORE0_VDEC0_BRDG_CTRL_GRACEFUL_STOP_SHIFT 0 41 #define DCORE0_VDEC0_BRDG_CTRL_GRACEFUL_STOP_MASK 0x1 42 #define DCORE0_VDEC0_BRDG_CTRL_GRACEFUL_PEND_SHIFT 4 43 #define DCORE0_VDEC0_BRDG_CTRL_GRACEFUL_PEND_MASK 0x10 44 45 /* DCORE0_VDEC0_BRDG_CTRL_IDLE_CGM_CNT */ 46 #define DCORE0_VDEC0_BRDG_CTRL_IDLE_CGM_CNT_VAL_SHIFT 0 47 #define DCORE0_VDEC0_BRDG_CTRL_IDLE_CGM_CNT_VAL_MASK 0xFFFF 48 49 /* DCORE0_VDEC0_BRDG_CTRL_CAUSE_INTR */ 50 #define DCORE0_VDEC0_BRDG_CTRL_CAUSE_INTR_MSIX_VCD_HBW_SEI_SHIFT 0 51 #define DCORE0_VDEC0_BRDG_CTRL_CAUSE_INTR_MSIX_VCD_HBW_SEI_MASK 0x1 52 #define DCORE0_VDEC0_BRDG_CTRL_CAUSE_INTR_MSIX_L2C_HBW_SEI_SHIFT 1 53 #define DCORE0_VDEC0_BRDG_CTRL_CAUSE_INTR_MSIX_L2C_HBW_SEI_MASK 0x2 54 #define DCORE0_VDEC0_BRDG_CTRL_CAUSE_INTR_MSIX_NRM_HBW_SEI_SHIFT 2 55 #define DCORE0_VDEC0_BRDG_CTRL_CAUSE_INTR_MSIX_NRM_HBW_SEI_MASK 0x4 56 #define DCORE0_VDEC0_BRDG_CTRL_CAUSE_INTR_MSIX_ABNRM_HBW_SEI_SHIFT 3 57 #define DCORE0_VDEC0_BRDG_CTRL_CAUSE_INTR_MSIX_ABNRM_HBW_SEI_MASK 0x8 58 #define DCORE0_VDEC0_BRDG_CTRL_CAUSE_INTR_MSIX_VCD_LBW_SEI_SHIFT 4 59 #define DCORE0_VDEC0_BRDG_CTRL_CAUSE_INTR_MSIX_VCD_LBW_SEI_MASK 0x10 60 #define DCORE0_VDEC0_BRDG_CTRL_CAUSE_INTR_MSIX_L2C_LBW_SEI_SHIFT 5 61 #define DCORE0_VDEC0_BRDG_CTRL_CAUSE_INTR_MSIX_L2C_LBW_SEI_MASK 0x20 62 #define DCORE0_VDEC0_BRDG_CTRL_CAUSE_INTR_MSIX_NRM_LBW_SEI_SHIFT 6 63 #define DCORE0_VDEC0_BRDG_CTRL_CAUSE_INTR_MSIX_NRM_LBW_SEI_MASK 0x40 64 #define DCORE0_VDEC0_BRDG_CTRL_CAUSE_INTR_MSIX_ABNRM_LBW_SEI_SHIFT 7 65 #define DCORE0_VDEC0_BRDG_CTRL_CAUSE_INTR_MSIX_ABNRM_LBW_SEI_MASK 0x80 66 #define DCORE0_VDEC0_BRDG_CTRL_CAUSE_INTR_APB_VCD_LBW_SEI_SHIFT 8 67 #define DCORE0_VDEC0_BRDG_CTRL_CAUSE_INTR_APB_VCD_LBW_SEI_MASK 0x100 68 #define DCORE0_VDEC0_BRDG_CTRL_CAUSE_INTR_APB_L2C_LBW_SEI_SHIFT 9 69 #define DCORE0_VDEC0_BRDG_CTRL_CAUSE_INTR_APB_L2C_LBW_SEI_MASK 0x200 70 #define DCORE0_VDEC0_BRDG_CTRL_CAUSE_INTR_APB_NRM_LBW_SEI_SHIFT 10 71 #define DCORE0_VDEC0_BRDG_CTRL_CAUSE_INTR_APB_NRM_LBW_SEI_MASK 0x400 72 #define DCORE0_VDEC0_BRDG_CTRL_CAUSE_INTR_APB_ABNRM_LBW_SEI_SHIFT 11 73 #define DCORE0_VDEC0_BRDG_CTRL_CAUSE_INTR_APB_ABNRM_LBW_SEI_MASK 0x800 74 #define DCORE0_VDEC0_BRDG_CTRL_CAUSE_INTR_DEC_SEI_SHIFT 12 75 #define DCORE0_VDEC0_BRDG_CTRL_CAUSE_INTR_DEC_SEI_MASK 0x1000 76 #define DCORE0_VDEC0_BRDG_CTRL_CAUSE_INTR_DEC_APB_SEI_SHIFT 13 77 #define DCORE0_VDEC0_BRDG_CTRL_CAUSE_INTR_DEC_APB_SEI_MASK 0x2000 78 #define DCORE0_VDEC0_BRDG_CTRL_CAUSE_INTR_TRC_APB_SEI_SHIFT 14 79 #define DCORE0_VDEC0_BRDG_CTRL_CAUSE_INTR_TRC_APB_SEI_MASK 0x4000 80 #define DCORE0_VDEC0_BRDG_CTRL_CAUSE_INTR_LBW_MSTR_IF_SEI_SHIFT 15 81 #define DCORE0_VDEC0_BRDG_CTRL_CAUSE_INTR_LBW_MSTR_IF_SEI_MASK 0x8000 82 #define DCORE0_VDEC0_BRDG_CTRL_CAUSE_INTR_AXI_SPLIT_BRESP_ERR_SEI_SHIFT 16 83 #define DCORE0_VDEC0_BRDG_CTRL_CAUSE_INTR_AXI_SPLIT_BRESP_ERR_SEI_MASK 0x10000 84 #define DCORE0_VDEC0_BRDG_CTRL_CAUSE_INTR_HBW_AXI_WR_VIOL_SEI_SHIFT 17 85 #define DCORE0_VDEC0_BRDG_CTRL_CAUSE_INTR_HBW_AXI_WR_VIOL_SEI_MASK 0x20000 86 #define DCORE0_VDEC0_BRDG_CTRL_CAUSE_INTR_HBW_AXI_RD_VIOL_SEI_SHIFT 18 87 #define DCORE0_VDEC0_BRDG_CTRL_CAUSE_INTR_HBW_AXI_RD_VIOL_SEI_MASK 0x40000 88 #define DCORE0_VDEC0_BRDG_CTRL_CAUSE_INTR_LBW_AXI_WR_VIOL_SEI_SHIFT 19 89 #define DCORE0_VDEC0_BRDG_CTRL_CAUSE_INTR_LBW_AXI_WR_VIOL_SEI_MASK 0x80000 90 #define DCORE0_VDEC0_BRDG_CTRL_CAUSE_INTR_LBW_AXI_RD_VIOL_SEI_SHIFT 20 91 #define DCORE0_VDEC0_BRDG_CTRL_CAUSE_INTR_LBW_AXI_RD_VIOL_SEI_MASK 0x100000 92 #define DCORE0_VDEC0_BRDG_CTRL_CAUSE_INTR_VCD_SPI_SHIFT 21 93 #define DCORE0_VDEC0_BRDG_CTRL_CAUSE_INTR_VCD_SPI_MASK 0x200000 94 #define DCORE0_VDEC0_BRDG_CTRL_CAUSE_INTR_L2C_SPI_SHIFT 22 95 #define DCORE0_VDEC0_BRDG_CTRL_CAUSE_INTR_L2C_SPI_MASK 0x400000 96 #define DCORE0_VDEC0_BRDG_CTRL_CAUSE_INTR_NRM_SPI_SHIFT 23 97 #define DCORE0_VDEC0_BRDG_CTRL_CAUSE_INTR_NRM_SPI_MASK 0x800000 98 #define DCORE0_VDEC0_BRDG_CTRL_CAUSE_INTR_ABNRM_SPI_SHIFT 24 99 #define DCORE0_VDEC0_BRDG_CTRL_CAUSE_INTR_ABNRM_SPI_MASK 0x1000000 100 101 /* DCORE0_VDEC0_BRDG_CTRL_HBW_AXI_VIOL_CAUSE */ 102 #define DCORE0_VDEC0_BRDG_CTRL_HBW_AXI_VIOL_CAUSE_AWLEN_GT_31_SHIFT 0 103 #define DCORE0_VDEC0_BRDG_CTRL_HBW_AXI_VIOL_CAUSE_AWLEN_GT_31_MASK 0x1 104 #define DCORE0_VDEC0_BRDG_CTRL_HBW_AXI_VIOL_CAUSE_AWLOCK_VIOL_SHIFT 1 105 #define DCORE0_VDEC0_BRDG_CTRL_HBW_AXI_VIOL_CAUSE_AWLOCK_VIOL_MASK 0x2 106 #define DCORE0_VDEC0_BRDG_CTRL_HBW_AXI_VIOL_CAUSE_AWBURST_VIOL_SHIFT 2 107 #define DCORE0_VDEC0_BRDG_CTRL_HBW_AXI_VIOL_CAUSE_AWBURST_VIOL_MASK 0x4 108 #define DCORE0_VDEC0_BRDG_CTRL_HBW_AXI_VIOL_CAUSE_AWADDR_SIZE_ALIGN_VIOL_SHIFT 3 109 #define DCORE0_VDEC0_BRDG_CTRL_HBW_AXI_VIOL_CAUSE_AWADDR_SIZE_ALIGN_VIOL_MASK 0x8 110 #define DCORE0_VDEC0_BRDG_CTRL_HBW_AXI_VIOL_CAUSE_AWSIZE_VIOL_SHIFT 4 111 #define DCORE0_VDEC0_BRDG_CTRL_HBW_AXI_VIOL_CAUSE_AWSIZE_VIOL_MASK 0x10 112 #define DCORE0_VDEC0_BRDG_CTRL_HBW_AXI_VIOL_CAUSE_ARLEN_GT_31_SHIFT 5 113 #define DCORE0_VDEC0_BRDG_CTRL_HBW_AXI_VIOL_CAUSE_ARLEN_GT_31_MASK 0x20 114 #define DCORE0_VDEC0_BRDG_CTRL_HBW_AXI_VIOL_CAUSE_ARLOCK_VIOL_SHIFT 6 115 #define DCORE0_VDEC0_BRDG_CTRL_HBW_AXI_VIOL_CAUSE_ARLOCK_VIOL_MASK 0x40 116 #define DCORE0_VDEC0_BRDG_CTRL_HBW_AXI_VIOL_CAUSE_ARBURST_VIOL_SHIFT 7 117 #define DCORE0_VDEC0_BRDG_CTRL_HBW_AXI_VIOL_CAUSE_ARBURST_VIOL_MASK 0x80 118 #define DCORE0_VDEC0_BRDG_CTRL_HBW_AXI_VIOL_CAUSE_ARADDR_SIZE_ALIGN_VIOL_SHIFT 8 119 #define DCORE0_VDEC0_BRDG_CTRL_HBW_AXI_VIOL_CAUSE_ARADDR_SIZE_ALIGN_VIOL_MASK 0x100 120 #define DCORE0_VDEC0_BRDG_CTRL_HBW_AXI_VIOL_CAUSE_ARSIZE_VIOL_SHIFT 9 121 #define DCORE0_VDEC0_BRDG_CTRL_HBW_AXI_VIOL_CAUSE_ARSIZE_VIOL_MASK 0x200 122 123 /* DCORE0_VDEC0_BRDG_CTRL_LBW_AXI_VIOL_CAUSE */ 124 #define DCORE0_VDEC0_BRDG_CTRL_LBW_AXI_VIOL_CAUSE_READ_ACCESS_VIOL_SHIFT 0 125 #define DCORE0_VDEC0_BRDG_CTRL_LBW_AXI_VIOL_CAUSE_READ_ACCESS_VIOL_MASK 0x1 126 #define DCORE0_VDEC0_BRDG_CTRL_LBW_AXI_VIOL_CAUSE_AWLOCK_VIOL_SHIFT 1 127 #define DCORE0_VDEC0_BRDG_CTRL_LBW_AXI_VIOL_CAUSE_AWLOCK_VIOL_MASK 0x2 128 #define DCORE0_VDEC0_BRDG_CTRL_LBW_AXI_VIOL_CAUSE_AWADDR_ALIGN_VIOL_SHIFT 2 129 #define DCORE0_VDEC0_BRDG_CTRL_LBW_AXI_VIOL_CAUSE_AWADDR_ALIGN_VIOL_MASK 0x4 130 #define DCORE0_VDEC0_BRDG_CTRL_LBW_AXI_VIOL_CAUSE_AWSIZE_VIOL_SHIFT 3 131 #define DCORE0_VDEC0_BRDG_CTRL_LBW_AXI_VIOL_CAUSE_AWSIZE_VIOL_MASK 0x8 132 #define DCORE0_VDEC0_BRDG_CTRL_LBW_AXI_VIOL_CAUSE_AWLEN_VIOL_SHIFT 4 133 #define DCORE0_VDEC0_BRDG_CTRL_LBW_AXI_VIOL_CAUSE_AWLEN_VIOL_MASK 0x10 134 #define DCORE0_VDEC0_BRDG_CTRL_LBW_AXI_VIOL_CAUSE_WSTRB_VIOL_SHIFT 5 135 #define DCORE0_VDEC0_BRDG_CTRL_LBW_AXI_VIOL_CAUSE_WSTRB_VIOL_MASK 0x20 136 137 /* DCORE0_VDEC0_BRDG_CTRL_AXI_VIOL_CLR_STICKY_TERM */ 138 #define DCORE0_VDEC0_BRDG_CTRL_AXI_VIOL_CLR_STICKY_TERM_HBW_AW_VIOL_CLR_SHIFT 0 139 #define DCORE0_VDEC0_BRDG_CTRL_AXI_VIOL_CLR_STICKY_TERM_HBW_AW_VIOL_CLR_MASK 0x1 140 #define DCORE0_VDEC0_BRDG_CTRL_AXI_VIOL_CLR_STICKY_TERM_HBW_AR_VIOL_CLR_SHIFT 1 141 #define DCORE0_VDEC0_BRDG_CTRL_AXI_VIOL_CLR_STICKY_TERM_HBW_AR_VIOL_CLR_MASK 0x2 142 #define DCORE0_VDEC0_BRDG_CTRL_AXI_VIOL_CLR_STICKY_TERM_LBW_AW_VIOL_CLR_SHIFT 2 143 #define DCORE0_VDEC0_BRDG_CTRL_AXI_VIOL_CLR_STICKY_TERM_LBW_AW_VIOL_CLR_MASK 0x4 144 145 /* DCORE0_VDEC0_BRDG_CTRL_CAUSE_INTR_MASK */ 146 #define DCORE0_VDEC0_BRDG_CTRL_CAUSE_INTR_MASK_VAL_SHIFT 0 147 #define DCORE0_VDEC0_BRDG_CTRL_CAUSE_INTR_MASK_VAL_MASK 0xFFFFFFFF 148 149 /* DCORE0_VDEC0_BRDG_CTRL_HBW_AXI_VIOL_MASK */ 150 #define DCORE0_VDEC0_BRDG_CTRL_HBW_AXI_VIOL_MASK_MASK_SHIFT 0 151 #define DCORE0_VDEC0_BRDG_CTRL_HBW_AXI_VIOL_MASK_MASK_MASK 0xFFFFFFFF 152 153 /* DCORE0_VDEC0_BRDG_CTRL_LBW_AXI_VIOL_MASK */ 154 #define DCORE0_VDEC0_BRDG_CTRL_LBW_AXI_VIOL_MASK_MASK_SHIFT 0 155 #define DCORE0_VDEC0_BRDG_CTRL_LBW_AXI_VIOL_MASK_MASK_MASK 0xFFFFFFFF 156 157 /* DCORE0_VDEC0_BRDG_CTRL_VCD_GIC_INTR_MASK */ 158 #define DCORE0_VDEC0_BRDG_CTRL_VCD_GIC_INTR_MASK_VAL_SHIFT 0 159 #define DCORE0_VDEC0_BRDG_CTRL_VCD_GIC_INTR_MASK_VAL_MASK 0x1 160 161 /* DCORE0_VDEC0_BRDG_CTRL_L2C_GIC_INTR_MASK */ 162 #define DCORE0_VDEC0_BRDG_CTRL_L2C_GIC_INTR_MASK_VAL_SHIFT 0 163 #define DCORE0_VDEC0_BRDG_CTRL_L2C_GIC_INTR_MASK_VAL_MASK 0x1 164 165 /* DCORE0_VDEC0_BRDG_CTRL_NRM_GIC_INTR_MASK */ 166 #define DCORE0_VDEC0_BRDG_CTRL_NRM_GIC_INTR_MASK_VAL_SHIFT 0 167 #define DCORE0_VDEC0_BRDG_CTRL_NRM_GIC_INTR_MASK_VAL_MASK 0x1 168 169 /* DCORE0_VDEC0_BRDG_CTRL_ABNRM_GIC_INTR_MASK */ 170 #define DCORE0_VDEC0_BRDG_CTRL_ABNRM_GIC_INTR_MASK_VAL_SHIFT 0 171 #define DCORE0_VDEC0_BRDG_CTRL_ABNRM_GIC_INTR_MASK_VAL_MASK 0x1 172 173 /* DCORE0_VDEC0_BRDG_CTRL_DEC_HBW_AWPROT */ 174 #define DCORE0_VDEC0_BRDG_CTRL_DEC_HBW_AWPROT_VAL_SHIFT 0 175 #define DCORE0_VDEC0_BRDG_CTRL_DEC_HBW_AWPROT_VAL_MASK 0x7 176 177 /* DCORE0_VDEC0_BRDG_CTRL_DEC_HBW_ARPROT */ 178 #define DCORE0_VDEC0_BRDG_CTRL_DEC_HBW_ARPROT_VAL_SHIFT 0 179 #define DCORE0_VDEC0_BRDG_CTRL_DEC_HBW_ARPROT_VAL_MASK 0x7 180 181 /* DCORE0_VDEC0_BRDG_CTRL_DEC_LBW_AWPROT */ 182 #define DCORE0_VDEC0_BRDG_CTRL_DEC_LBW_AWPROT_VAL_SHIFT 0 183 #define DCORE0_VDEC0_BRDG_CTRL_DEC_LBW_AWPROT_VAL_MASK 0x7 184 185 /* DCORE0_VDEC0_BRDG_CTRL_DEC_LBW_ARPROT */ 186 #define DCORE0_VDEC0_BRDG_CTRL_DEC_LBW_ARPROT_VAL_SHIFT 0 187 #define DCORE0_VDEC0_BRDG_CTRL_DEC_LBW_ARPROT_VAL_MASK 0x7 188 189 /* DCORE0_VDEC0_BRDG_CTRL_DEC_LBW_SLV_AWPROT */ 190 #define DCORE0_VDEC0_BRDG_CTRL_DEC_LBW_SLV_AWPROT_VAL_SHIFT 0 191 #define DCORE0_VDEC0_BRDG_CTRL_DEC_LBW_SLV_AWPROT_VAL_MASK 0x7 192 193 /* DCORE0_VDEC0_BRDG_CTRL_DEC_LBW_SLV_ARPROT */ 194 #define DCORE0_VDEC0_BRDG_CTRL_DEC_LBW_SLV_ARPROT_VAL_SHIFT 0 195 #define DCORE0_VDEC0_BRDG_CTRL_DEC_LBW_SLV_ARPROT_VAL_MASK 0x7 196 197 /* DCORE0_VDEC0_BRDG_CTRL_DEC_AXI_LEGAL_AXSIZE */ 198 #define DCORE0_VDEC0_BRDG_CTRL_DEC_AXI_LEGAL_AXSIZE_HBW_LEGAL_AWSIZE_SHIFT 0 199 #define DCORE0_VDEC0_BRDG_CTRL_DEC_AXI_LEGAL_AXSIZE_HBW_LEGAL_AWSIZE_MASK 0x7 200 #define DCORE0_VDEC0_BRDG_CTRL_DEC_AXI_LEGAL_AXSIZE_HBW_LEGAL_ARSIZE_SHIFT 3 201 #define DCORE0_VDEC0_BRDG_CTRL_DEC_AXI_LEGAL_AXSIZE_HBW_LEGAL_ARSIZE_MASK 0x38 202 #define DCORE0_VDEC0_BRDG_CTRL_DEC_AXI_LEGAL_AXSIZE_LBW_LEGAL_AWSIZE_SHIFT 6 203 #define DCORE0_VDEC0_BRDG_CTRL_DEC_AXI_LEGAL_AXSIZE_LBW_LEGAL_AWSIZE_MASK 0x1C0 204 205 /* DCORE0_VDEC0_BRDG_CTRL_ARC_MSG_MASK */ 206 #define DCORE0_VDEC0_BRDG_CTRL_ARC_MSG_MASK_VAL_SHIFT 0 207 #define DCORE0_VDEC0_BRDG_CTRL_ARC_MSG_MASK_VAL_MASK 0x1 208 209 /* DCORE0_VDEC0_BRDG_CTRL_ARC_START_LBW_WDATA */ 210 #define DCORE0_VDEC0_BRDG_CTRL_ARC_START_LBW_WDATA_VAL_SHIFT 0 211 #define DCORE0_VDEC0_BRDG_CTRL_ARC_START_LBW_WDATA_VAL_MASK 0xFF 212 213 /* DCORE0_VDEC0_BRDG_CTRL_ARC_FINISH_LBW_WDATA */ 214 #define DCORE0_VDEC0_BRDG_CTRL_ARC_FINISH_LBW_WDATA_VAL_SHIFT 0 215 #define DCORE0_VDEC0_BRDG_CTRL_ARC_FINISH_LBW_WDATA_VAL_MASK 0xFF 216 217 /* DCORE0_VDEC0_BRDG_CTRL_HWEVENT_TRACE_SEL */ 218 #define DCORE0_VDEC0_BRDG_CTRL_HWEVENT_TRACE_SEL_VAL_SHIFT 0 219 #define DCORE0_VDEC0_BRDG_CTRL_HWEVENT_TRACE_SEL_VAL_MASK 0x7 220 221 /* DCORE0_VDEC0_BRDG_CTRL_HWEVENT_TRACE_ADDR */ 222 #define DCORE0_VDEC0_BRDG_CTRL_HWEVENT_TRACE_ADDR_VAL_SHIFT 0 223 #define DCORE0_VDEC0_BRDG_CTRL_HWEVENT_TRACE_ADDR_VAL_MASK 0xFFFFFFFF 224 225 /* DCORE0_VDEC0_BRDG_CTRL_DEC_FREE_RUN_CNT_L */ 226 #define DCORE0_VDEC0_BRDG_CTRL_DEC_FREE_RUN_CNT_L_VAL_SHIFT 0 227 #define DCORE0_VDEC0_BRDG_CTRL_DEC_FREE_RUN_CNT_L_VAL_MASK 0xFFFFFFFF 228 229 /* DCORE0_VDEC0_BRDG_CTRL_DEC_FREE_RUN_CNT_H */ 230 #define DCORE0_VDEC0_BRDG_CTRL_DEC_FREE_RUN_CNT_H_VAL_SHIFT 0 231 #define DCORE0_VDEC0_BRDG_CTRL_DEC_FREE_RUN_CNT_H_VAL_MASK 0xFFFFFFFF 232 233 /* DCORE0_VDEC0_BRDG_CTRL_DEC_FREE_RUN_SET_VALUE_L */ 234 #define DCORE0_VDEC0_BRDG_CTRL_DEC_FREE_RUN_SET_VALUE_L_IND_SHIFT 0 235 #define DCORE0_VDEC0_BRDG_CTRL_DEC_FREE_RUN_SET_VALUE_L_IND_MASK 0xFFFFFFFF 236 237 /* DCORE0_VDEC0_BRDG_CTRL_DEC_FREE_RUN_SET_VALUE_H */ 238 #define DCORE0_VDEC0_BRDG_CTRL_DEC_FREE_RUN_SET_VALUE_H_IND_SHIFT 0 239 #define DCORE0_VDEC0_BRDG_CTRL_DEC_FREE_RUN_SET_VALUE_H_IND_MASK 0xFFFFFFFF 240 241 /* DCORE0_VDEC0_BRDG_CTRL_DEC_BUSY_CNT_L */ 242 #define DCORE0_VDEC0_BRDG_CTRL_DEC_BUSY_CNT_L_VAL_SHIFT 0 243 #define DCORE0_VDEC0_BRDG_CTRL_DEC_BUSY_CNT_L_VAL_MASK 0xFFFFFFFF 244 245 /* DCORE0_VDEC0_BRDG_CTRL_DEC_BUSY_CNT_H */ 246 #define DCORE0_VDEC0_BRDG_CTRL_DEC_BUSY_CNT_H_VAL_SHIFT 0 247 #define DCORE0_VDEC0_BRDG_CTRL_DEC_BUSY_CNT_H_VAL_MASK 0xFFFFFFFF 248 249 /* DCORE0_VDEC0_BRDG_CTRL_DEC_BUSY_SET_VALUE_L */ 250 #define DCORE0_VDEC0_BRDG_CTRL_DEC_BUSY_SET_VALUE_L_IND_SHIFT 0 251 #define DCORE0_VDEC0_BRDG_CTRL_DEC_BUSY_SET_VALUE_L_IND_MASK 0xFFFFFFFF 252 253 /* DCORE0_VDEC0_BRDG_CTRL_DEC_BUSY_SET_VALUE_H */ 254 #define DCORE0_VDEC0_BRDG_CTRL_DEC_BUSY_SET_VALUE_H_IND_SHIFT 0 255 #define DCORE0_VDEC0_BRDG_CTRL_DEC_BUSY_SET_VALUE_H_IND_MASK 0xFFFFFFFF 256 257 /* DCORE0_VDEC0_BRDG_CTRL_STAT_CNTR_EN */ 258 #define DCORE0_VDEC0_BRDG_CTRL_STAT_CNTR_EN_VAL_SHIFT 0 259 #define DCORE0_VDEC0_BRDG_CTRL_STAT_CNTR_EN_VAL_MASK 0x1 260 261 /* DCORE0_VDEC0_BRDG_CTRL_VCD_INTR_MASK */ 262 #define DCORE0_VDEC0_BRDG_CTRL_VCD_INTR_MASK_VAL_SHIFT 0 263 #define DCORE0_VDEC0_BRDG_CTRL_VCD_INTR_MASK_VAL_MASK 0x1 264 265 /* DCORE0_VDEC0_BRDG_CTRL_VCD_MSIX_FLOW_MASK */ 266 #define DCORE0_VDEC0_BRDG_CTRL_VCD_MSIX_FLOW_MASK_APB_WR_SHIFT 0 267 #define DCORE0_VDEC0_BRDG_CTRL_VCD_MSIX_FLOW_MASK_APB_WR_MASK 0x1 268 #define DCORE0_VDEC0_BRDG_CTRL_VCD_MSIX_FLOW_MASK_APB_RD_SHIFT 1 269 #define DCORE0_VDEC0_BRDG_CTRL_VCD_MSIX_FLOW_MASK_APB_RD_MASK 0x2 270 #define DCORE0_VDEC0_BRDG_CTRL_VCD_MSIX_FLOW_MASK_LBW_SHIFT 2 271 #define DCORE0_VDEC0_BRDG_CTRL_VCD_MSIX_FLOW_MASK_LBW_MASK 0x4 272 273 /* DCORE0_VDEC0_BRDG_CTRL_VCD_WAIT_CNTR */ 274 #define DCORE0_VDEC0_BRDG_CTRL_VCD_WAIT_CNTR_VAL_SHIFT 0 275 #define DCORE0_VDEC0_BRDG_CTRL_VCD_WAIT_CNTR_VAL_MASK 0xFFFFFF 276 277 /* DCORE0_VDEC0_BRDG_CTRL_VCD_MSIX_WAIT_CNTR */ 278 #define DCORE0_VDEC0_BRDG_CTRL_VCD_MSIX_WAIT_CNTR_VAL_SHIFT 0 279 #define DCORE0_VDEC0_BRDG_CTRL_VCD_MSIX_WAIT_CNTR_VAL_MASK 0xFFFFFF 280 281 /* DCORE0_VDEC0_BRDG_CTRL_STAT_VCD_WAIT_CNTR */ 282 #define DCORE0_VDEC0_BRDG_CTRL_STAT_VCD_WAIT_CNTR_VAL_SHIFT 0 283 #define DCORE0_VDEC0_BRDG_CTRL_STAT_VCD_WAIT_CNTR_VAL_MASK 0xFFFFFF 284 285 /* DCORE0_VDEC0_BRDG_CTRL_STAT_VCD_MSIX_WAIT_CNTR */ 286 #define DCORE0_VDEC0_BRDG_CTRL_STAT_VCD_MSIX_WAIT_CNTR_VAL_SHIFT 0 287 #define DCORE0_VDEC0_BRDG_CTRL_STAT_VCD_MSIX_WAIT_CNTR_VAL_MASK 0xFFFFFF 288 289 /* DCORE0_VDEC0_BRDG_CTRL_VCD_SWREG1_ADDR */ 290 #define DCORE0_VDEC0_BRDG_CTRL_VCD_SWREG1_ADDR_VAL_SHIFT 0 291 #define DCORE0_VDEC0_BRDG_CTRL_VCD_SWREG1_ADDR_VAL_MASK 0xFFFFFFFF 292 293 /* DCORE0_VDEC0_BRDG_CTRL_VCD_APB_WR_ADDR */ 294 #define DCORE0_VDEC0_BRDG_CTRL_VCD_APB_WR_ADDR_VAL_SHIFT 0 295 #define DCORE0_VDEC0_BRDG_CTRL_VCD_APB_WR_ADDR_VAL_MASK 0xFFFFFFFF 296 297 /* DCORE0_VDEC0_BRDG_CTRL_VCD_APB_WR_DATA */ 298 #define DCORE0_VDEC0_BRDG_CTRL_VCD_APB_WR_DATA_VAL_SHIFT 0 299 #define DCORE0_VDEC0_BRDG_CTRL_VCD_APB_WR_DATA_VAL_MASK 0xFFFFFFFF 300 301 /* DCORE0_VDEC0_BRDG_CTRL_VCD_CPLQ_HBW_AWPROT */ 302 #define DCORE0_VDEC0_BRDG_CTRL_VCD_CPLQ_HBW_AWPROT_VAL_SHIFT 0 303 #define DCORE0_VDEC0_BRDG_CTRL_VCD_CPLQ_HBW_AWPROT_VAL_MASK 0x7 304 305 /* DCORE0_VDEC0_BRDG_CTRL_VCD_CPLQ_HBW_AWADDR_L */ 306 #define DCORE0_VDEC0_BRDG_CTRL_VCD_CPLQ_HBW_AWADDR_L_VAL_SHIFT 0 307 #define DCORE0_VDEC0_BRDG_CTRL_VCD_CPLQ_HBW_AWADDR_L_VAL_MASK 0xFFFFFFFF 308 309 /* DCORE0_VDEC0_BRDG_CTRL_VCD_CPLQ_HBW_AWADDR_H */ 310 #define DCORE0_VDEC0_BRDG_CTRL_VCD_CPLQ_HBW_AWADDR_H_VAL_SHIFT 0 311 #define DCORE0_VDEC0_BRDG_CTRL_VCD_CPLQ_HBW_AWADDR_H_VAL_MASK 0xFFFFFFFF 312 313 /* DCORE0_VDEC0_BRDG_CTRL_VCD_MSIX_LBW_AWPROT */ 314 #define DCORE0_VDEC0_BRDG_CTRL_VCD_MSIX_LBW_AWPROT_VAL_SHIFT 0 315 #define DCORE0_VDEC0_BRDG_CTRL_VCD_MSIX_LBW_AWPROT_VAL_MASK 0x7 316 317 /* DCORE0_VDEC0_BRDG_CTRL_VCD_MSIX_LBW_AWADDR */ 318 #define DCORE0_VDEC0_BRDG_CTRL_VCD_MSIX_LBW_AWADDR_VAL_SHIFT 0 319 #define DCORE0_VDEC0_BRDG_CTRL_VCD_MSIX_LBW_AWADDR_VAL_MASK 0xFFFFFFFF 320 321 /* DCORE0_VDEC0_BRDG_CTRL_VCD_MSIX_LBW_WDATA */ 322 #define DCORE0_VDEC0_BRDG_CTRL_VCD_MSIX_LBW_WDATA_VAL_SHIFT 0 323 #define DCORE0_VDEC0_BRDG_CTRL_VCD_MSIX_LBW_WDATA_VAL_MASK 0xFFFFFFFF 324 325 /* DCORE0_VDEC0_BRDG_CTRL_L2C_INTR_MASK */ 326 #define DCORE0_VDEC0_BRDG_CTRL_L2C_INTR_MASK_VAL_SHIFT 0 327 #define DCORE0_VDEC0_BRDG_CTRL_L2C_INTR_MASK_VAL_MASK 0x1 328 329 /* DCORE0_VDEC0_BRDG_CTRL_L2C_MSIX_FLOW_MASK */ 330 #define DCORE0_VDEC0_BRDG_CTRL_L2C_MSIX_FLOW_MASK_APB_WR_SHIFT 0 331 #define DCORE0_VDEC0_BRDG_CTRL_L2C_MSIX_FLOW_MASK_APB_WR_MASK 0x1 332 #define DCORE0_VDEC0_BRDG_CTRL_L2C_MSIX_FLOW_MASK_APB_RD_SHIFT 1 333 #define DCORE0_VDEC0_BRDG_CTRL_L2C_MSIX_FLOW_MASK_APB_RD_MASK 0x2 334 #define DCORE0_VDEC0_BRDG_CTRL_L2C_MSIX_FLOW_MASK_LBW_SHIFT 2 335 #define DCORE0_VDEC0_BRDG_CTRL_L2C_MSIX_FLOW_MASK_LBW_MASK 0x4 336 337 /* DCORE0_VDEC0_BRDG_CTRL_L2C_WAIT_CNTR */ 338 #define DCORE0_VDEC0_BRDG_CTRL_L2C_WAIT_CNTR_VAL_SHIFT 0 339 #define DCORE0_VDEC0_BRDG_CTRL_L2C_WAIT_CNTR_VAL_MASK 0xFFFFFF 340 341 /* DCORE0_VDEC0_BRDG_CTRL_L2C_MSIX_WAIT_CNTR */ 342 #define DCORE0_VDEC0_BRDG_CTRL_L2C_MSIX_WAIT_CNTR_VAL_SHIFT 0 343 #define DCORE0_VDEC0_BRDG_CTRL_L2C_MSIX_WAIT_CNTR_VAL_MASK 0xFFFFFF 344 345 /* DCORE0_VDEC0_BRDG_CTRL_STAT_L2C_WAIT_CNTR */ 346 #define DCORE0_VDEC0_BRDG_CTRL_STAT_L2C_WAIT_CNTR_VAL_SHIFT 0 347 #define DCORE0_VDEC0_BRDG_CTRL_STAT_L2C_WAIT_CNTR_VAL_MASK 0xFFFFFF 348 349 /* DCORE0_VDEC0_BRDG_CTRL_STAT_L2C_MSIX_WAIT_CNTR */ 350 #define DCORE0_VDEC0_BRDG_CTRL_STAT_L2C_MSIX_WAIT_CNTR_VAL_SHIFT 0 351 #define DCORE0_VDEC0_BRDG_CTRL_STAT_L2C_MSIX_WAIT_CNTR_VAL_MASK 0xFFFFFF 352 353 /* DCORE0_VDEC0_BRDG_CTRL_L2C_SWREG1_ADDR */ 354 #define DCORE0_VDEC0_BRDG_CTRL_L2C_SWREG1_ADDR_VAL_SHIFT 0 355 #define DCORE0_VDEC0_BRDG_CTRL_L2C_SWREG1_ADDR_VAL_MASK 0xFFFFFFFF 356 357 /* DCORE0_VDEC0_BRDG_CTRL_L2C_APB_WR_ADDR */ 358 #define DCORE0_VDEC0_BRDG_CTRL_L2C_APB_WR_ADDR_VAL_SHIFT 0 359 #define DCORE0_VDEC0_BRDG_CTRL_L2C_APB_WR_ADDR_VAL_MASK 0xFFFFFFFF 360 361 /* DCORE0_VDEC0_BRDG_CTRL_L2C_APB_WR_DATA */ 362 #define DCORE0_VDEC0_BRDG_CTRL_L2C_APB_WR_DATA_VAL_SHIFT 0 363 #define DCORE0_VDEC0_BRDG_CTRL_L2C_APB_WR_DATA_VAL_MASK 0xFFFFFFFF 364 365 /* DCORE0_VDEC0_BRDG_CTRL_L2C_CPLQ_HBW_AWPROT */ 366 #define DCORE0_VDEC0_BRDG_CTRL_L2C_CPLQ_HBW_AWPROT_VAL_SHIFT 0 367 #define DCORE0_VDEC0_BRDG_CTRL_L2C_CPLQ_HBW_AWPROT_VAL_MASK 0x7 368 369 /* DCORE0_VDEC0_BRDG_CTRL_L2C_CPLQ_HBW_AWADDR_L */ 370 #define DCORE0_VDEC0_BRDG_CTRL_L2C_CPLQ_HBW_AWADDR_L_VAL_SHIFT 0 371 #define DCORE0_VDEC0_BRDG_CTRL_L2C_CPLQ_HBW_AWADDR_L_VAL_MASK 0xFFFFFFFF 372 373 /* DCORE0_VDEC0_BRDG_CTRL_L2C_CPLQ_HBW_AWADDR_H */ 374 #define DCORE0_VDEC0_BRDG_CTRL_L2C_CPLQ_HBW_AWADDR_H_VAL_SHIFT 0 375 #define DCORE0_VDEC0_BRDG_CTRL_L2C_CPLQ_HBW_AWADDR_H_VAL_MASK 0xFFFFFFFF 376 377 /* DCORE0_VDEC0_BRDG_CTRL_L2C_MSIX_LBW_AWPROT */ 378 #define DCORE0_VDEC0_BRDG_CTRL_L2C_MSIX_LBW_AWPROT_VAL_SHIFT 0 379 #define DCORE0_VDEC0_BRDG_CTRL_L2C_MSIX_LBW_AWPROT_VAL_MASK 0x7 380 381 /* DCORE0_VDEC0_BRDG_CTRL_L2C_MSIX_LBW_AWADDR */ 382 #define DCORE0_VDEC0_BRDG_CTRL_L2C_MSIX_LBW_AWADDR_VAL_SHIFT 0 383 #define DCORE0_VDEC0_BRDG_CTRL_L2C_MSIX_LBW_AWADDR_VAL_MASK 0xFFFFFFFF 384 385 /* DCORE0_VDEC0_BRDG_CTRL_L2C_MSIX_LBW_WDATA */ 386 #define DCORE0_VDEC0_BRDG_CTRL_L2C_MSIX_LBW_WDATA_VAL_SHIFT 0 387 #define DCORE0_VDEC0_BRDG_CTRL_L2C_MSIX_LBW_WDATA_VAL_MASK 0xFFFFFFFF 388 389 /* DCORE0_VDEC0_BRDG_CTRL_NRM_INTR_MASK */ 390 #define DCORE0_VDEC0_BRDG_CTRL_NRM_INTR_MASK_VAL_SHIFT 0 391 #define DCORE0_VDEC0_BRDG_CTRL_NRM_INTR_MASK_VAL_MASK 0x1 392 393 /* DCORE0_VDEC0_BRDG_CTRL_NRM_MSIX_FLOW_MASK */ 394 #define DCORE0_VDEC0_BRDG_CTRL_NRM_MSIX_FLOW_MASK_APB_WR_SHIFT 0 395 #define DCORE0_VDEC0_BRDG_CTRL_NRM_MSIX_FLOW_MASK_APB_WR_MASK 0x1 396 #define DCORE0_VDEC0_BRDG_CTRL_NRM_MSIX_FLOW_MASK_APB_RD_SHIFT 1 397 #define DCORE0_VDEC0_BRDG_CTRL_NRM_MSIX_FLOW_MASK_APB_RD_MASK 0x2 398 #define DCORE0_VDEC0_BRDG_CTRL_NRM_MSIX_FLOW_MASK_LBW_SHIFT 2 399 #define DCORE0_VDEC0_BRDG_CTRL_NRM_MSIX_FLOW_MASK_LBW_MASK 0x4 400 401 /* DCORE0_VDEC0_BRDG_CTRL_NRM_WAIT_CNTR */ 402 #define DCORE0_VDEC0_BRDG_CTRL_NRM_WAIT_CNTR_VAL_SHIFT 0 403 #define DCORE0_VDEC0_BRDG_CTRL_NRM_WAIT_CNTR_VAL_MASK 0xFFFFFF 404 405 /* DCORE0_VDEC0_BRDG_CTRL_NRM_MSIX_WAIT_CNTR */ 406 #define DCORE0_VDEC0_BRDG_CTRL_NRM_MSIX_WAIT_CNTR_VAL_SHIFT 0 407 #define DCORE0_VDEC0_BRDG_CTRL_NRM_MSIX_WAIT_CNTR_VAL_MASK 0xFFFFFF 408 409 /* DCORE0_VDEC0_BRDG_CTRL_STAT_NRM_WAIT_CNTR */ 410 #define DCORE0_VDEC0_BRDG_CTRL_STAT_NRM_WAIT_CNTR_VAL_SHIFT 0 411 #define DCORE0_VDEC0_BRDG_CTRL_STAT_NRM_WAIT_CNTR_VAL_MASK 0xFFFFFF 412 413 /* DCORE0_VDEC0_BRDG_CTRL_STAT_NRM_MSIX_WAIT_CNTR */ 414 #define DCORE0_VDEC0_BRDG_CTRL_STAT_NRM_MSIX_WAIT_CNTR_VAL_SHIFT 0 415 #define DCORE0_VDEC0_BRDG_CTRL_STAT_NRM_MSIX_WAIT_CNTR_VAL_MASK 0xFFFFFF 416 417 /* DCORE0_VDEC0_BRDG_CTRL_NRM_SWREG1_ADDR */ 418 #define DCORE0_VDEC0_BRDG_CTRL_NRM_SWREG1_ADDR_VAL_SHIFT 0 419 #define DCORE0_VDEC0_BRDG_CTRL_NRM_SWREG1_ADDR_VAL_MASK 0xFFFFFFFF 420 421 /* DCORE0_VDEC0_BRDG_CTRL_NRM_APB_WR_ADDR */ 422 #define DCORE0_VDEC0_BRDG_CTRL_NRM_APB_WR_ADDR_VAL_SHIFT 0 423 #define DCORE0_VDEC0_BRDG_CTRL_NRM_APB_WR_ADDR_VAL_MASK 0xFFFFFFFF 424 425 /* DCORE0_VDEC0_BRDG_CTRL_NRM_APB_WR_DATA */ 426 #define DCORE0_VDEC0_BRDG_CTRL_NRM_APB_WR_DATA_VAL_SHIFT 0 427 #define DCORE0_VDEC0_BRDG_CTRL_NRM_APB_WR_DATA_VAL_MASK 0xFFFFFFFF 428 429 /* DCORE0_VDEC0_BRDG_CTRL_NRM_CPLQ_HBW_AWPROT */ 430 #define DCORE0_VDEC0_BRDG_CTRL_NRM_CPLQ_HBW_AWPROT_VAL_SHIFT 0 431 #define DCORE0_VDEC0_BRDG_CTRL_NRM_CPLQ_HBW_AWPROT_VAL_MASK 0x7 432 433 /* DCORE0_VDEC0_BRDG_CTRL_NRM_CPLQ_HBW_AWADDR_L */ 434 #define DCORE0_VDEC0_BRDG_CTRL_NRM_CPLQ_HBW_AWADDR_L_VAL_SHIFT 0 435 #define DCORE0_VDEC0_BRDG_CTRL_NRM_CPLQ_HBW_AWADDR_L_VAL_MASK 0xFFFFFFFF 436 437 /* DCORE0_VDEC0_BRDG_CTRL_NRM_CPLQ_HBW_AWADDR_H */ 438 #define DCORE0_VDEC0_BRDG_CTRL_NRM_CPLQ_HBW_AWADDR_H_VAL_SHIFT 0 439 #define DCORE0_VDEC0_BRDG_CTRL_NRM_CPLQ_HBW_AWADDR_H_VAL_MASK 0xFFFFFFFF 440 441 /* DCORE0_VDEC0_BRDG_CTRL_NRM_MSIX_LBW_AWPROT */ 442 #define DCORE0_VDEC0_BRDG_CTRL_NRM_MSIX_LBW_AWPROT_VAL_SHIFT 0 443 #define DCORE0_VDEC0_BRDG_CTRL_NRM_MSIX_LBW_AWPROT_VAL_MASK 0x7 444 445 /* DCORE0_VDEC0_BRDG_CTRL_NRM_MSIX_LBW_AWADDR */ 446 #define DCORE0_VDEC0_BRDG_CTRL_NRM_MSIX_LBW_AWADDR_VAL_SHIFT 0 447 #define DCORE0_VDEC0_BRDG_CTRL_NRM_MSIX_LBW_AWADDR_VAL_MASK 0xFFFFFFFF 448 449 /* DCORE0_VDEC0_BRDG_CTRL_NRM_MSIX_LBW_WDATA */ 450 #define DCORE0_VDEC0_BRDG_CTRL_NRM_MSIX_LBW_WDATA_VAL_SHIFT 0 451 #define DCORE0_VDEC0_BRDG_CTRL_NRM_MSIX_LBW_WDATA_VAL_MASK 0xFFFFFFFF 452 453 /* DCORE0_VDEC0_BRDG_CTRL_ABNRM_INTR_MASK */ 454 #define DCORE0_VDEC0_BRDG_CTRL_ABNRM_INTR_MASK_VAL_SHIFT 0 455 #define DCORE0_VDEC0_BRDG_CTRL_ABNRM_INTR_MASK_VAL_MASK 0x1 456 457 /* DCORE0_VDEC0_BRDG_CTRL_ABNRM_MSIX_FLOW_MASK */ 458 #define DCORE0_VDEC0_BRDG_CTRL_ABNRM_MSIX_FLOW_MASK_APB_WR_SHIFT 0 459 #define DCORE0_VDEC0_BRDG_CTRL_ABNRM_MSIX_FLOW_MASK_APB_WR_MASK 0x1 460 #define DCORE0_VDEC0_BRDG_CTRL_ABNRM_MSIX_FLOW_MASK_APB_RD_SHIFT 1 461 #define DCORE0_VDEC0_BRDG_CTRL_ABNRM_MSIX_FLOW_MASK_APB_RD_MASK 0x2 462 #define DCORE0_VDEC0_BRDG_CTRL_ABNRM_MSIX_FLOW_MASK_LBW_SHIFT 2 463 #define DCORE0_VDEC0_BRDG_CTRL_ABNRM_MSIX_FLOW_MASK_LBW_MASK 0x4 464 465 /* DCORE0_VDEC0_BRDG_CTRL_ABNRM_WAIT_CNTR */ 466 #define DCORE0_VDEC0_BRDG_CTRL_ABNRM_WAIT_CNTR_VAL_SHIFT 0 467 #define DCORE0_VDEC0_BRDG_CTRL_ABNRM_WAIT_CNTR_VAL_MASK 0xFFFFFF 468 469 /* DCORE0_VDEC0_BRDG_CTRL_ABNRM_MSIX_WAIT_CNTR */ 470 #define DCORE0_VDEC0_BRDG_CTRL_ABNRM_MSIX_WAIT_CNTR_VAL_SHIFT 0 471 #define DCORE0_VDEC0_BRDG_CTRL_ABNRM_MSIX_WAIT_CNTR_VAL_MASK 0xFFFFFF 472 473 /* DCORE0_VDEC0_BRDG_CTRL_STAT_ABNRM_WAIT_CNTR */ 474 #define DCORE0_VDEC0_BRDG_CTRL_STAT_ABNRM_WAIT_CNTR_VAL_SHIFT 0 475 #define DCORE0_VDEC0_BRDG_CTRL_STAT_ABNRM_WAIT_CNTR_VAL_MASK 0xFFFFFF 476 477 /* DCORE0_VDEC0_BRDG_CTRL_STAT_ABNRM_MSIX_WAIT_CNTR */ 478 #define DCORE0_VDEC0_BRDG_CTRL_STAT_ABNRM_MSIX_WAIT_CNTR_VAL_SHIFT 0 479 #define DCORE0_VDEC0_BRDG_CTRL_STAT_ABNRM_MSIX_WAIT_CNTR_VAL_MASK 0xFFFFFF 480 481 /* DCORE0_VDEC0_BRDG_CTRL_ABNRM_SWREG1_ADDR */ 482 #define DCORE0_VDEC0_BRDG_CTRL_ABNRM_SWREG1_ADDR_VAL_SHIFT 0 483 #define DCORE0_VDEC0_BRDG_CTRL_ABNRM_SWREG1_ADDR_VAL_MASK 0xFFFFFFFF 484 485 /* DCORE0_VDEC0_BRDG_CTRL_ABNRM_APB_WR_ADDR */ 486 #define DCORE0_VDEC0_BRDG_CTRL_ABNRM_APB_WR_ADDR_VAL_SHIFT 0 487 #define DCORE0_VDEC0_BRDG_CTRL_ABNRM_APB_WR_ADDR_VAL_MASK 0xFFFFFFFF 488 489 /* DCORE0_VDEC0_BRDG_CTRL_ABNRM_APB_WR_DATA */ 490 #define DCORE0_VDEC0_BRDG_CTRL_ABNRM_APB_WR_DATA_VAL_SHIFT 0 491 #define DCORE0_VDEC0_BRDG_CTRL_ABNRM_APB_WR_DATA_VAL_MASK 0xFFFFFFFF 492 493 /* DCORE0_VDEC0_BRDG_CTRL_ABNRM_CPLQ_HBW_AWPROT */ 494 #define DCORE0_VDEC0_BRDG_CTRL_ABNRM_CPLQ_HBW_AWPROT_VAL_SHIFT 0 495 #define DCORE0_VDEC0_BRDG_CTRL_ABNRM_CPLQ_HBW_AWPROT_VAL_MASK 0x7 496 497 /* DCORE0_VDEC0_BRDG_CTRL_ABNRM_CPLQ_HBW_AWADDR_L */ 498 #define DCORE0_VDEC0_BRDG_CTRL_ABNRM_CPLQ_HBW_AWADDR_L_VAL_SHIFT 0 499 #define DCORE0_VDEC0_BRDG_CTRL_ABNRM_CPLQ_HBW_AWADDR_L_VAL_MASK 0xFFFFFFFF 500 501 /* DCORE0_VDEC0_BRDG_CTRL_ABNRM_CPLQ_HBW_AWADDR_H */ 502 #define DCORE0_VDEC0_BRDG_CTRL_ABNRM_CPLQ_HBW_AWADDR_H_VAL_SHIFT 0 503 #define DCORE0_VDEC0_BRDG_CTRL_ABNRM_CPLQ_HBW_AWADDR_H_VAL_MASK 0xFFFFFFFF 504 505 /* DCORE0_VDEC0_BRDG_CTRL_ABNRM_MSIX_LBW_AWPROT */ 506 #define DCORE0_VDEC0_BRDG_CTRL_ABNRM_MSIX_LBW_AWPROT_VAL_SHIFT 0 507 #define DCORE0_VDEC0_BRDG_CTRL_ABNRM_MSIX_LBW_AWPROT_VAL_MASK 0x7 508 509 /* DCORE0_VDEC0_BRDG_CTRL_ABNRM_MSIX_LBW_AWADDR */ 510 #define DCORE0_VDEC0_BRDG_CTRL_ABNRM_MSIX_LBW_AWADDR_VAL_SHIFT 0 511 #define DCORE0_VDEC0_BRDG_CTRL_ABNRM_MSIX_LBW_AWADDR_VAL_MASK 0xFFFFFFFF 512 513 /* DCORE0_VDEC0_BRDG_CTRL_ABNRM_MSIX_LBW_WDATA */ 514 #define DCORE0_VDEC0_BRDG_CTRL_ABNRM_MSIX_LBW_WDATA_VAL_SHIFT 0 515 #define DCORE0_VDEC0_BRDG_CTRL_ABNRM_MSIX_LBW_WDATA_VAL_MASK 0xFFFFFFFF 516 517 /* DCORE0_VDEC0_BRDG_CTRL_AXI_SPLIT_BRESP_ERR_ID */ 518 #define DCORE0_VDEC0_BRDG_CTRL_AXI_SPLIT_BRESP_ERR_ID_ID_SHIFT 0 519 #define DCORE0_VDEC0_BRDG_CTRL_AXI_SPLIT_BRESP_ERR_ID_ID_MASK 0xFF 520 521 /* DCORE0_VDEC0_BRDG_CTRL_AXI_SPLIT_CFG */ 522 #define DCORE0_VDEC0_BRDG_CTRL_AXI_SPLIT_CFG_FORCE_RESP_OK_SHIFT 0 523 #define DCORE0_VDEC0_BRDG_CTRL_AXI_SPLIT_CFG_FORCE_RESP_OK_MASK 0x1 524 #define DCORE0_VDEC0_BRDG_CTRL_AXI_SPLIT_CFG_FORCE_WR_BUF_SHIFT 1 525 #define DCORE0_VDEC0_BRDG_CTRL_AXI_SPLIT_CFG_FORCE_WR_BUF_MASK 0x2 526 #define DCORE0_VDEC0_BRDG_CTRL_AXI_SPLIT_CFG_NUM_RD_OS_SHIFT 8 527 #define DCORE0_VDEC0_BRDG_CTRL_AXI_SPLIT_CFG_NUM_RD_OS_MASK 0xFF00 528 #define DCORE0_VDEC0_BRDG_CTRL_AXI_SPLIT_CFG_NUM_WR_OS_SHIFT 16 529 #define DCORE0_VDEC0_BRDG_CTRL_AXI_SPLIT_CFG_NUM_WR_OS_MASK 0xFF0000 530 531 /* DCORE0_VDEC0_BRDG_CTRL_AXI_SPLIT_NO_WR_INFLIGHT */ 532 #define DCORE0_VDEC0_BRDG_CTRL_AXI_SPLIT_NO_WR_INFLIGHT_VAL_SHIFT 0 533 #define DCORE0_VDEC0_BRDG_CTRL_AXI_SPLIT_NO_WR_INFLIGHT_VAL_MASK 0x1 534 535 /* DCORE0_VDEC0_BRDG_CTRL_HWEVENT_MASK */ 536 #define DCORE0_VDEC0_BRDG_CTRL_HWEVENT_MASK_MASK_SHIFT 1 537 #define DCORE0_VDEC0_BRDG_CTRL_HWEVENT_MASK_MASK_MASK 0x2 538 539 /* DCORE0_VDEC0_BRDG_CTRL_HWEVENT_CNTXT */ 540 #define DCORE0_VDEC0_BRDG_CTRL_HWEVENT_CNTXT_VAL_SHIFT 0 541 #define DCORE0_VDEC0_BRDG_CTRL_HWEVENT_CNTXT_VAL_MASK 0xFFFF 542 543 /* DCORE0_VDEC0_BRDG_CTRL_LBW_SLV_TERM_ERR_RESP */ 544 #define DCORE0_VDEC0_BRDG_CTRL_LBW_SLV_TERM_ERR_RESP_ERR_RESP_SHIFT 0 545 #define DCORE0_VDEC0_BRDG_CTRL_LBW_SLV_TERM_ERR_RESP_ERR_RESP_MASK 0x3 546 547 /* DCORE0_VDEC0_BRDG_CTRL_LBW_MSTR_TERM_ERR_RESP */ 548 #define DCORE0_VDEC0_BRDG_CTRL_LBW_MSTR_TERM_ERR_RESP_ERR_RESP_SHIFT 0 549 #define DCORE0_VDEC0_BRDG_CTRL_LBW_MSTR_TERM_ERR_RESP_ERR_RESP_MASK 0x3 550 551 /* DCORE0_VDEC0_BRDG_CTRL_DEC_HBW_MSTR_ERR_RESP */ 552 #define DCORE0_VDEC0_BRDG_CTRL_DEC_HBW_MSTR_ERR_RESP_WR_ERR_RESP_SHIFT 0 553 #define DCORE0_VDEC0_BRDG_CTRL_DEC_HBW_MSTR_ERR_RESP_WR_ERR_RESP_MASK 0x3 554 #define DCORE0_VDEC0_BRDG_CTRL_DEC_HBW_MSTR_ERR_RESP_RD_ERR_RESP_SHIFT 2 555 #define DCORE0_VDEC0_BRDG_CTRL_DEC_HBW_MSTR_ERR_RESP_RD_ERR_RESP_MASK 0xC 556 557 /* DCORE0_VDEC0_BRDG_CTRL_HBW_VIOL_TERM_STATUS */ 558 #define DCORE0_VDEC0_BRDG_CTRL_HBW_VIOL_TERM_STATUS_AW_STA_SHIFT 0 559 #define DCORE0_VDEC0_BRDG_CTRL_HBW_VIOL_TERM_STATUS_AW_STA_MASK 0x1 560 #define DCORE0_VDEC0_BRDG_CTRL_HBW_VIOL_TERM_STATUS_AR_STA_SHIFT 1 561 #define DCORE0_VDEC0_BRDG_CTRL_HBW_VIOL_TERM_STATUS_AR_STA_MASK 0x2 562 563 /* DCORE0_VDEC0_BRDG_CTRL_HBW_LAST_AWADDR_TERM_L */ 564 #define DCORE0_VDEC0_BRDG_CTRL_HBW_LAST_AWADDR_TERM_L_VAL_SHIFT 0 565 #define DCORE0_VDEC0_BRDG_CTRL_HBW_LAST_AWADDR_TERM_L_VAL_MASK 0xFFFFFFFF 566 567 /* DCORE0_VDEC0_BRDG_CTRL_HBW_LAST_AWADDR_TERM_H */ 568 #define DCORE0_VDEC0_BRDG_CTRL_HBW_LAST_AWADDR_TERM_H_VAL_SHIFT 0 569 #define DCORE0_VDEC0_BRDG_CTRL_HBW_LAST_AWADDR_TERM_H_VAL_MASK 0xFFFFFFFF 570 571 /* DCORE0_VDEC0_BRDG_CTRL_HBW_LAST_ARADDR_TERM_L */ 572 #define DCORE0_VDEC0_BRDG_CTRL_HBW_LAST_ARADDR_TERM_L_VAL_SHIFT 0 573 #define DCORE0_VDEC0_BRDG_CTRL_HBW_LAST_ARADDR_TERM_L_VAL_MASK 0xFFFFFFFF 574 575 /* DCORE0_VDEC0_BRDG_CTRL_HBW_LAST_ARADDR_TERM_H */ 576 #define DCORE0_VDEC0_BRDG_CTRL_HBW_LAST_ARADDR_TERM_H_VAL_SHIFT 0 577 #define DCORE0_VDEC0_BRDG_CTRL_HBW_LAST_ARADDR_TERM_H_VAL_MASK 0xFFFFFFFF 578 579 #endif /* ASIC_REG_DCORE0_VDEC0_BRDG_CTRL_MASKS_H_ */ 580
