1 /* SPDX-License-Identifier: GPL-2.0
2  *
3  * Copyright 2016-2020 HabanaLabs, Ltd.
4  * All Rights Reserved.
5  *
6  */
7 
8 /************************************
9  ** This is an auto-generated file **
10  **       DO NOT EDIT BELOW        **
11  ************************************/
12 
13 #ifndef ASIC_REG_DCORE0_TPC0_CFG_QM_REGS_H_
14 #define ASIC_REG_DCORE0_TPC0_CFG_QM_REGS_H_
15 
16 /*
17  *****************************************
18  *   DCORE0_TPC0_CFG_QM
19  *   (Prototype: TPC_NON_TENSOR_DESCRIPTOR)
20  *****************************************
21  */
22 
23 #define mmDCORE0_TPC0_CFG_QM_KERNEL_BASE_ADDRESS_LOW 0x400BAE4
24 
25 #define mmDCORE0_TPC0_CFG_QM_KERNEL_BASE_ADDRESS_HIGH 0x400BAE8
26 
27 #define mmDCORE0_TPC0_CFG_QM_TID_BASE_DIM_0 0x400BAEC
28 
29 #define mmDCORE0_TPC0_CFG_QM_TID_SIZE_DIM_0 0x400BAF0
30 
31 #define mmDCORE0_TPC0_CFG_QM_TID_BASE_DIM_1 0x400BAF4
32 
33 #define mmDCORE0_TPC0_CFG_QM_TID_SIZE_DIM_1 0x400BAF8
34 
35 #define mmDCORE0_TPC0_CFG_QM_TID_BASE_DIM_2 0x400BAFC
36 
37 #define mmDCORE0_TPC0_CFG_QM_TID_SIZE_DIM_2 0x400BB00
38 
39 #define mmDCORE0_TPC0_CFG_QM_TID_BASE_DIM_3 0x400BB04
40 
41 #define mmDCORE0_TPC0_CFG_QM_TID_SIZE_DIM_3 0x400BB08
42 
43 #define mmDCORE0_TPC0_CFG_QM_TID_BASE_DIM_4 0x400BB0C
44 
45 #define mmDCORE0_TPC0_CFG_QM_TID_SIZE_DIM_4 0x400BB10
46 
47 #define mmDCORE0_TPC0_CFG_QM_KERNEL_CONFIG 0x400BB14
48 
49 #define mmDCORE0_TPC0_CFG_QM_KERNEL_ID 0x400BB18
50 
51 #define mmDCORE0_TPC0_CFG_QM_POWER_LOOP 0x400BB1C
52 
53 #define mmDCORE0_TPC0_CFG_QM_SRF_0 0x400BB20
54 
55 #define mmDCORE0_TPC0_CFG_QM_SRF_1 0x400BB24
56 
57 #define mmDCORE0_TPC0_CFG_QM_SRF_2 0x400BB28
58 
59 #define mmDCORE0_TPC0_CFG_QM_SRF_3 0x400BB2C
60 
61 #define mmDCORE0_TPC0_CFG_QM_SRF_4 0x400BB30
62 
63 #define mmDCORE0_TPC0_CFG_QM_SRF_5 0x400BB34
64 
65 #define mmDCORE0_TPC0_CFG_QM_SRF_6 0x400BB38
66 
67 #define mmDCORE0_TPC0_CFG_QM_SRF_7 0x400BB3C
68 
69 #define mmDCORE0_TPC0_CFG_QM_SRF_8 0x400BB40
70 
71 #define mmDCORE0_TPC0_CFG_QM_SRF_9 0x400BB44
72 
73 #define mmDCORE0_TPC0_CFG_QM_SRF_10 0x400BB48
74 
75 #define mmDCORE0_TPC0_CFG_QM_SRF_11 0x400BB4C
76 
77 #define mmDCORE0_TPC0_CFG_QM_SRF_12 0x400BB50
78 
79 #define mmDCORE0_TPC0_CFG_QM_SRF_13 0x400BB54
80 
81 #define mmDCORE0_TPC0_CFG_QM_SRF_14 0x400BB58
82 
83 #define mmDCORE0_TPC0_CFG_QM_SRF_15 0x400BB5C
84 
85 #define mmDCORE0_TPC0_CFG_QM_SRF_16 0x400BB60
86 
87 #define mmDCORE0_TPC0_CFG_QM_SRF_17 0x400BB64
88 
89 #define mmDCORE0_TPC0_CFG_QM_SRF_18 0x400BB68
90 
91 #define mmDCORE0_TPC0_CFG_QM_SRF_19 0x400BB6C
92 
93 #define mmDCORE0_TPC0_CFG_QM_SRF_20 0x400BB70
94 
95 #define mmDCORE0_TPC0_CFG_QM_SRF_21 0x400BB74
96 
97 #define mmDCORE0_TPC0_CFG_QM_SRF_22 0x400BB78
98 
99 #define mmDCORE0_TPC0_CFG_QM_SRF_23 0x400BB7C
100 
101 #define mmDCORE0_TPC0_CFG_QM_SRF_24 0x400BB80
102 
103 #define mmDCORE0_TPC0_CFG_QM_SRF_25 0x400BB84
104 
105 #define mmDCORE0_TPC0_CFG_QM_SRF_26 0x400BB88
106 
107 #define mmDCORE0_TPC0_CFG_QM_SRF_27 0x400BB8C
108 
109 #define mmDCORE0_TPC0_CFG_QM_SRF_28 0x400BB90
110 
111 #define mmDCORE0_TPC0_CFG_QM_SRF_29 0x400BB94
112 
113 #define mmDCORE0_TPC0_CFG_QM_SRF_30 0x400BB98
114 
115 #define mmDCORE0_TPC0_CFG_QM_SRF_31 0x400BB9C
116 
117 #define mmDCORE0_TPC0_CFG_QM_KERNEL_ID_INC 0x400BBA0
118 
119 #define mmDCORE0_TPC0_CFG_QM_TID_BASE_SIZE_HIGH_DIM_0 0x400BBA4
120 
121 #define mmDCORE0_TPC0_CFG_QM_TID_BASE_SIZE_HIGH_DIM_1 0x400BBA8
122 
123 #define mmDCORE0_TPC0_CFG_QM_TID_BASE_SIZE_HIGH_DIM_2 0x400BBAC
124 
125 #define mmDCORE0_TPC0_CFG_QM_TID_BASE_SIZE_HIGH_DIM_3 0x400BBB0
126 
127 #define mmDCORE0_TPC0_CFG_QM_TID_BASE_SIZE_HIGH_DIM_4 0x400BBB4
128 
129 #endif /* ASIC_REG_DCORE0_TPC0_CFG_QM_REGS_H_ */
130