1 /* SPDX-License-Identifier: GPL-2.0 2 * 3 * Copyright 2016-2020 HabanaLabs, Ltd. 4 * All Rights Reserved. 5 * 6 */ 7 8 /************************************ 9 ** This is an auto-generated file ** 10 ** DO NOT EDIT BELOW ** 11 ************************************/ 12 13 #ifndef ASIC_REG_DCORE0_MME_CTRL_LO_MASKS_H_ 14 #define ASIC_REG_DCORE0_MME_CTRL_LO_MASKS_H_ 15 16 /* 17 ***************************************** 18 * DCORE0_MME_CTRL_LO 19 * (Prototype: MME_CTRL_LO) 20 ***************************************** 21 */ 22 23 /* DCORE0_MME_CTRL_LO_ARCH_STATUS */ 24 #define DCORE0_MME_CTRL_LO_ARCH_STATUS_AGU_IN_SHIFT 0 25 #define DCORE0_MME_CTRL_LO_ARCH_STATUS_AGU_IN_MASK 0x1F 26 #define DCORE0_MME_CTRL_LO_ARCH_STATUS_EU_SHIFT 5 27 #define DCORE0_MME_CTRL_LO_ARCH_STATUS_EU_MASK 0x20 28 #define DCORE0_MME_CTRL_LO_ARCH_STATUS_AP_SHIFT 6 29 #define DCORE0_MME_CTRL_LO_ARCH_STATUS_AP_MASK 0x40 30 #define DCORE0_MME_CTRL_LO_ARCH_STATUS_AGU_COUT_SHIFT 7 31 #define DCORE0_MME_CTRL_LO_ARCH_STATUS_AGU_COUT_MASK 0x180 32 #define DCORE0_MME_CTRL_LO_ARCH_STATUS_SB_IN_EMPTY_SHIFT 9 33 #define DCORE0_MME_CTRL_LO_ARCH_STATUS_SB_IN_EMPTY_MASK 0x3E00 34 #define DCORE0_MME_CTRL_LO_ARCH_STATUS_AGU_COUT_SM_IDLE_SHIFT 14 35 #define DCORE0_MME_CTRL_LO_ARCH_STATUS_AGU_COUT_SM_IDLE_MASK 0xC000 36 #define DCORE0_MME_CTRL_LO_ARCH_STATUS_WBC_AXI_IDLE_SHIFT 16 37 #define DCORE0_MME_CTRL_LO_ARCH_STATUS_WBC_AXI_IDLE_MASK 0x30000 38 #define DCORE0_MME_CTRL_LO_ARCH_STATUS_SB_IN_AXI_IDLE_SHIFT 18 39 #define DCORE0_MME_CTRL_LO_ARCH_STATUS_SB_IN_AXI_IDLE_MASK 0x7C0000 40 #define DCORE0_MME_CTRL_LO_ARCH_STATUS_ACCUM_FREE_SHIFT 23 41 #define DCORE0_MME_CTRL_LO_ARCH_STATUS_ACCUM_FREE_MASK 0x3800000 42 #define DCORE0_MME_CTRL_LO_ARCH_STATUS_QM_IDLE_SHIFT 30 43 #define DCORE0_MME_CTRL_LO_ARCH_STATUS_QM_IDLE_MASK 0x40000000 44 #define DCORE0_MME_CTRL_LO_ARCH_STATUS_QM_RDY_SHIFT 31 45 #define DCORE0_MME_CTRL_LO_ARCH_STATUS_QM_RDY_MASK 0x80000000 46 47 /* DCORE0_MME_CTRL_LO_CMD */ 48 #define DCORE0_MME_CTRL_LO_CMD_AGU_IN_SHIFT 0 49 #define DCORE0_MME_CTRL_LO_CMD_AGU_IN_MASK 0x1F 50 #define DCORE0_MME_CTRL_LO_CMD_EU_SHIFT 5 51 #define DCORE0_MME_CTRL_LO_CMD_EU_MASK 0x20 52 #define DCORE0_MME_CTRL_LO_CMD_AP_SHIFT 6 53 #define DCORE0_MME_CTRL_LO_CMD_AP_MASK 0x40 54 #define DCORE0_MME_CTRL_LO_CMD_AGU_COUT_SHIFT 7 55 #define DCORE0_MME_CTRL_LO_CMD_AGU_COUT_MASK 0x180 56 #define DCORE0_MME_CTRL_LO_CMD_COPY_AND_INC_SHIFT 9 57 #define DCORE0_MME_CTRL_LO_CMD_COPY_AND_INC_MASK 0x200 58 #define DCORE0_MME_CTRL_LO_CMD_DESC_SEL_SHIFT 10 59 #define DCORE0_MME_CTRL_LO_CMD_DESC_SEL_MASK 0xC00 60 #define DCORE0_MME_CTRL_LO_CMD_MASK_IDLE_IND_SHIFT 12 61 #define DCORE0_MME_CTRL_LO_CMD_MASK_IDLE_IND_MASK 0x1000 62 #define DCORE0_MME_CTRL_LO_CMD_AGU_OUT1_FROM_AGU0_DW0_SHIFT 13 63 #define DCORE0_MME_CTRL_LO_CMD_AGU_OUT1_FROM_AGU0_DW0_MASK 0x2000 64 #define DCORE0_MME_CTRL_LO_CMD_AGU_OUT1_FROM_AGU0_DW1_4_SHIFT 14 65 #define DCORE0_MME_CTRL_LO_CMD_AGU_OUT1_FROM_AGU0_DW1_4_MASK 0x4000 66 #define DCORE0_MME_CTRL_LO_CMD_NULL_DESC_SHIFT 15 67 #define DCORE0_MME_CTRL_LO_CMD_NULL_DESC_MASK 0x8000 68 69 /* DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_DW0 */ 70 #define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_DW0_SIGNAL_MASK0_SHIFT 0 71 #define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_DW0_SIGNAL_MASK0_MASK 0x3F 72 #define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_DW0_SIGNAL_EN0_SHIFT 6 73 #define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_DW0_SIGNAL_EN0_MASK 0x40 74 #define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_DW0_SIGNAL_MASK1_SHIFT 8 75 #define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_DW0_SIGNAL_MASK1_MASK 0x3F00 76 #define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_DW0_SIGNAL_EN1_SHIFT 14 77 #define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_DW0_SIGNAL_EN1_MASK 0x4000 78 #define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_DW0_MASTER_WAIT_SLAVE_FENCE_SHIFT 15 79 #define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_DW0_MASTER_WAIT_SLAVE_FENCE_MASK 0x8000 80 #define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_DW0_SLAVE_SEND_FENCE2MASTER_SHIFT 16 81 #define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_DW0_SLAVE_SEND_FENCE2MASTER_MASK \ 82 0x10000 83 #define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_DW0_SLAVE_SIGNAL_EN_SHIFT 17 84 #define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_DW0_SLAVE_SIGNAL_EN_MASK 0x20000 85 #define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_DW0_SLAVE0_USE_SLV_ADR_SHIFT 18 86 #define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_DW0_SLAVE0_USE_SLV_ADR_MASK 0x40000 87 #define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_DW0_SLAVE1_USE_SLV_ADR_SHIFT 19 88 #define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_DW0_SLAVE1_USE_SLV_ADR_MASK 0x80000 89 #define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_DW0_SLAVE0_USE_MSTR_ADR_PLUS4_SHIFT 20 90 #define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_DW0_SLAVE0_USE_MSTR_ADR_PLUS4_MASK \ 91 0x100000 92 #define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_DW0_SLAVE1_USE_MSTR_ADR_PLUS4_SHIFT 21 93 #define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_DW0_SLAVE1_USE_MSTR_ADR_PLUS4_MASK \ 94 0x200000 95 96 /* DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_ADDR0 */ 97 #define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_ADDR0_V_SHIFT 0 98 #define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_ADDR0_V_MASK 0xFFFFFFFF 99 100 /* DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_VAL0 */ 101 #define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_VAL0_SO_VALUE_SHIFT 0 102 #define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_VAL0_SO_VALUE_MASK 0x7FFF 103 #define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_VAL0_SO_RESERVED_SHIFT 15 104 #define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_VAL0_SO_RESERVED_MASK 0x3FFF8000 105 #define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_VAL0_SO_PERF_EN_SHIFT 30 106 #define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_VAL0_SO_PERF_EN_MASK 0x40000000 107 #define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_VAL0_SO_OP_SHIFT 31 108 #define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_VAL0_SO_OP_MASK 0x80000000 109 110 /* DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_ADDR1 */ 111 #define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_ADDR1_V_SHIFT 0 112 #define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_ADDR1_V_MASK 0xFFFFFFFF 113 114 /* DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_VAL1 */ 115 #define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_VAL1_SO_VALUE_SHIFT 0 116 #define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_VAL1_SO_VALUE_MASK 0x7FFF 117 #define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_VAL1_SO_RESERVED_SHIFT 15 118 #define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_VAL1_SO_RESERVED_MASK 0x3FFF8000 119 #define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_VAL1_SO_PERF_EN_SHIFT 30 120 #define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_VAL1_SO_PERF_EN_MASK 0x40000000 121 #define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_VAL1_SO_OP_SHIFT 31 122 #define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_VAL1_SO_OP_MASK 0x80000000 123 124 /* DCORE0_MME_CTRL_LO_ARCH_A_SS */ 125 #define DCORE0_MME_CTRL_LO_ARCH_A_SS_MINUS_1_SHIFT 0 126 #define DCORE0_MME_CTRL_LO_ARCH_A_SS_MINUS_1_MASK 0xFFFFFFFF 127 128 /* DCORE0_MME_CTRL_LO_ARCH_B_SS */ 129 #define DCORE0_MME_CTRL_LO_ARCH_B_SS_MINUS_1_SHIFT 0 130 #define DCORE0_MME_CTRL_LO_ARCH_B_SS_MINUS_1_MASK 0xFFFFFFFF 131 132 /* DCORE0_MME_CTRL_LO_ARCH_COUT_SS */ 133 #define DCORE0_MME_CTRL_LO_ARCH_COUT_SS_MINUS_1_SHIFT 0 134 #define DCORE0_MME_CTRL_LO_ARCH_COUT_SS_MINUS_1_MASK 0xFFFFFFFF 135 136 /* DCORE0_MME_CTRL_LO_QM_STALL */ 137 #define DCORE0_MME_CTRL_LO_QM_STALL_V_SHIFT 0 138 #define DCORE0_MME_CTRL_LO_QM_STALL_V_MASK 0x1 139 140 /* DCORE0_MME_CTRL_LO_LOG_SHADOW_LO */ 141 #define DCORE0_MME_CTRL_LO_LOG_SHADOW_LO_MASK_0_SHIFT 0 142 #define DCORE0_MME_CTRL_LO_LOG_SHADOW_LO_MASK_0_MASK 0x1FF 143 #define DCORE0_MME_CTRL_LO_LOG_SHADOW_LO_MASK_1_SHIFT 9 144 #define DCORE0_MME_CTRL_LO_LOG_SHADOW_LO_MASK_1_MASK 0x3FE00 145 146 /* DCORE0_MME_CTRL_LO_LOG_SHADOW_HI */ 147 #define DCORE0_MME_CTRL_LO_LOG_SHADOW_HI_MASK_2_SHIFT 0 148 #define DCORE0_MME_CTRL_LO_LOG_SHADOW_HI_MASK_2_MASK 0x1FF 149 #define DCORE0_MME_CTRL_LO_LOG_SHADOW_HI_MASK_3_SHIFT 9 150 #define DCORE0_MME_CTRL_LO_LOG_SHADOW_HI_MASK_3_MASK 0x3FE00 151 152 /* DCORE0_MME_CTRL_LO_SYNC_OBJECT_FIFO_TH */ 153 #define DCORE0_MME_CTRL_LO_SYNC_OBJECT_FIFO_TH_V_SHIFT 0 154 #define DCORE0_MME_CTRL_LO_SYNC_OBJECT_FIFO_TH_V_MASK 0x1F 155 156 /* DCORE0_MME_CTRL_LO_REDUN */ 157 #define DCORE0_MME_CTRL_LO_REDUN_FMA_SHIFT 0 158 #define DCORE0_MME_CTRL_LO_REDUN_FMA_MASK 0x3F 159 160 /* DCORE0_MME_CTRL_LO_EUS_LOCAL_FIFO_TH */ 161 #define DCORE0_MME_CTRL_LO_EUS_LOCAL_FIFO_TH_FIFO0_SHIFT 0 162 #define DCORE0_MME_CTRL_LO_EUS_LOCAL_FIFO_TH_FIFO0_MASK 0x1F 163 #define DCORE0_MME_CTRL_LO_EUS_LOCAL_FIFO_TH_FIFO1_SHIFT 5 164 #define DCORE0_MME_CTRL_LO_EUS_LOCAL_FIFO_TH_FIFO1_MASK 0x3E0 165 #define DCORE0_MME_CTRL_LO_EUS_LOCAL_FIFO_TH_FIFO2_SHIFT 10 166 #define DCORE0_MME_CTRL_LO_EUS_LOCAL_FIFO_TH_FIFO2_MASK 0x7C00 167 168 /* DCORE0_MME_CTRL_LO_EUS_ROLLUP_DLY_DW0 */ 169 #define DCORE0_MME_CTRL_LO_EUS_ROLLUP_DLY_DW0_FP_SHIFT 0 170 #define DCORE0_MME_CTRL_LO_EUS_ROLLUP_DLY_DW0_FP_MASK 0xFF 171 #define DCORE0_MME_CTRL_LO_EUS_ROLLUP_DLY_DW0_FP_PE0_SHIFT 8 172 #define DCORE0_MME_CTRL_LO_EUS_ROLLUP_DLY_DW0_FP_PE0_MASK 0x1F00 173 #define DCORE0_MME_CTRL_LO_EUS_ROLLUP_DLY_DW0_FP_PE1_SHIFT 13 174 #define DCORE0_MME_CTRL_LO_EUS_ROLLUP_DLY_DW0_FP_PE1_MASK 0x3E000 175 #define DCORE0_MME_CTRL_LO_EUS_ROLLUP_DLY_DW0_FP_PE2_SHIFT 18 176 #define DCORE0_MME_CTRL_LO_EUS_ROLLUP_DLY_DW0_FP_PE2_MASK 0x7C0000 177 #define DCORE0_MME_CTRL_LO_EUS_ROLLUP_DLY_DW0_FP_PE3_SHIFT 23 178 #define DCORE0_MME_CTRL_LO_EUS_ROLLUP_DLY_DW0_FP_PE3_MASK 0xF800000 179 180 /* DCORE0_MME_CTRL_LO_EUS_ROLLUP_DLY_DW1 */ 181 #define DCORE0_MME_CTRL_LO_EUS_ROLLUP_DLY_DW1_FP_PE4_SHIFT 0 182 #define DCORE0_MME_CTRL_LO_EUS_ROLLUP_DLY_DW1_FP_PE4_MASK 0x1F 183 #define DCORE0_MME_CTRL_LO_EUS_ROLLUP_DLY_DW1_FP_PE_HI_SHIFT 5 184 #define DCORE0_MME_CTRL_LO_EUS_ROLLUP_DLY_DW1_FP_PE_HI_MASK 0x3E0 185 186 /* DCORE0_MME_CTRL_LO_EUS_ROLLUP_CD_PROT_F16 */ 187 #define DCORE0_MME_CTRL_LO_EUS_ROLLUP_CD_PROT_F16_DLY_SHIFT 0 188 #define DCORE0_MME_CTRL_LO_EUS_ROLLUP_CD_PROT_F16_DLY_MASK 0xFFF 189 #define DCORE0_MME_CTRL_LO_EUS_ROLLUP_CD_PROT_F16_EN_SHIFT 31 190 #define DCORE0_MME_CTRL_LO_EUS_ROLLUP_CD_PROT_F16_EN_MASK 0x80000000 191 192 /* DCORE0_MME_CTRL_LO_EUS_ROLLUP_CD_PROT_F8 */ 193 #define DCORE0_MME_CTRL_LO_EUS_ROLLUP_CD_PROT_F8_DLY_SHIFT 0 194 #define DCORE0_MME_CTRL_LO_EUS_ROLLUP_CD_PROT_F8_DLY_MASK 0xFFF 195 #define DCORE0_MME_CTRL_LO_EUS_ROLLUP_CD_PROT_F8_EN_SHIFT 31 196 #define DCORE0_MME_CTRL_LO_EUS_ROLLUP_CD_PROT_F8_EN_MASK 0x80000000 197 198 /* DCORE0_MME_CTRL_LO_EUS_ROLLUP_CD_PROT_FP32 */ 199 #define DCORE0_MME_CTRL_LO_EUS_ROLLUP_CD_PROT_FP32_DLY_SHIFT 0 200 #define DCORE0_MME_CTRL_LO_EUS_ROLLUP_CD_PROT_FP32_DLY_MASK 0xFFF 201 #define DCORE0_MME_CTRL_LO_EUS_ROLLUP_CD_PROT_FP32_EN_SHIFT 31 202 #define DCORE0_MME_CTRL_LO_EUS_ROLLUP_CD_PROT_FP32_EN_MASK 0x80000000 203 204 /* DCORE0_MME_CTRL_LO_EUS_ROLLUP_CD_PROT_FP32I */ 205 #define DCORE0_MME_CTRL_LO_EUS_ROLLUP_CD_PROT_FP32I_DLY_SHIFT 0 206 #define DCORE0_MME_CTRL_LO_EUS_ROLLUP_CD_PROT_FP32I_DLY_MASK 0xFFF 207 #define DCORE0_MME_CTRL_LO_EUS_ROLLUP_CD_PROT_FP32I_EN_SHIFT 31 208 #define DCORE0_MME_CTRL_LO_EUS_ROLLUP_CD_PROT_FP32I_EN_MASK 0x80000000 209 210 /* DCORE0_MME_CTRL_LO_EUS_ROLLUP_CD_PROT_TF32 */ 211 #define DCORE0_MME_CTRL_LO_EUS_ROLLUP_CD_PROT_TF32_DLY_SHIFT 0 212 #define DCORE0_MME_CTRL_LO_EUS_ROLLUP_CD_PROT_TF32_DLY_MASK 0xFFF 213 #define DCORE0_MME_CTRL_LO_EUS_ROLLUP_CD_PROT_TF32_EN_SHIFT 31 214 #define DCORE0_MME_CTRL_LO_EUS_ROLLUP_CD_PROT_TF32_EN_MASK 0x80000000 215 216 /* DCORE0_MME_CTRL_LO_PCU_RL_DESC0 */ 217 #define DCORE0_MME_CTRL_LO_PCU_RL_DESC0_RL_RST_TOKEN_SHIFT 0 218 #define DCORE0_MME_CTRL_LO_PCU_RL_DESC0_RL_RST_TOKEN_MASK 0xFFFF 219 #define DCORE0_MME_CTRL_LO_PCU_RL_DESC0_RL_TIMEOUT_SHIFT 16 220 #define DCORE0_MME_CTRL_LO_PCU_RL_DESC0_RL_TIMEOUT_MASK 0xFF0000 221 #define DCORE0_MME_CTRL_LO_PCU_RL_DESC0_RL_DUMMY2REAL_PERIOD_SHIFT 24 222 #define DCORE0_MME_CTRL_LO_PCU_RL_DESC0_RL_DUMMY2REAL_PERIOD_MASK 0xFF000000 223 224 /* DCORE0_MME_CTRL_LO_PCU_RL_TOKEN_UPDATE */ 225 #define DCORE0_MME_CTRL_LO_PCU_RL_TOKEN_UPDATE_INC_VAL_SHIFT 0 226 #define DCORE0_MME_CTRL_LO_PCU_RL_TOKEN_UPDATE_INC_VAL_MASK 0xFFFF 227 #define DCORE0_MME_CTRL_LO_PCU_RL_TOKEN_UPDATE_DEC_VAL_SHIFT 16 228 #define DCORE0_MME_CTRL_LO_PCU_RL_TOKEN_UPDATE_DEC_VAL_MASK 0xFFFF0000 229 230 /* DCORE0_MME_CTRL_LO_PCU_RL_TH */ 231 #define DCORE0_MME_CTRL_LO_PCU_RL_TH_POOL_TH_DEC_SHIFT 0 232 #define DCORE0_MME_CTRL_LO_PCU_RL_TH_POOL_TH_DEC_MASK 0xFFFF 233 #define DCORE0_MME_CTRL_LO_PCU_RL_TH_DUMMY_REAL_DIFF_TH_SHIFT 16 234 #define DCORE0_MME_CTRL_LO_PCU_RL_TH_DUMMY_REAL_DIFF_TH_MASK 0xFFFF0000 235 236 /* DCORE0_MME_CTRL_LO_PCU_RL_MIN */ 237 #define DCORE0_MME_CTRL_LO_PCU_RL_MIN_AVG_MIN_TO_FORCE_DUMMY_SHIFT 0 238 #define DCORE0_MME_CTRL_LO_PCU_RL_MIN_AVG_MIN_TO_FORCE_DUMMY_MASK 0xFFFF 239 #define DCORE0_MME_CTRL_LO_PCU_RL_MIN_TOKEN_MIN_VAL_SHIFT 16 240 #define DCORE0_MME_CTRL_LO_PCU_RL_MIN_TOKEN_MIN_VAL_MASK 0xFFFF0000 241 242 /* DCORE0_MME_CTRL_LO_PCU_RL_CTRL_EN */ 243 #define DCORE0_MME_CTRL_LO_PCU_RL_CTRL_EN_PCU_DISABLE_SHIFT 0 244 #define DCORE0_MME_CTRL_LO_PCU_RL_CTRL_EN_PCU_DISABLE_MASK 0x1 245 #define DCORE0_MME_CTRL_LO_PCU_RL_CTRL_EN_MIN_VAL_PROT_EN_SHIFT 1 246 #define DCORE0_MME_CTRL_LO_PCU_RL_CTRL_EN_MIN_VAL_PROT_EN_MASK 0x2 247 248 /* DCORE0_MME_CTRL_LO_PCU_RL_HISTORY_LOG_SIZE */ 249 #define DCORE0_MME_CTRL_LO_PCU_RL_HISTORY_LOG_SIZE_ALL_MACS_SHIFT 0 250 #define DCORE0_MME_CTRL_LO_PCU_RL_HISTORY_LOG_SIZE_ALL_MACS_MASK 0x7 251 #define DCORE0_MME_CTRL_LO_PCU_RL_HISTORY_LOG_SIZE_REAL_MACS_SHIFT 3 252 #define DCORE0_MME_CTRL_LO_PCU_RL_HISTORY_LOG_SIZE_REAL_MACS_MASK 0x18 253 254 /* DCORE0_MME_CTRL_LO_PCU_DUMMY_A_BF16 */ 255 #define DCORE0_MME_CTRL_LO_PCU_DUMMY_A_BF16_ODD_SHIFT 0 256 #define DCORE0_MME_CTRL_LO_PCU_DUMMY_A_BF16_ODD_MASK 0xFFFF 257 #define DCORE0_MME_CTRL_LO_PCU_DUMMY_A_BF16_EVEN_SHIFT 16 258 #define DCORE0_MME_CTRL_LO_PCU_DUMMY_A_BF16_EVEN_MASK 0xFFFF0000 259 260 /* DCORE0_MME_CTRL_LO_PCU_DUMMY_B_BF16 */ 261 #define DCORE0_MME_CTRL_LO_PCU_DUMMY_B_BF16_ODD_SHIFT 0 262 #define DCORE0_MME_CTRL_LO_PCU_DUMMY_B_BF16_ODD_MASK 0xFFFF 263 #define DCORE0_MME_CTRL_LO_PCU_DUMMY_B_BF16_EVEN_SHIFT 16 264 #define DCORE0_MME_CTRL_LO_PCU_DUMMY_B_BF16_EVEN_MASK 0xFFFF0000 265 266 /* DCORE0_MME_CTRL_LO_PCU_DUMMY_A_FP16 */ 267 #define DCORE0_MME_CTRL_LO_PCU_DUMMY_A_FP16_ODD_SHIFT 0 268 #define DCORE0_MME_CTRL_LO_PCU_DUMMY_A_FP16_ODD_MASK 0xFFFF 269 #define DCORE0_MME_CTRL_LO_PCU_DUMMY_A_FP16_EVEN_SHIFT 16 270 #define DCORE0_MME_CTRL_LO_PCU_DUMMY_A_FP16_EVEN_MASK 0xFFFF0000 271 272 /* DCORE0_MME_CTRL_LO_PCU_DUMMY_B_FP16 */ 273 #define DCORE0_MME_CTRL_LO_PCU_DUMMY_B_FP16_ODD_SHIFT 0 274 #define DCORE0_MME_CTRL_LO_PCU_DUMMY_B_FP16_ODD_MASK 0xFFFF 275 #define DCORE0_MME_CTRL_LO_PCU_DUMMY_B_FP16_EVEN_SHIFT 16 276 #define DCORE0_MME_CTRL_LO_PCU_DUMMY_B_FP16_EVEN_MASK 0xFFFF0000 277 278 /* DCORE0_MME_CTRL_LO_PCU_DUMMY_F8 */ 279 #define DCORE0_MME_CTRL_LO_PCU_DUMMY_F8_A_VAL_ODD_SHIFT 0 280 #define DCORE0_MME_CTRL_LO_PCU_DUMMY_F8_A_VAL_ODD_MASK 0xFF 281 #define DCORE0_MME_CTRL_LO_PCU_DUMMY_F8_A_VAL_EVEN_SHIFT 8 282 #define DCORE0_MME_CTRL_LO_PCU_DUMMY_F8_A_VAL_EVEN_MASK 0xFF00 283 #define DCORE0_MME_CTRL_LO_PCU_DUMMY_F8_B_VAL_ODD_SHIFT 16 284 #define DCORE0_MME_CTRL_LO_PCU_DUMMY_F8_B_VAL_ODD_MASK 0xFF0000 285 #define DCORE0_MME_CTRL_LO_PCU_DUMMY_F8_B_VAL_EVEN_SHIFT 24 286 #define DCORE0_MME_CTRL_LO_PCU_DUMMY_F8_B_VAL_EVEN_MASK 0xFF000000 287 288 /* DCORE0_MME_CTRL_LO_PCU_DUMMY_A_FP32_ODD */ 289 #define DCORE0_MME_CTRL_LO_PCU_DUMMY_A_FP32_ODD_V_SHIFT 0 290 #define DCORE0_MME_CTRL_LO_PCU_DUMMY_A_FP32_ODD_V_MASK 0xFFFFFFFF 291 292 /* DCORE0_MME_CTRL_LO_PCU_DUMMY_A_FP32_EVEN */ 293 #define DCORE0_MME_CTRL_LO_PCU_DUMMY_A_FP32_EVEN_V_SHIFT 0 294 #define DCORE0_MME_CTRL_LO_PCU_DUMMY_A_FP32_EVEN_V_MASK 0xFFFFFFFF 295 296 /* DCORE0_MME_CTRL_LO_PCU_DUMMY_B_FP32_ODD */ 297 #define DCORE0_MME_CTRL_LO_PCU_DUMMY_B_FP32_ODD_V_SHIFT 0 298 #define DCORE0_MME_CTRL_LO_PCU_DUMMY_B_FP32_ODD_V_MASK 0xFFFFFFFF 299 300 /* DCORE0_MME_CTRL_LO_PCU_DUMMY_B_FP32_EVEN */ 301 #define DCORE0_MME_CTRL_LO_PCU_DUMMY_B_FP32_EVEN_V_SHIFT 0 302 #define DCORE0_MME_CTRL_LO_PCU_DUMMY_B_FP32_EVEN_V_MASK 0xFFFFFFFF 303 304 /* DCORE0_MME_CTRL_LO_PCU_DUMMY_A_TF32_ODD */ 305 #define DCORE0_MME_CTRL_LO_PCU_DUMMY_A_TF32_ODD_V_SHIFT 0 306 #define DCORE0_MME_CTRL_LO_PCU_DUMMY_A_TF32_ODD_V_MASK 0xFFFFFFFF 307 308 /* DCORE0_MME_CTRL_LO_PCU_DUMMY_A_TF32_EVEN */ 309 #define DCORE0_MME_CTRL_LO_PCU_DUMMY_A_TF32_EVEN_V_SHIFT 0 310 #define DCORE0_MME_CTRL_LO_PCU_DUMMY_A_TF32_EVEN_V_MASK 0xFFFFFFFF 311 312 /* DCORE0_MME_CTRL_LO_PCU_DUMMY_B_TF32_ODD */ 313 #define DCORE0_MME_CTRL_LO_PCU_DUMMY_B_TF32_ODD_V_SHIFT 0 314 #define DCORE0_MME_CTRL_LO_PCU_DUMMY_B_TF32_ODD_V_MASK 0xFFFFFFFF 315 316 /* DCORE0_MME_CTRL_LO_PCU_DUMMY_B_TF32_EVEN */ 317 #define DCORE0_MME_CTRL_LO_PCU_DUMMY_B_TF32_EVEN_V_SHIFT 0 318 #define DCORE0_MME_CTRL_LO_PCU_DUMMY_B_TF32_EVEN_V_MASK 0xFFFFFFFF 319 320 /* DCORE0_MME_CTRL_LO_PROT */ 321 #define DCORE0_MME_CTRL_LO_PROT_VALUE_SHIFT 0 322 #define DCORE0_MME_CTRL_LO_PROT_VALUE_MASK 0x7 323 324 /* DCORE0_MME_CTRL_LO_EU */ 325 #define DCORE0_MME_CTRL_LO_EU_POWER_SAVE_DISABLE_SHIFT 0 326 #define DCORE0_MME_CTRL_LO_EU_POWER_SAVE_DISABLE_MASK 0x1 327 #define DCORE0_MME_CTRL_LO_EU_FP_PYR_CLOSE_CGATE_EN_SHIFT 1 328 #define DCORE0_MME_CTRL_LO_EU_FP_PYR_CLOSE_CGATE_EN_MASK 0x2 329 #define DCORE0_MME_CTRL_LO_EU_FP_CLS_CLOSE_CGATE_EN_SHIFT 2 330 #define DCORE0_MME_CTRL_LO_EU_FP_CLS_CLOSE_CGATE_EN_MASK 0x4 331 #define DCORE0_MME_CTRL_LO_EU_FP_CLOSE_CGATE_DLY_SHIFT 8 332 #define DCORE0_MME_CTRL_LO_EU_FP_CLOSE_CGATE_DLY_MASK 0xFFF00 333 #define DCORE0_MME_CTRL_LO_EU_FP_CLOSE_CGATE_ON_DESC_SHIFT 20 334 #define DCORE0_MME_CTRL_LO_EU_FP_CLOSE_CGATE_ON_DESC_MASK 0x100000 335 #define DCORE0_MME_CTRL_LO_EU_FP_ROLLUP_CDC_STALL_DIS_SHIFT 21 336 #define DCORE0_MME_CTRL_LO_EU_FP_ROLLUP_CDC_STALL_DIS_MASK 0x200000 337 338 /* DCORE0_MME_CTRL_LO_SBTE */ 339 #define DCORE0_MME_CTRL_LO_SBTE_CLOSE_CGATE_SHIFT 0 340 #define DCORE0_MME_CTRL_LO_SBTE_CLOSE_CGATE_MASK 0x1F 341 342 /* DCORE0_MME_CTRL_LO_AGU_SM_INFLIGHT_CNTR */ 343 #define DCORE0_MME_CTRL_LO_AGU_SM_INFLIGHT_CNTR_V_SHIFT 0 344 #define DCORE0_MME_CTRL_LO_AGU_SM_INFLIGHT_CNTR_V_MASK 0xFFFFFFFF 345 346 /* DCORE0_MME_CTRL_LO_AGU_SM_TOTAL_CNTR */ 347 #define DCORE0_MME_CTRL_LO_AGU_SM_TOTAL_CNTR_V_SHIFT 0 348 #define DCORE0_MME_CTRL_LO_AGU_SM_TOTAL_CNTR_V_MASK 0xFFFFFFFF 349 350 /* DCORE0_MME_CTRL_LO_PCU_RL_SAT_SEC */ 351 #define DCORE0_MME_CTRL_LO_PCU_RL_SAT_SEC_VAL_SHIFT 0 352 #define DCORE0_MME_CTRL_LO_PCU_RL_SAT_SEC_VAL_MASK 0xFFFFF 353 #define DCORE0_MME_CTRL_LO_PCU_RL_SAT_SEC_SEL_SHIFT 31 354 #define DCORE0_MME_CTRL_LO_PCU_RL_SAT_SEC_SEL_MASK 0x80000000 355 356 /* DCORE0_MME_CTRL_LO_FMA_FUNC_REDUN_CLK_EN32 */ 357 #define DCORE0_MME_CTRL_LO_FMA_FUNC_REDUN_CLK_EN32_V_NMB__SHIFT 0 358 #define DCORE0_MME_CTRL_LO_FMA_FUNC_REDUN_CLK_EN32_V_NMB__MASK 0xFFFFFFFF 359 360 /* DCORE0_MME_CTRL_LO_FMA_FUNC_REDUN_CLK_EN33 */ 361 #define DCORE0_MME_CTRL_LO_FMA_FUNC_REDUN_CLK_EN33_V_NMB__SHIFT 0 362 #define DCORE0_MME_CTRL_LO_FMA_FUNC_REDUN_CLK_EN33_V_NMB__MASK 0x1 363 364 /* DCORE0_MME_CTRL_LO_EU_ISOLATION_DIS */ 365 #define DCORE0_MME_CTRL_LO_EU_ISOLATION_DIS_FMA_SHIFT 0 366 #define DCORE0_MME_CTRL_LO_EU_ISOLATION_DIS_FMA_MASK 0x1 367 368 /* DCORE0_MME_CTRL_LO_QM_SLV_CLK_EN */ 369 #define DCORE0_MME_CTRL_LO_QM_SLV_CLK_EN_V_SHIFT 0 370 #define DCORE0_MME_CTRL_LO_QM_SLV_CLK_EN_V_MASK 0x1 371 372 /* DCORE0_MME_CTRL_LO_HBW_CLK_ENABLER_DIS */ 373 #define DCORE0_MME_CTRL_LO_HBW_CLK_ENABLER_DIS_AXI_SHIFT 0 374 #define DCORE0_MME_CTRL_LO_HBW_CLK_ENABLER_DIS_AXI_MASK 0x1 375 #define DCORE0_MME_CTRL_LO_HBW_CLK_ENABLER_DIS_APB_SHIFT 1 376 #define DCORE0_MME_CTRL_LO_HBW_CLK_ENABLER_DIS_APB_MASK 0x2 377 378 /* DCORE0_MME_CTRL_LO_AGU */ 379 #define DCORE0_MME_CTRL_LO_AGU_COUT_H_FROM_SPATIAL_LOOP_SHIFT 0 380 #define DCORE0_MME_CTRL_LO_AGU_COUT_H_FROM_SPATIAL_LOOP_MASK 0x1 381 382 /* DCORE0_MME_CTRL_LO_QM */ 383 #define DCORE0_MME_CTRL_LO_QM_STOP_ON_SBTE_ERR_SHIFT 0 384 #define DCORE0_MME_CTRL_LO_QM_STOP_ON_SBTE_ERR_MASK 0x1 385 #define DCORE0_MME_CTRL_LO_QM_EXT_ADDR_ERR_EN_SHIFT 1 386 #define DCORE0_MME_CTRL_LO_QM_EXT_ADDR_ERR_EN_MASK 0x2 387 388 /* DCORE0_MME_CTRL_LO_EARLY_RELEASE_STATUS */ 389 #define DCORE0_MME_CTRL_LO_EARLY_RELEASE_STATUS_AGU_COUT0_SHIFT 0 390 #define DCORE0_MME_CTRL_LO_EARLY_RELEASE_STATUS_AGU_COUT0_MASK 0xF 391 #define DCORE0_MME_CTRL_LO_EARLY_RELEASE_STATUS_AGU_COUT1_SHIFT 4 392 #define DCORE0_MME_CTRL_LO_EARLY_RELEASE_STATUS_AGU_COUT1_MASK 0xF0 393 #define DCORE0_MME_CTRL_LO_EARLY_RELEASE_STATUS_AP_BRAIN_SHIFT 8 394 #define DCORE0_MME_CTRL_LO_EARLY_RELEASE_STATUS_AP_BRAIN_MASK 0xF00 395 #define DCORE0_MME_CTRL_LO_EARLY_RELEASE_STATUS_EU_BRAIN_SHIFT 12 396 #define DCORE0_MME_CTRL_LO_EARLY_RELEASE_STATUS_EU_BRAIN_MASK 0xF000 397 398 /* DCORE0_MME_CTRL_LO_INTR_CAUSE */ 399 #define DCORE0_MME_CTRL_LO_INTR_CAUSE_V_SHIFT 0 400 #define DCORE0_MME_CTRL_LO_INTR_CAUSE_V_MASK 0xFFFF 401 402 /* DCORE0_MME_CTRL_LO_INTR_MASK */ 403 #define DCORE0_MME_CTRL_LO_INTR_MASK_V_SHIFT 0 404 #define DCORE0_MME_CTRL_LO_INTR_MASK_V_MASK 0x3FFFFF 405 406 /* DCORE0_MME_CTRL_LO_INTR_CLEAR */ 407 #define DCORE0_MME_CTRL_LO_INTR_CLEAR_V_SHIFT 0 408 #define DCORE0_MME_CTRL_LO_INTR_CLEAR_V_MASK 0xFFFF 409 410 /* DCORE0_MME_CTRL_LO_REDUN_PSOC_SEL_SEC */ 411 #define DCORE0_MME_CTRL_LO_REDUN_PSOC_SEL_SEC_V_SHIFT 0 412 #define DCORE0_MME_CTRL_LO_REDUN_PSOC_SEL_SEC_V_MASK 0x1 413 414 /* DCORE0_MME_CTRL_LO_BIST */ 415 #define DCORE0_MME_CTRL_LO_BIST_FUNC_MODE_SHIFT 0 416 #define DCORE0_MME_CTRL_LO_BIST_FUNC_MODE_MASK 0x1 417 #define DCORE0_MME_CTRL_LO_BIST_APB_SW_MODE_SHIFT 1 418 #define DCORE0_MME_CTRL_LO_BIST_APB_SW_MODE_MASK 0x2 419 420 /* DCORE0_MME_CTRL_LO_EU_RL_ENABLE */ 421 #define DCORE0_MME_CTRL_LO_EU_RL_ENABLE_V_SHIFT 0 422 #define DCORE0_MME_CTRL_LO_EU_RL_ENABLE_V_MASK 0x1 423 424 /* DCORE0_MME_CTRL_LO_EU_RL_TOKEN_SEL */ 425 #define DCORE0_MME_CTRL_LO_EU_RL_TOKEN_SEL_STAT_SHIFT 0 426 #define DCORE0_MME_CTRL_LO_EU_RL_TOKEN_SEL_STAT_MASK 0x1 427 428 /* DCORE0_MME_CTRL_LO_EU_RL_CFG */ 429 #define DCORE0_MME_CTRL_LO_EU_RL_CFG_RST_TOKEN_SHIFT 0 430 #define DCORE0_MME_CTRL_LO_EU_RL_CFG_RST_TOKEN_MASK 0xFF 431 #define DCORE0_MME_CTRL_LO_EU_RL_CFG_TIMEOUT_SHIFT 8 432 #define DCORE0_MME_CTRL_LO_EU_RL_CFG_TIMEOUT_MASK 0xFF00 433 #define DCORE0_MME_CTRL_LO_EU_RL_CFG_SATURATION_SHIFT 16 434 #define DCORE0_MME_CTRL_LO_EU_RL_CFG_SATURATION_MASK 0xFF0000 435 #define DCORE0_MME_CTRL_LO_EU_RL_CFG_DATA_SIZE_SHIFT 24 436 #define DCORE0_MME_CTRL_LO_EU_RL_CFG_DATA_SIZE_MASK 0xFF000000 437 438 /* DCORE0_MME_CTRL_LO_PCU_DBG_DW0 */ 439 #define DCORE0_MME_CTRL_LO_PCU_DBG_DW0_FSM_STATE_SHIFT 0 440 #define DCORE0_MME_CTRL_LO_PCU_DBG_DW0_FSM_STATE_MASK 0x1 441 #define DCORE0_MME_CTRL_LO_PCU_DBG_DW0_REAL_POOL_TOKENS_SHIFT 8 442 #define DCORE0_MME_CTRL_LO_PCU_DBG_DW0_REAL_POOL_TOKENS_MASK 0xFFFFF00 443 444 /* DCORE0_MME_CTRL_LO_PCU_DBG_DW1 */ 445 #define DCORE0_MME_CTRL_LO_PCU_DBG_DW1_ALL_POOL_TOKENS_SHIFT 0 446 #define DCORE0_MME_CTRL_LO_PCU_DBG_DW1_ALL_POOL_TOKENS_MASK 0xFFFFF 447 448 /* DCORE0_MME_CTRL_LO_PCU_DBG_DW2 */ 449 #define DCORE0_MME_CTRL_LO_PCU_DBG_DW2_BUBBLE_CYC_CNTR_SHIFT 0 450 #define DCORE0_MME_CTRL_LO_PCU_DBG_DW2_BUBBLE_CYC_CNTR_MASK 0xFFFF 451 #define DCORE0_MME_CTRL_LO_PCU_DBG_DW2_DUMMY_CYC_CNTR_SHIFT 16 452 #define DCORE0_MME_CTRL_LO_PCU_DBG_DW2_DUMMY_CYC_CNTR_MASK 0xFFFF0000 453 454 /* DCORE0_MME_CTRL_LO_PCU_DBG_DW3 */ 455 #define DCORE0_MME_CTRL_LO_PCU_DBG_DW3_REAL_MACS_HISTORY_SHIFT 0 456 #define DCORE0_MME_CTRL_LO_PCU_DBG_DW3_REAL_MACS_HISTORY_MASK 0xFFFF 457 #define DCORE0_MME_CTRL_LO_PCU_DBG_DW3_ALL_MACS_HISTORY_SHIFT 16 458 #define DCORE0_MME_CTRL_LO_PCU_DBG_DW3_ALL_MACS_HISTORY_MASK 0xFFFF0000 459 460 /* DCORE0_MME_CTRL_LO_PCU_DBG_WKL_ID */ 461 #define DCORE0_MME_CTRL_LO_PCU_DBG_WKL_ID_B_SHIFT 0 462 #define DCORE0_MME_CTRL_LO_PCU_DBG_WKL_ID_B_MASK 0xFFFFFFFF 463 464 /* DCORE0_MME_CTRL_LO_ETF_MEM_WRAP_RM */ 465 #define DCORE0_MME_CTRL_LO_ETF_MEM_WRAP_RM_V_SHIFT 0 466 #define DCORE0_MME_CTRL_LO_ETF_MEM_WRAP_RM_V_MASK 0x3FFFFFFF 467 468 #endif /* ASIC_REG_DCORE0_MME_CTRL_LO_MASKS_H_ */ 469
