1 /* SPDX-License-Identifier: GPL-2.0 2 * 3 * Copyright 2016-2020 HabanaLabs, Ltd. 4 * All Rights Reserved. 5 * 6 */ 7 8 /************************************ 9 ** This is an auto-generated file ** 10 ** DO NOT EDIT BELOW ** 11 ************************************/ 12 13 #ifndef ASIC_REG_DCORE0_HMMU0_STLB_MASKS_H_ 14 #define ASIC_REG_DCORE0_HMMU0_STLB_MASKS_H_ 15 16 /* 17 ***************************************** 18 * DCORE0_HMMU0_STLB 19 * (Prototype: STLB) 20 ***************************************** 21 */ 22 23 /* DCORE0_HMMU0_STLB_BUSY */ 24 #define DCORE0_HMMU0_STLB_BUSY_BUSY_SHIFT 0 25 #define DCORE0_HMMU0_STLB_BUSY_BUSY_MASK 0xFFFFFFFF 26 27 /* DCORE0_HMMU0_STLB_ASID */ 28 #define DCORE0_HMMU0_STLB_ASID_ASID_SHIFT 0 29 #define DCORE0_HMMU0_STLB_ASID_ASID_MASK 0x3FF 30 31 /* DCORE0_HMMU0_STLB_HOP0_PA43_12 */ 32 #define DCORE0_HMMU0_STLB_HOP0_PA43_12_HOP0_PA43_12_SHIFT 0 33 #define DCORE0_HMMU0_STLB_HOP0_PA43_12_HOP0_PA43_12_MASK 0xFFFFFFFF 34 35 /* DCORE0_HMMU0_STLB_HOP0_PA63_44 */ 36 #define DCORE0_HMMU0_STLB_HOP0_PA63_44_HOP0_PA63_44_SHIFT 0 37 #define DCORE0_HMMU0_STLB_HOP0_PA63_44_HOP0_PA63_44_MASK 0xFFFFF 38 39 /* DCORE0_HMMU0_STLB_CACHE_INV */ 40 #define DCORE0_HMMU0_STLB_CACHE_INV_PRODUCER_INDEX_SHIFT 0 41 #define DCORE0_HMMU0_STLB_CACHE_INV_PRODUCER_INDEX_MASK 0xFF 42 #define DCORE0_HMMU0_STLB_CACHE_INV_INDEX_MASK_SHIFT 8 43 #define DCORE0_HMMU0_STLB_CACHE_INV_INDEX_MASK_MASK 0xFF00 44 45 /* DCORE0_HMMU0_STLB_CACHE_INV_BASE_39_8 */ 46 #define DCORE0_HMMU0_STLB_CACHE_INV_BASE_39_8_PA_SHIFT 0 47 #define DCORE0_HMMU0_STLB_CACHE_INV_BASE_39_8_PA_MASK 0xFFFFFFFF 48 49 /* DCORE0_HMMU0_STLB_CACHE_INV_BASE_63_40 */ 50 #define DCORE0_HMMU0_STLB_CACHE_INV_BASE_63_40_PA_SHIFT 0 51 #define DCORE0_HMMU0_STLB_CACHE_INV_BASE_63_40_PA_MASK 0xFFFFFF 52 53 /* DCORE0_HMMU0_STLB_STLB_FEATURE_EN */ 54 #define DCORE0_HMMU0_STLB_STLB_FEATURE_EN_STLB_CTRL_MULTI_PAGE_SIZE_EN_SHIFT 0 55 #define DCORE0_HMMU0_STLB_STLB_FEATURE_EN_STLB_CTRL_MULTI_PAGE_SIZE_EN_MASK 0x1 56 #define DCORE0_HMMU0_STLB_STLB_FEATURE_EN_MULTI_PAGE_SIZE_EN_SHIFT 1 57 #define DCORE0_HMMU0_STLB_STLB_FEATURE_EN_MULTI_PAGE_SIZE_EN_MASK 0x2 58 #define DCORE0_HMMU0_STLB_STLB_FEATURE_EN_LOOKUP_EN_SHIFT 2 59 #define DCORE0_HMMU0_STLB_STLB_FEATURE_EN_LOOKUP_EN_MASK 0x4 60 #define DCORE0_HMMU0_STLB_STLB_FEATURE_EN_BYPASS_SHIFT 3 61 #define DCORE0_HMMU0_STLB_STLB_FEATURE_EN_BYPASS_MASK 0x8 62 #define DCORE0_HMMU0_STLB_STLB_FEATURE_EN_BANK_STOP_SHIFT 4 63 #define DCORE0_HMMU0_STLB_STLB_FEATURE_EN_BANK_STOP_MASK 0x10 64 #define DCORE0_HMMU0_STLB_STLB_FEATURE_EN_TRACE_EN_SHIFT 5 65 #define DCORE0_HMMU0_STLB_STLB_FEATURE_EN_TRACE_EN_MASK 0x20 66 #define DCORE0_HMMU0_STLB_STLB_FEATURE_EN_FOLLOWER_EN_SHIFT 6 67 #define DCORE0_HMMU0_STLB_STLB_FEATURE_EN_FOLLOWER_EN_MASK 0x40 68 #define DCORE0_HMMU0_STLB_STLB_FEATURE_EN_CACHING_EN_SHIFT 7 69 #define DCORE0_HMMU0_STLB_STLB_FEATURE_EN_CACHING_EN_MASK 0x1F80 70 #define DCORE0_HMMU0_STLB_STLB_FEATURE_EN_FOLLOWING_NUM_LIMIT_SHIFT 13 71 #define DCORE0_HMMU0_STLB_STLB_FEATURE_EN_FOLLOWING_NUM_LIMIT_MASK 0xE000 72 73 /* DCORE0_HMMU0_STLB_STLB_AXI_CACHE */ 74 #define DCORE0_HMMU0_STLB_STLB_AXI_CACHE_STLB_CTRL_ARCACHE_SHIFT 0 75 #define DCORE0_HMMU0_STLB_STLB_AXI_CACHE_STLB_CTRL_ARCACHE_MASK 0xF 76 #define DCORE0_HMMU0_STLB_STLB_AXI_CACHE_STLB_CTRL_AWCACHE_SHIFT 4 77 #define DCORE0_HMMU0_STLB_STLB_AXI_CACHE_STLB_CTRL_AWCACHE_MASK 0xF0 78 #define DCORE0_HMMU0_STLB_STLB_AXI_CACHE_INV_ARCACHE_SHIFT 8 79 #define DCORE0_HMMU0_STLB_STLB_AXI_CACHE_INV_ARCACHE_MASK 0xF00 80 81 /* DCORE0_HMMU0_STLB_HOP_CONFIGURATION */ 82 #define DCORE0_HMMU0_STLB_HOP_CONFIGURATION_FIRST_HOP_SHIFT 0 83 #define DCORE0_HMMU0_STLB_HOP_CONFIGURATION_FIRST_HOP_MASK 0x7 84 #define DCORE0_HMMU0_STLB_HOP_CONFIGURATION_FIRST_LOOKUP_HOP_SMALL_P_SHIFT 4 85 #define DCORE0_HMMU0_STLB_HOP_CONFIGURATION_FIRST_LOOKUP_HOP_SMALL_P_MASK 0x70 86 #define DCORE0_HMMU0_STLB_HOP_CONFIGURATION_FIRST_LOOKUP_HOP_LARGE_P_SHIFT 8 87 #define DCORE0_HMMU0_STLB_HOP_CONFIGURATION_FIRST_LOOKUP_HOP_LARGE_P_MASK 0x700 88 #define DCORE0_HMMU0_STLB_HOP_CONFIGURATION_LAST_HOP_SHIFT 12 89 #define DCORE0_HMMU0_STLB_HOP_CONFIGURATION_LAST_HOP_MASK 0x7000 90 #define DCORE0_HMMU0_STLB_HOP_CONFIGURATION_FOLLOWER_HOP_SHIFT 16 91 #define DCORE0_HMMU0_STLB_HOP_CONFIGURATION_FOLLOWER_HOP_MASK 0x70000 92 #define DCORE0_HMMU0_STLB_HOP_CONFIGURATION_ONLY_LARGE_PAGE_SHIFT 20 93 #define DCORE0_HMMU0_STLB_HOP_CONFIGURATION_ONLY_LARGE_PAGE_MASK 0x100000 94 #define DCORE0_HMMU0_STLB_HOP_CONFIGURATION_LARGE_PAGE_INDICATION_BIT_SHIFT 21 95 #define DCORE0_HMMU0_STLB_HOP_CONFIGURATION_LARGE_PAGE_INDICATION_BIT_MASK \ 96 0x7E00000 97 98 /* DCORE0_HMMU0_STLB_LINK_LIST_LOOKUP_MASK_63_32 */ 99 #define DCORE0_HMMU0_STLB_LINK_LIST_LOOKUP_MASK_63_32_R_SHIFT 0 100 #define DCORE0_HMMU0_STLB_LINK_LIST_LOOKUP_MASK_63_32_R_MASK 0xFFFFFFFF 101 102 /* DCORE0_HMMU0_STLB_LINK_LIST_LOOKUP_MASK_31_0 */ 103 #define DCORE0_HMMU0_STLB_LINK_LIST_LOOKUP_MASK_31_0_R_SHIFT 0 104 #define DCORE0_HMMU0_STLB_LINK_LIST_LOOKUP_MASK_31_0_R_MASK 0xFFFFFFFF 105 106 /* DCORE0_HMMU0_STLB_INV_ALL_START */ 107 #define DCORE0_HMMU0_STLB_INV_ALL_START_R_SHIFT 0 108 #define DCORE0_HMMU0_STLB_INV_ALL_START_R_MASK 0x1 109 110 /* DCORE0_HMMU0_STLB_INV_ALL_SET */ 111 #define DCORE0_HMMU0_STLB_INV_ALL_SET_R_SHIFT 0 112 #define DCORE0_HMMU0_STLB_INV_ALL_SET_R_MASK 0xFF 113 114 /* DCORE0_HMMU0_STLB_INV_PS */ 115 #define DCORE0_HMMU0_STLB_INV_PS_R_SHIFT 0 116 #define DCORE0_HMMU0_STLB_INV_PS_R_MASK 0x3 117 118 /* DCORE0_HMMU0_STLB_INV_CONSUMER_INDEX */ 119 #define DCORE0_HMMU0_STLB_INV_CONSUMER_INDEX_R_SHIFT 0 120 #define DCORE0_HMMU0_STLB_INV_CONSUMER_INDEX_R_MASK 0xFF 121 122 /* DCORE0_HMMU0_STLB_INV_HIT_COUNT */ 123 #define DCORE0_HMMU0_STLB_INV_HIT_COUNT_R_SHIFT 0 124 #define DCORE0_HMMU0_STLB_INV_HIT_COUNT_R_MASK 0x7FF 125 126 /* DCORE0_HMMU0_STLB_INV_SET */ 127 #define DCORE0_HMMU0_STLB_INV_SET_R_SHIFT 0 128 #define DCORE0_HMMU0_STLB_INV_SET_R_MASK 0xFF 129 130 /* DCORE0_HMMU0_STLB_SRAM_INIT */ 131 #define DCORE0_HMMU0_STLB_SRAM_INIT_BUSY_TAG_SHIFT 0 132 #define DCORE0_HMMU0_STLB_SRAM_INIT_BUSY_TAG_MASK 0x3 133 #define DCORE0_HMMU0_STLB_SRAM_INIT_BUSY_SLICE_SHIFT 2 134 #define DCORE0_HMMU0_STLB_SRAM_INIT_BUSY_SLICE_MASK 0xC 135 #define DCORE0_HMMU0_STLB_SRAM_INIT_BUSY_DATA_SHIFT 4 136 #define DCORE0_HMMU0_STLB_SRAM_INIT_BUSY_DATA_MASK 0x10 137 138 /* DCORE0_HMMU0_STLB_MEM_CACHE_INVALIDATION */ 139 140 /* DCORE0_HMMU0_STLB_MEM_CACHE_INV_STATUS */ 141 #define DCORE0_HMMU0_STLB_MEM_CACHE_INV_STATUS_INVALIDATE_DONE_SHIFT 0 142 #define DCORE0_HMMU0_STLB_MEM_CACHE_INV_STATUS_INVALIDATE_DONE_MASK 0x1 143 #define DCORE0_HMMU0_STLB_MEM_CACHE_INV_STATUS_CACHE_IDLE_SHIFT 1 144 #define DCORE0_HMMU0_STLB_MEM_CACHE_INV_STATUS_CACHE_IDLE_MASK 0x2 145 146 /* DCORE0_HMMU0_STLB_MEM_CACHE_BASE_38_7 */ 147 #define DCORE0_HMMU0_STLB_MEM_CACHE_BASE_38_7_R_SHIFT 0 148 #define DCORE0_HMMU0_STLB_MEM_CACHE_BASE_38_7_R_MASK 0xFFFFFFFF 149 150 /* DCORE0_HMMU0_STLB_MEM_CACHE_BASE_63_39 */ 151 #define DCORE0_HMMU0_STLB_MEM_CACHE_BASE_63_39_R_SHIFT 0 152 #define DCORE0_HMMU0_STLB_MEM_CACHE_BASE_63_39_R_MASK 0x1FFFFFF 153 154 /* DCORE0_HMMU0_STLB_MEM_CACHE_CONFIG */ 155 #define DCORE0_HMMU0_STLB_MEM_CACHE_CONFIG_CACHE_HOP_EN_SHIFT 0 156 #define DCORE0_HMMU0_STLB_MEM_CACHE_CONFIG_CACHE_HOP_EN_MASK 0x3F 157 #define DCORE0_HMMU0_STLB_MEM_CACHE_CONFIG_CACHE_HOP_PREFETCH_EN_SHIFT 6 158 #define DCORE0_HMMU0_STLB_MEM_CACHE_CONFIG_CACHE_HOP_PREFETCH_EN_MASK 0xFC0 159 #define DCORE0_HMMU0_STLB_MEM_CACHE_CONFIG_BYPASS_EN_SHIFT 12 160 #define DCORE0_HMMU0_STLB_MEM_CACHE_CONFIG_BYPASS_EN_MASK 0x1000 161 #define DCORE0_HMMU0_STLB_MEM_CACHE_CONFIG_RELEASE_INVALIDATE_SHIFT 13 162 #define DCORE0_HMMU0_STLB_MEM_CACHE_CONFIG_RELEASE_INVALIDATE_MASK 0x2000 163 164 /* DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP5 */ 165 #define DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP5_MIN_SHIFT 0 166 #define DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP5_MIN_MASK 0x1FF 167 #define DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP5_MAX_SHIFT 9 168 #define DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP5_MAX_MASK 0x3FE00 169 #define DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP5_MASK_SHIFT 18 170 #define DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP5_MASK_MASK 0x7FC0000 171 172 /* DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP4 */ 173 #define DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP4_MIN_SHIFT 0 174 #define DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP4_MIN_MASK 0x1FF 175 #define DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP4_MAX_SHIFT 9 176 #define DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP4_MAX_MASK 0x3FE00 177 #define DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP4_MASK_SHIFT 18 178 #define DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP4_MASK_MASK 0x7FC0000 179 180 /* DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP3 */ 181 #define DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP3_MIN_SHIFT 0 182 #define DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP3_MIN_MASK 0x1FF 183 #define DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP3_MAX_SHIFT 9 184 #define DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP3_MAX_MASK 0x3FE00 185 #define DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP3_MASK_SHIFT 18 186 #define DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP3_MASK_MASK 0x7FC0000 187 188 /* DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP2 */ 189 #define DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP2_MIN_SHIFT 0 190 #define DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP2_MIN_MASK 0x1FF 191 #define DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP2_MAX_SHIFT 9 192 #define DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP2_MAX_MASK 0x3FE00 193 #define DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP2_MASK_SHIFT 18 194 #define DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP2_MASK_MASK 0x7FC0000 195 196 /* DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP1 */ 197 #define DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP1_MIN_SHIFT 0 198 #define DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP1_MIN_MASK 0x1FF 199 #define DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP1_MAX_SHIFT 9 200 #define DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP1_MAX_MASK 0x3FE00 201 #define DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP1_MASK_SHIFT 18 202 #define DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP1_MASK_MASK 0x7FC0000 203 204 /* DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP0 */ 205 #define DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP0_MIN_SHIFT 0 206 #define DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP0_MIN_MASK 0x1FF 207 #define DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP0_MAX_SHIFT 9 208 #define DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP0_MAX_MASK 0x3FE00 209 #define DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP0_MASK_SHIFT 18 210 #define DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP0_MASK_MASK 0x7FC0000 211 212 /* DCORE0_HMMU0_STLB_MULTI_HIT_INTERRUPT_CLR */ 213 214 /* DCORE0_HMMU0_STLB_MULTI_HIT_INTERRUPT_MASK */ 215 #define DCORE0_HMMU0_STLB_MULTI_HIT_INTERRUPT_MASK_R_SHIFT 0 216 #define DCORE0_HMMU0_STLB_MULTI_HIT_INTERRUPT_MASK_R_MASK 0x1 217 218 /* DCORE0_HMMU0_STLB_MEM_L0_CACHE_CFG */ 219 #define DCORE0_HMMU0_STLB_MEM_L0_CACHE_CFG_PLRU_EVICTION_SHIFT 0 220 #define DCORE0_HMMU0_STLB_MEM_L0_CACHE_CFG_PLRU_EVICTION_MASK 0x1 221 #define DCORE0_HMMU0_STLB_MEM_L0_CACHE_CFG_CACHE_STOP_SHIFT 1 222 #define DCORE0_HMMU0_STLB_MEM_L0_CACHE_CFG_CACHE_STOP_MASK 0x2 223 #define DCORE0_HMMU0_STLB_MEM_L0_CACHE_CFG_INV_WRITEBACK_SHIFT 2 224 #define DCORE0_HMMU0_STLB_MEM_L0_CACHE_CFG_INV_WRITEBACK_MASK 0x4 225 226 /* DCORE0_HMMU0_STLB_MEM_READ_ARPROT */ 227 #define DCORE0_HMMU0_STLB_MEM_READ_ARPROT_R_SHIFT 0 228 #define DCORE0_HMMU0_STLB_MEM_READ_ARPROT_R_MASK 0x7 229 230 /* DCORE0_HMMU0_STLB_RANGE_CACHE_INVALIDATION */ 231 #define \ 232 DCORE0_HMMU0_STLB_RANGE_CACHE_INVALIDATION_RANGE_INVALIDATION_ENABLE_SHIFT \ 233 0 234 #define \ 235 DCORE0_HMMU0_STLB_RANGE_CACHE_INVALIDATION_RANGE_INVALIDATION_ENABLE_MASK \ 236 0x1 237 #define DCORE0_HMMU0_STLB_RANGE_CACHE_INVALIDATION_INVALIDATION_ASID_EN_SHIFT 1 238 #define DCORE0_HMMU0_STLB_RANGE_CACHE_INVALIDATION_INVALIDATION_ASID_EN_MASK 0x2 239 #define DCORE0_HMMU0_STLB_RANGE_CACHE_INVALIDATION_INVALIDATION_ASID_SHIFT 2 240 #define DCORE0_HMMU0_STLB_RANGE_CACHE_INVALIDATION_INVALIDATION_ASID_MASK 0xFFC 241 242 /* DCORE0_HMMU0_STLB_RANGE_INV_START_LSB */ 243 #define DCORE0_HMMU0_STLB_RANGE_INV_START_LSB_INV_START_LSB_SHIFT 0 244 #define DCORE0_HMMU0_STLB_RANGE_INV_START_LSB_INV_START_LSB_MASK 0xFFFFFFFF 245 246 /* DCORE0_HMMU0_STLB_RANGE_INV_START_MSB */ 247 #define DCORE0_HMMU0_STLB_RANGE_INV_START_MSB_INV_START_MSB_SHIFT 0 248 #define DCORE0_HMMU0_STLB_RANGE_INV_START_MSB_INV_START_MSB_MASK 0xFFFFF 249 250 /* DCORE0_HMMU0_STLB_RANGE_INV_END_LSB */ 251 #define DCORE0_HMMU0_STLB_RANGE_INV_END_LSB_INV_END_LSB_SHIFT 0 252 #define DCORE0_HMMU0_STLB_RANGE_INV_END_LSB_INV_END_LSB_MASK 0xFFFFFFFF 253 254 /* DCORE0_HMMU0_STLB_RANGE_INV_END_MSB */ 255 #define DCORE0_HMMU0_STLB_RANGE_INV_END_MSB_INV_END_MSB_SHIFT 0 256 #define DCORE0_HMMU0_STLB_RANGE_INV_END_MSB_INV_END_MSB_MASK 0xFFFFF 257 258 /* DCORE0_HMMU0_STLB_ASID_SCRAMBLER_CTRL */ 259 #define DCORE0_HMMU0_STLB_ASID_SCRAMBLER_CTRL_SCRAMBLER_SCRAM_EN_SHIFT 0 260 #define DCORE0_HMMU0_STLB_ASID_SCRAMBLER_CTRL_SCRAMBLER_SCRAM_EN_MASK 0x1 261 262 /* DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_0 */ 263 #define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_0_ASID_POLY_MATRIX_H3_SHIFT 0 264 #define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_0_ASID_POLY_MATRIX_H3_MASK \ 265 0x1FF 266 267 /* DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_1 */ 268 #define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_1_ASID_POLY_MATRIX_H3_SHIFT 0 269 #define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_1_ASID_POLY_MATRIX_H3_MASK \ 270 0x1FF 271 272 /* DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_2 */ 273 #define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_2_ASID_POLY_MATRIX_H3_SHIFT 0 274 #define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_2_ASID_POLY_MATRIX_H3_MASK \ 275 0x1FF 276 277 /* DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_3 */ 278 #define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_3_ASID_POLY_MATRIX_H3_SHIFT 0 279 #define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_3_ASID_POLY_MATRIX_H3_MASK \ 280 0x1FF 281 282 /* DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_4 */ 283 #define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_4_ASID_POLY_MATRIX_H3_SHIFT 0 284 #define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_4_ASID_POLY_MATRIX_H3_MASK \ 285 0x1FF 286 287 /* DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_5 */ 288 #define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_5_ASID_POLY_MATRIX_H3_SHIFT 0 289 #define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_5_ASID_POLY_MATRIX_H3_MASK \ 290 0x1FF 291 292 /* DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_6 */ 293 #define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_6_ASID_POLY_MATRIX_H3_SHIFT 0 294 #define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_6_ASID_POLY_MATRIX_H3_MASK \ 295 0x1FF 296 297 /* DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_7 */ 298 #define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_7_ASID_POLY_MATRIX_H3_SHIFT 0 299 #define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_7_ASID_POLY_MATRIX_H3_MASK \ 300 0x1FF 301 302 /* DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_8 */ 303 #define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_8_ASID_POLY_MATRIX_H3_SHIFT 0 304 #define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_8_ASID_POLY_MATRIX_H3_MASK \ 305 0x1FF 306 307 /* DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_9 */ 308 #define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_9_ASID_POLY_MATRIX_H3_SHIFT 0 309 #define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_9_ASID_POLY_MATRIX_H3_MASK \ 310 0x1FF 311 312 /* DCORE0_HMMU0_STLB_ASID_SCR_POLY_MAT_H3_10 */ 313 #define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MAT_H3_10_ASID_POLY_MATRIX_H3_SHIFT 0 314 #define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MAT_H3_10_ASID_POLY_MATRIX_H3_MASK 0x1FF 315 316 /* DCORE0_HMMU0_STLB_ASID_SCR_POLY_MAT_H3_11 */ 317 #define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MAT_H3_11_ASID_POLY_MATRIX_H3_SHIFT 0 318 #define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MAT_H3_11_ASID_POLY_MATRIX_H3_MASK 0x1FF 319 320 /* DCORE0_HMMU0_STLB_ASID_SCR_POLY_MAT_H3_12 */ 321 #define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MAT_H3_12_ASID_POLY_MATRIX_H3_SHIFT 0 322 #define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MAT_H3_12_ASID_POLY_MATRIX_H3_MASK 0x1FF 323 324 /* DCORE0_HMMU0_STLB_ASID_SCR_POLY_MAT_H3_13 */ 325 #define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MAT_H3_13_ASID_POLY_MATRIX_H3_SHIFT 0 326 #define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MAT_H3_13_ASID_POLY_MATRIX_H3_MASK 0x1FF 327 328 /* DCORE0_HMMU0_STLB_ASID_SCR_POLY_MAT_H3_14 */ 329 #define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MAT_H3_14_ASID_POLY_MATRIX_H3_SHIFT 0 330 #define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MAT_H3_14_ASID_POLY_MATRIX_H3_MASK 0x1FF 331 332 /* DCORE0_HMMU0_STLB_ASID_SCR_POLY_MAT_H3_15 */ 333 #define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MAT_H3_15_ASID_POLY_MATRIX_H3_SHIFT 0 334 #define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MAT_H3_15_ASID_POLY_MATRIX_H3_MASK 0x1FF 335 336 /* DCORE0_HMMU0_STLB_ASID_SCR_POLY_MAT_H3_16 */ 337 #define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MAT_H3_16_ASID_POLY_MATRIX_H3_SHIFT 0 338 #define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MAT_H3_16_ASID_POLY_MATRIX_H3_MASK 0x1FF 339 340 /* DCORE0_HMMU0_STLB_ASID_SCR_POLY_MAT_H3_17 */ 341 #define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MAT_H3_17_ASID_POLY_MATRIX_H3_SHIFT 0 342 #define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MAT_H3_17_ASID_POLY_MATRIX_H3_MASK 0x1FF 343 344 /* DCORE0_HMMU0_STLB_ASID_SCR_POLY_MAT_H3_18 */ 345 #define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MAT_H3_18_ASID_POLY_MATRIX_H3_SHIFT 0 346 #define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MAT_H3_18_ASID_POLY_MATRIX_H3_MASK 0x1FF 347 348 #endif /* ASIC_REG_DCORE0_HMMU0_STLB_MASKS_H_ */ 349
