1 /* 2 * Copyright 2012-15 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef __DC_LINK_ENCODER__DCE110_H__ 27 #define __DC_LINK_ENCODER__DCE110_H__ 28 29 #include "link_encoder.h" 30 31 #define TO_DCE110_LINK_ENC(link_encoder)\ 32 container_of(link_encoder, struct dce110_link_encoder, base) 33 34 /* Not found regs in dce120 spec 35 * BIOS_SCRATCH_2 36 * DP_DPHY_INTERNAL_CTRL 37 */ 38 39 #define AUX_REG_LIST(id)\ 40 SRI(AUX_CONTROL, DP_AUX, id), \ 41 SRI(AUX_DPHY_RX_CONTROL0, DP_AUX, id) 42 43 #define HPD_REG_LIST(id)\ 44 SRI(DC_HPD_CONTROL, HPD, id) 45 46 #define LE_COMMON_REG_LIST_BASE(id) \ 47 SR(DMCU_RAM_ACCESS_CTRL), \ 48 SR(DMCU_IRAM_RD_CTRL), \ 49 SR(DMCU_IRAM_RD_DATA), \ 50 SR(DMCU_INTERRUPT_TO_UC_EN_MASK), \ 51 SRI(DIG_BE_CNTL, DIG, id), \ 52 SRI(DIG_BE_EN_CNTL, DIG, id), \ 53 SRI(DP_CONFIG, DP, id), \ 54 SRI(DP_DPHY_CNTL, DP, id), \ 55 SRI(DP_DPHY_PRBS_CNTL, DP, id), \ 56 SRI(DP_DPHY_SCRAM_CNTL, DP, id),\ 57 SRI(DP_DPHY_SYM0, DP, id), \ 58 SRI(DP_DPHY_SYM1, DP, id), \ 59 SRI(DP_DPHY_SYM2, DP, id), \ 60 SRI(DP_DPHY_TRAINING_PATTERN_SEL, DP, id), \ 61 SRI(DP_LINK_CNTL, DP, id), \ 62 SRI(DP_LINK_FRAMING_CNTL, DP, id), \ 63 SRI(DP_MSE_SAT0, DP, id), \ 64 SRI(DP_MSE_SAT1, DP, id), \ 65 SRI(DP_MSE_SAT2, DP, id), \ 66 SRI(DP_MSE_SAT_UPDATE, DP, id), \ 67 SRI(DP_SEC_CNTL, DP, id), \ 68 SRI(DP_VID_STREAM_CNTL, DP, id), \ 69 SRI(DP_DPHY_FAST_TRAINING, DP, id), \ 70 SRI(DP_SEC_CNTL1, DP, id) 71 72 #define LE_COMMON_REG_LIST(id)\ 73 LE_COMMON_REG_LIST_BASE(id), \ 74 SRI(DP_DPHY_BS_SR_SWAP_CNTL, DP, id), \ 75 SRI(DP_DPHY_INTERNAL_CTRL, DP, id), \ 76 SR(DCI_MEM_PWR_STATUS) 77 78 #define LE_DCE80_REG_LIST(id)\ 79 SRI(DP_DPHY_INTERNAL_CTRL, DP, id), \ 80 LE_COMMON_REG_LIST_BASE(id) 81 82 #define LE_DCE100_REG_LIST(id)\ 83 LE_COMMON_REG_LIST_BASE(id), \ 84 SRI(DP_DPHY_BS_SR_SWAP_CNTL, DP, id), \ 85 SRI(DP_DPHY_INTERNAL_CTRL, DP, id), \ 86 SR(DCI_MEM_PWR_STATUS) 87 88 #define LE_DCE110_REG_LIST(id)\ 89 LE_COMMON_REG_LIST_BASE(id), \ 90 SRI(DP_DPHY_BS_SR_SWAP_CNTL, DP, id), \ 91 SRI(DP_DPHY_INTERNAL_CTRL, DP, id), \ 92 SRI(DP_DPHY_HBR2_PATTERN_CONTROL, DP, id), \ 93 SR(DCI_MEM_PWR_STATUS) 94 95 #define LE_DCE120_REG_LIST(id)\ 96 LE_COMMON_REG_LIST_BASE(id), \ 97 SRI(DP_DPHY_BS_SR_SWAP_CNTL, DP, id), \ 98 SRI(DP_DPHY_HBR2_PATTERN_CONTROL, DP, id), \ 99 SR(DCI_MEM_PWR_STATUS) 100 101 #define LE_DCN10_REG_LIST(id)\ 102 LE_COMMON_REG_LIST_BASE(id), \ 103 SRI(DP_DPHY_BS_SR_SWAP_CNTL, DP, id), \ 104 SRI(DP_DPHY_INTERNAL_CTRL, DP, id), \ 105 SRI(DP_DPHY_HBR2_PATTERN_CONTROL, DP, id) 106 107 struct dce110_link_enc_aux_registers { 108 uint32_t AUX_CONTROL; 109 uint32_t AUX_DPHY_RX_CONTROL0; 110 }; 111 112 struct dce110_link_enc_hpd_registers { 113 uint32_t DC_HPD_CONTROL; 114 }; 115 116 struct dce110_link_enc_registers { 117 /* DMCU registers */ 118 uint32_t MASTER_COMM_DATA_REG1; 119 uint32_t MASTER_COMM_DATA_REG2; 120 uint32_t MASTER_COMM_DATA_REG3; 121 uint32_t MASTER_COMM_CMD_REG; 122 uint32_t MASTER_COMM_CNTL_REG; 123 uint32_t DMCU_RAM_ACCESS_CTRL; 124 uint32_t DCI_MEM_PWR_STATUS; 125 uint32_t DMU_MEM_PWR_CNTL; 126 uint32_t DMCU_IRAM_RD_CTRL; 127 uint32_t DMCU_IRAM_RD_DATA; 128 uint32_t DMCU_INTERRUPT_TO_UC_EN_MASK; 129 130 /* Common DP registers */ 131 uint32_t DIG_BE_CNTL; 132 uint32_t DIG_BE_EN_CNTL; 133 uint32_t DP_CONFIG; 134 uint32_t DP_DPHY_CNTL; 135 uint32_t DP_DPHY_INTERNAL_CTRL; 136 uint32_t DP_DPHY_PRBS_CNTL; 137 uint32_t DP_DPHY_SCRAM_CNTL; 138 uint32_t DP_DPHY_SYM0; 139 uint32_t DP_DPHY_SYM1; 140 uint32_t DP_DPHY_SYM2; 141 uint32_t DP_DPHY_TRAINING_PATTERN_SEL; 142 uint32_t DP_LINK_CNTL; 143 uint32_t DP_LINK_FRAMING_CNTL; 144 uint32_t DP_MSE_SAT0; 145 uint32_t DP_MSE_SAT1; 146 uint32_t DP_MSE_SAT2; 147 uint32_t DP_MSE_SAT_UPDATE; 148 uint32_t DP_SEC_CNTL; 149 uint32_t DP_VID_STREAM_CNTL; 150 uint32_t DP_DPHY_FAST_TRAINING; 151 uint32_t DP_DPHY_BS_SR_SWAP_CNTL; 152 uint32_t DP_DPHY_HBR2_PATTERN_CONTROL; 153 uint32_t DP_SEC_CNTL1; 154 }; 155 156 struct dce110_link_encoder { 157 struct link_encoder base; 158 const struct dce110_link_enc_registers *link_regs; 159 const struct dce110_link_enc_aux_registers *aux_regs; 160 const struct dce110_link_enc_hpd_registers *hpd_regs; 161 }; 162 163 164 void dce110_link_encoder_construct( 165 struct dce110_link_encoder *enc110, 166 const struct encoder_init_data *init_data, 167 const struct encoder_feature_support *enc_features, 168 const struct dce110_link_enc_registers *link_regs, 169 const struct dce110_link_enc_aux_registers *aux_regs, 170 const struct dce110_link_enc_hpd_registers *hpd_regs); 171 172 bool dce110_link_encoder_validate_dvi_output( 173 const struct dce110_link_encoder *enc110, 174 enum signal_type connector_signal, 175 enum signal_type signal, 176 const struct dc_crtc_timing *crtc_timing); 177 178 bool dce110_link_encoder_validate_rgb_output( 179 const struct dce110_link_encoder *enc110, 180 const struct dc_crtc_timing *crtc_timing); 181 182 bool dce110_link_encoder_validate_dp_output( 183 const struct dce110_link_encoder *enc110, 184 const struct dc_crtc_timing *crtc_timing); 185 186 bool dce110_link_encoder_validate_wireless_output( 187 const struct dce110_link_encoder *enc110, 188 const struct dc_crtc_timing *crtc_timing); 189 190 bool dce110_link_encoder_validate_output_with_stream( 191 struct link_encoder *enc, 192 const struct dc_stream_state *stream); 193 194 /****************** HW programming ************************/ 195 196 /* initialize HW */ /* why do we initialze aux in here? */ 197 void dce110_link_encoder_hw_init(struct link_encoder *enc); 198 199 void dce110_link_encoder_destroy(struct link_encoder **enc); 200 201 /* program DIG_MODE in DIG_BE */ 202 /* TODO can this be combined with enable_output? */ 203 void dce110_link_encoder_setup( 204 struct link_encoder *enc, 205 enum signal_type signal); 206 207 /* enables TMDS PHY output */ 208 /* TODO: still need depth or just pass in adjusted pixel clock? */ 209 void dce110_link_encoder_enable_tmds_output( 210 struct link_encoder *enc, 211 enum clock_source_id clock_source, 212 enum dc_color_depth color_depth, 213 enum signal_type signal, 214 uint32_t pixel_clock); 215 216 /* enables DP PHY output */ 217 void dce110_link_encoder_enable_dp_output( 218 struct link_encoder *enc, 219 const struct dc_link_settings *link_settings, 220 enum clock_source_id clock_source); 221 222 /* enables DP PHY output in MST mode */ 223 void dce110_link_encoder_enable_dp_mst_output( 224 struct link_encoder *enc, 225 const struct dc_link_settings *link_settings, 226 enum clock_source_id clock_source); 227 228 /* disable PHY output */ 229 void dce110_link_encoder_disable_output( 230 struct link_encoder *enc, 231 enum signal_type signal); 232 233 /* set DP lane settings */ 234 void dce110_link_encoder_dp_set_lane_settings( 235 struct link_encoder *enc, 236 const struct link_training_settings *link_settings); 237 238 void dce110_link_encoder_dp_set_phy_pattern( 239 struct link_encoder *enc, 240 const struct encoder_set_dp_phy_pattern_param *param); 241 242 /* programs DP MST VC payload allocation */ 243 void dce110_link_encoder_update_mst_stream_allocation_table( 244 struct link_encoder *enc, 245 const struct link_mst_stream_allocation_table *table); 246 247 void dce110_link_encoder_connect_dig_be_to_fe( 248 struct link_encoder *enc, 249 enum engine_id engine, 250 bool connect); 251 252 void dce110_link_encoder_set_dp_phy_pattern_training_pattern( 253 struct link_encoder *enc, 254 uint32_t index); 255 256 void dce110_link_encoder_enable_hpd(struct link_encoder *enc); 257 258 void dce110_link_encoder_disable_hpd(struct link_encoder *enc); 259 260 void dce110_psr_program_dp_dphy_fast_training(struct link_encoder *enc, 261 bool exit_link_training_required); 262 263 void dce110_psr_program_secondary_packet(struct link_encoder *enc, 264 unsigned int sdp_transmit_line_num_deadline); 265 266 bool dce110_is_dig_enabled(struct link_encoder *enc); 267 268 #endif /* __DC_LINK_ENCODER__DCE110_H__ */ 269
