1 /* Copyright 2012-15 Advanced Micro Devices, Inc. 2 * 3 * Permission is hereby granted, free of charge, to any person obtaining a 4 * copy of this software and associated documentation files (the "Software"), 5 * to deal in the Software without restriction, including without limitation 6 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 7 * and/or sell copies of the Software, and to permit persons to whom the 8 * Software is furnished to do so, subject to the following conditions: 9 * 10 * The above copyright notice and this permission notice shall be included in 11 * all copies or substantial portions of the Software. 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 15 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 16 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 17 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 18 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 19 * OTHER DEALINGS IN THE SOFTWARE. 20 * 21 * Authors: AMD 22 * 23 */ 24 25 #ifndef __DC_CLOCK_SOURCE_DCE_H__ 26 #define __DC_CLOCK_SOURCE_DCE_H__ 27 28 #include "../inc/clock_source.h" 29 30 #define TO_DCE110_CLK_SRC(clk_src)\ 31 container_of(clk_src, struct dce110_clk_src, base) 32 33 #define CS_COMMON_REG_LIST_DCE_100_110(id) \ 34 SRI(RESYNC_CNTL, PIXCLK, id), \ 35 SRI(PLL_CNTL, BPHYC_PLL, id) 36 37 #define CS_COMMON_REG_LIST_DCE_80(id) \ 38 SRI(RESYNC_CNTL, PIXCLK, id), \ 39 SRI(PLL_CNTL, DCCG_PLL, id) 40 41 #define CS_COMMON_REG_LIST_DCE_112(id) \ 42 SRI(PIXCLK_RESYNC_CNTL, PHYPLL, id) 43 44 45 #define CS_SF(reg_name, field_name, post_fix)\ 46 .field_name = reg_name ## __ ## field_name ## post_fix 47 48 #define CS_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh)\ 49 CS_SF(PLL_CNTL, PLL_REF_DIV_SRC, mask_sh),\ 50 CS_SF(PIXCLK1_RESYNC_CNTL, DCCG_DEEP_COLOR_CNTL1, mask_sh),\ 51 CS_SF(PLL_POST_DIV, PLL_POST_DIV_PIXCLK, mask_sh),\ 52 CS_SF(PLL_REF_DIV, PLL_REF_DIV, mask_sh) 53 54 #define CS_COMMON_MASK_SH_LIST_DCE_112(mask_sh)\ 55 CS_SF(PHYPLLA_PIXCLK_RESYNC_CNTL, PHYPLLA_DCCG_DEEP_COLOR_CNTL, mask_sh),\ 56 CS_SF(PHYPLLA_PIXCLK_RESYNC_CNTL, PHYPLLA_PIXCLK_DOUBLE_RATE_ENABLE, mask_sh) 57 58 #define CS_COMMON_REG_LIST_DCN2_0(index, pllid) \ 59 SRI(PIXCLK_RESYNC_CNTL, PHYPLL, pllid),\ 60 SRII(PHASE, DP_DTO, 0),\ 61 SRII(PHASE, DP_DTO, 1),\ 62 SRII(PHASE, DP_DTO, 2),\ 63 SRII(PHASE, DP_DTO, 3),\ 64 SRII(PHASE, DP_DTO, 4),\ 65 SRII(PHASE, DP_DTO, 5),\ 66 SRII(MODULO, DP_DTO, 0),\ 67 SRII(MODULO, DP_DTO, 1),\ 68 SRII(MODULO, DP_DTO, 2),\ 69 SRII(MODULO, DP_DTO, 3),\ 70 SRII(MODULO, DP_DTO, 4),\ 71 SRII(MODULO, DP_DTO, 5),\ 72 SRII(PIXEL_RATE_CNTL, OTG, 0),\ 73 SRII(PIXEL_RATE_CNTL, OTG, 1),\ 74 SRII(PIXEL_RATE_CNTL, OTG, 2),\ 75 SRII(PIXEL_RATE_CNTL, OTG, 3),\ 76 SRII(PIXEL_RATE_CNTL, OTG, 4),\ 77 SRII(PIXEL_RATE_CNTL, OTG, 5) 78 79 #define CS_COMMON_REG_LIST_DCN2_1(index, pllid) \ 80 SRI(PIXCLK_RESYNC_CNTL, PHYPLL, pllid),\ 81 SRII(PHASE, DP_DTO, 0),\ 82 SRII(PHASE, DP_DTO, 1),\ 83 SRII(PHASE, DP_DTO, 2),\ 84 SRII(PHASE, DP_DTO, 3),\ 85 SRII(MODULO, DP_DTO, 0),\ 86 SRII(MODULO, DP_DTO, 1),\ 87 SRII(MODULO, DP_DTO, 2),\ 88 SRII(MODULO, DP_DTO, 3),\ 89 SRII(PIXEL_RATE_CNTL, OTG, 0),\ 90 SRII(PIXEL_RATE_CNTL, OTG, 1),\ 91 SRII(PIXEL_RATE_CNTL, OTG, 2),\ 92 SRII(PIXEL_RATE_CNTL, OTG, 3) 93 94 #if defined(CONFIG_DRM_AMD_DC_DCN) 95 #define CS_COMMON_REG_LIST_DCN3_0(index, pllid) \ 96 SRI(PIXCLK_RESYNC_CNTL, PHYPLL, pllid),\ 97 SRII(PHASE, DP_DTO, 0),\ 98 SRII(PHASE, DP_DTO, 1),\ 99 SRII(PHASE, DP_DTO, 2),\ 100 SRII(PHASE, DP_DTO, 3),\ 101 SRII(MODULO, DP_DTO, 0),\ 102 SRII(MODULO, DP_DTO, 1),\ 103 SRII(MODULO, DP_DTO, 2),\ 104 SRII(MODULO, DP_DTO, 3),\ 105 SRII(PIXEL_RATE_CNTL, OTG, 0),\ 106 SRII(PIXEL_RATE_CNTL, OTG, 1),\ 107 SRII(PIXEL_RATE_CNTL, OTG, 2),\ 108 SRII(PIXEL_RATE_CNTL, OTG, 3) 109 110 #define CS_COMMON_REG_LIST_DCN3_01(index, pllid) \ 111 SRI(PIXCLK_RESYNC_CNTL, PHYPLL, pllid),\ 112 SRII(PHASE, DP_DTO, 0),\ 113 SRII(PHASE, DP_DTO, 1),\ 114 SRII(PHASE, DP_DTO, 2),\ 115 SRII(PHASE, DP_DTO, 3),\ 116 SRII(MODULO, DP_DTO, 0),\ 117 SRII(MODULO, DP_DTO, 1),\ 118 SRII(MODULO, DP_DTO, 2),\ 119 SRII(MODULO, DP_DTO, 3),\ 120 SRII(PIXEL_RATE_CNTL, OTG, 0),\ 121 SRII(PIXEL_RATE_CNTL, OTG, 1),\ 122 SRII(PIXEL_RATE_CNTL, OTG, 2),\ 123 SRII(PIXEL_RATE_CNTL, OTG, 3) 124 #endif 125 126 #if defined(CONFIG_DRM_AMD_DC_DCN) 127 #define CS_COMMON_REG_LIST_DCN3_02(index, pllid) \ 128 SRI(PIXCLK_RESYNC_CNTL, PHYPLL, pllid),\ 129 SRII(PHASE, DP_DTO, 0),\ 130 SRII(PHASE, DP_DTO, 1),\ 131 SRII(PHASE, DP_DTO, 2),\ 132 SRII(PHASE, DP_DTO, 3),\ 133 SRII(PHASE, DP_DTO, 4),\ 134 SRII(MODULO, DP_DTO, 0),\ 135 SRII(MODULO, DP_DTO, 1),\ 136 SRII(MODULO, DP_DTO, 2),\ 137 SRII(MODULO, DP_DTO, 3),\ 138 SRII(MODULO, DP_DTO, 4),\ 139 SRII(PIXEL_RATE_CNTL, OTG, 0),\ 140 SRII(PIXEL_RATE_CNTL, OTG, 1),\ 141 SRII(PIXEL_RATE_CNTL, OTG, 2),\ 142 SRII(PIXEL_RATE_CNTL, OTG, 3),\ 143 SRII(PIXEL_RATE_CNTL, OTG, 4) 144 145 #define CS_COMMON_REG_LIST_DCN3_03(index, pllid) \ 146 SRI(PIXCLK_RESYNC_CNTL, PHYPLL, pllid),\ 147 SRII(PHASE, DP_DTO, 0),\ 148 SRII(PHASE, DP_DTO, 1),\ 149 SRII(MODULO, DP_DTO, 0),\ 150 SRII(MODULO, DP_DTO, 1),\ 151 SRII(PIXEL_RATE_CNTL, OTG, 0),\ 152 SRII(PIXEL_RATE_CNTL, OTG, 1) 153 154 #endif 155 #define CS_COMMON_MASK_SH_LIST_DCN2_0(mask_sh)\ 156 CS_SF(DP_DTO0_PHASE, DP_DTO0_PHASE, mask_sh),\ 157 CS_SF(DP_DTO0_MODULO, DP_DTO0_MODULO, mask_sh),\ 158 CS_SF(PHYPLLA_PIXCLK_RESYNC_CNTL, PHYPLLA_DCCG_DEEP_COLOR_CNTL, mask_sh),\ 159 CS_SF(OTG0_PIXEL_RATE_CNTL, DP_DTO0_ENABLE, mask_sh) 160 161 #if defined(CONFIG_DRM_AMD_DC_DCN) 162 163 #define CS_COMMON_REG_LIST_DCN1_0(index, pllid) \ 164 SRI(PIXCLK_RESYNC_CNTL, PHYPLL, pllid),\ 165 SRII(PHASE, DP_DTO, 0),\ 166 SRII(PHASE, DP_DTO, 1),\ 167 SRII(PHASE, DP_DTO, 2),\ 168 SRII(PHASE, DP_DTO, 3),\ 169 SRII(MODULO, DP_DTO, 0),\ 170 SRII(MODULO, DP_DTO, 1),\ 171 SRII(MODULO, DP_DTO, 2),\ 172 SRII(MODULO, DP_DTO, 3),\ 173 SRII(PIXEL_RATE_CNTL, OTG, 0), \ 174 SRII(PIXEL_RATE_CNTL, OTG, 1), \ 175 SRII(PIXEL_RATE_CNTL, OTG, 2), \ 176 SRII(PIXEL_RATE_CNTL, OTG, 3) 177 178 #define CS_COMMON_MASK_SH_LIST_DCN1_0(mask_sh)\ 179 CS_SF(DP_DTO0_PHASE, DP_DTO0_PHASE, mask_sh),\ 180 CS_SF(DP_DTO0_MODULO, DP_DTO0_MODULO, mask_sh),\ 181 CS_SF(PHYPLLA_PIXCLK_RESYNC_CNTL, PHYPLLA_DCCG_DEEP_COLOR_CNTL, mask_sh),\ 182 CS_SF(OTG0_PIXEL_RATE_CNTL, DP_DTO0_ENABLE, mask_sh) 183 184 #endif 185 186 #define CS_REG_FIELD_LIST(type) \ 187 type PLL_REF_DIV_SRC; \ 188 type DCCG_DEEP_COLOR_CNTL1; \ 189 type PHYPLLA_DCCG_DEEP_COLOR_CNTL; \ 190 type PHYPLLA_PIXCLK_DOUBLE_RATE_ENABLE; \ 191 type PLL_POST_DIV_PIXCLK; \ 192 type PLL_REF_DIV; \ 193 type DP_DTO0_PHASE; \ 194 type DP_DTO0_MODULO; \ 195 type DP_DTO0_ENABLE; 196 197 struct dce110_clk_src_shift { 198 CS_REG_FIELD_LIST(uint8_t) 199 }; 200 201 struct dce110_clk_src_mask{ 202 CS_REG_FIELD_LIST(uint32_t) 203 }; 204 205 struct dce110_clk_src_regs { 206 uint32_t RESYNC_CNTL; 207 uint32_t PIXCLK_RESYNC_CNTL; 208 uint32_t PLL_CNTL; 209 210 /* below are for DTO. 211 * todo: should probably use different struct to not waste space 212 */ 213 uint32_t PHASE[MAX_PIPES]; 214 uint32_t MODULO[MAX_PIPES]; 215 uint32_t PIXEL_RATE_CNTL[MAX_PIPES]; 216 }; 217 218 struct dce110_clk_src { 219 struct clock_source base; 220 const struct dce110_clk_src_regs *regs; 221 const struct dce110_clk_src_mask *cs_mask; 222 const struct dce110_clk_src_shift *cs_shift; 223 struct dc_bios *bios; 224 225 struct spread_spectrum_data *dp_ss_params; 226 uint32_t dp_ss_params_cnt; 227 struct spread_spectrum_data *hdmi_ss_params; 228 uint32_t hdmi_ss_params_cnt; 229 struct spread_spectrum_data *dvi_ss_params; 230 uint32_t dvi_ss_params_cnt; 231 struct spread_spectrum_data *lvds_ss_params; 232 uint32_t lvds_ss_params_cnt; 233 234 uint32_t ext_clk_khz; 235 uint32_t ref_freq_khz; 236 237 struct calc_pll_clock_source calc_pll; 238 struct calc_pll_clock_source calc_pll_hdmi; 239 }; 240 241 bool dce110_clk_src_construct( 242 struct dce110_clk_src *clk_src, 243 struct dc_context *ctx, 244 struct dc_bios *bios, 245 enum clock_source_id, 246 const struct dce110_clk_src_regs *regs, 247 const struct dce110_clk_src_shift *cs_shift, 248 const struct dce110_clk_src_mask *cs_mask); 249 250 bool dce112_clk_src_construct( 251 struct dce110_clk_src *clk_src, 252 struct dc_context *ctx, 253 struct dc_bios *bios, 254 enum clock_source_id id, 255 const struct dce110_clk_src_regs *regs, 256 const struct dce110_clk_src_shift *cs_shift, 257 const struct dce110_clk_src_mask *cs_mask); 258 259 bool dcn20_clk_src_construct( 260 struct dce110_clk_src *clk_src, 261 struct dc_context *ctx, 262 struct dc_bios *bios, 263 enum clock_source_id id, 264 const struct dce110_clk_src_regs *regs, 265 const struct dce110_clk_src_shift *cs_shift, 266 const struct dce110_clk_src_mask *cs_mask); 267 268 #if defined(CONFIG_DRM_AMD_DC_DCN) 269 bool dcn3_clk_src_construct( 270 struct dce110_clk_src *clk_src, 271 struct dc_context *ctx, 272 struct dc_bios *bios, 273 enum clock_source_id id, 274 const struct dce110_clk_src_regs *regs, 275 const struct dce110_clk_src_shift *cs_shift, 276 const struct dce110_clk_src_mask *cs_mask); 277 278 bool dcn301_clk_src_construct( 279 struct dce110_clk_src *clk_src, 280 struct dc_context *ctx, 281 struct dc_bios *bios, 282 enum clock_source_id id, 283 const struct dce110_clk_src_regs *regs, 284 const struct dce110_clk_src_shift *cs_shift, 285 const struct dce110_clk_src_mask *cs_mask); 286 #endif 287 288 /* this table is use to find *1.001 and /1.001 pixel rates from non-precise pixel rate */ 289 struct pixel_rate_range_table_entry { 290 unsigned int range_min_khz; 291 unsigned int range_max_khz; 292 unsigned int target_pixel_rate_khz; 293 unsigned short mult_factor; 294 unsigned short div_factor; 295 }; 296 297 #if defined(CONFIG_DRM_AMD_DC_DCN) 298 extern const struct pixel_rate_range_table_entry video_optimized_pixel_rates[]; 299 const struct pixel_rate_range_table_entry *look_up_in_video_optimized_rate_tlb( 300 unsigned int pixel_rate_khz); 301 #endif 302 303 #endif 304
