1 /* Copyright 2012-15 Advanced Micro Devices, Inc. 2 * 3 * Permission is hereby granted, free of charge, to any person obtaining a 4 * copy of this software and associated documentation files (the "Software"), 5 * to deal in the Software without restriction, including without limitation 6 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 7 * and/or sell copies of the Software, and to permit persons to whom the 8 * Software is furnished to do so, subject to the following conditions: 9 * 10 * The above copyright notice and this permission notice shall be included in 11 * all copies or substantial portions of the Software. 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 15 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 16 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 17 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 18 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 19 * OTHER DEALINGS IN THE SOFTWARE. 20 * 21 * Authors: AMD 22 * 23 */ 24 25 #ifndef __DC_CLOCK_SOURCE_DCE_H__ 26 #define __DC_CLOCK_SOURCE_DCE_H__ 27 28 #include "../inc/clock_source.h" 29 30 #define TO_DCE110_CLK_SRC(clk_src)\ 31 container_of(clk_src, struct dce110_clk_src, base) 32 33 #define CS_COMMON_REG_LIST_DCE_100_110(id) \ 34 SRI(RESYNC_CNTL, PIXCLK, id), \ 35 SRI(PLL_CNTL, BPHYC_PLL, id) 36 37 #define CS_COMMON_REG_LIST_DCE_80(id) \ 38 SRI(RESYNC_CNTL, PIXCLK, id), \ 39 SRI(PLL_CNTL, DCCG_PLL, id) 40 41 #define CS_COMMON_REG_LIST_DCE_112(id) \ 42 SRI(PIXCLK_RESYNC_CNTL, PHYPLL, id) 43 44 45 #define CS_SF(reg_name, field_name, post_fix)\ 46 .field_name = reg_name ## __ ## field_name ## post_fix 47 48 #define CS_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh)\ 49 CS_SF(PLL_CNTL, PLL_REF_DIV_SRC, mask_sh),\ 50 CS_SF(PIXCLK1_RESYNC_CNTL, DCCG_DEEP_COLOR_CNTL1, mask_sh),\ 51 CS_SF(PLL_POST_DIV, PLL_POST_DIV_PIXCLK, mask_sh),\ 52 CS_SF(PLL_REF_DIV, PLL_REF_DIV, mask_sh) 53 54 #define CS_COMMON_MASK_SH_LIST_DCE_112(mask_sh)\ 55 CS_SF(PHYPLLA_PIXCLK_RESYNC_CNTL, PHYPLLA_DCCG_DEEP_COLOR_CNTL, mask_sh),\ 56 CS_SF(PHYPLLA_PIXCLK_RESYNC_CNTL, PHYPLLA_PIXCLK_DOUBLE_RATE_ENABLE, mask_sh) 57 58 #define CS_COMMON_REG_LIST_DCN2_0(index, pllid) \ 59 SRI(PIXCLK_RESYNC_CNTL, PHYPLL, pllid),\ 60 SRII(PHASE, DP_DTO, 0),\ 61 SRII(PHASE, DP_DTO, 1),\ 62 SRII(PHASE, DP_DTO, 2),\ 63 SRII(PHASE, DP_DTO, 3),\ 64 SRII(PHASE, DP_DTO, 4),\ 65 SRII(PHASE, DP_DTO, 5),\ 66 SRII(MODULO, DP_DTO, 0),\ 67 SRII(MODULO, DP_DTO, 1),\ 68 SRII(MODULO, DP_DTO, 2),\ 69 SRII(MODULO, DP_DTO, 3),\ 70 SRII(MODULO, DP_DTO, 4),\ 71 SRII(MODULO, DP_DTO, 5),\ 72 SRII(PIXEL_RATE_CNTL, OTG, 0),\ 73 SRII(PIXEL_RATE_CNTL, OTG, 1),\ 74 SRII(PIXEL_RATE_CNTL, OTG, 2),\ 75 SRII(PIXEL_RATE_CNTL, OTG, 3),\ 76 SRII(PIXEL_RATE_CNTL, OTG, 4),\ 77 SRII(PIXEL_RATE_CNTL, OTG, 5) 78 79 #define CS_COMMON_REG_LIST_DCN2_1(index, pllid) \ 80 SRI(PIXCLK_RESYNC_CNTL, PHYPLL, pllid),\ 81 SRII(PHASE, DP_DTO, 0),\ 82 SRII(PHASE, DP_DTO, 1),\ 83 SRII(PHASE, DP_DTO, 2),\ 84 SRII(PHASE, DP_DTO, 3),\ 85 SRII(MODULO, DP_DTO, 0),\ 86 SRII(MODULO, DP_DTO, 1),\ 87 SRII(MODULO, DP_DTO, 2),\ 88 SRII(MODULO, DP_DTO, 3),\ 89 SRII(PIXEL_RATE_CNTL, OTG, 0),\ 90 SRII(PIXEL_RATE_CNTL, OTG, 1),\ 91 SRII(PIXEL_RATE_CNTL, OTG, 2),\ 92 SRII(PIXEL_RATE_CNTL, OTG, 3) 93 94 #if defined(CONFIG_DRM_AMD_DC_DCN3_0) 95 #define CS_COMMON_REG_LIST_DCN3_0(index, pllid) \ 96 SRI(PIXCLK_RESYNC_CNTL, PHYPLL, pllid),\ 97 SRII(PHASE, DP_DTO, 0),\ 98 SRII(PHASE, DP_DTO, 1),\ 99 SRII(PHASE, DP_DTO, 2),\ 100 SRII(PHASE, DP_DTO, 3),\ 101 SRII(MODULO, DP_DTO, 0),\ 102 SRII(MODULO, DP_DTO, 1),\ 103 SRII(MODULO, DP_DTO, 2),\ 104 SRII(MODULO, DP_DTO, 3),\ 105 SRII(PIXEL_RATE_CNTL, OTG, 0),\ 106 SRII(PIXEL_RATE_CNTL, OTG, 1),\ 107 SRII(PIXEL_RATE_CNTL, OTG, 2),\ 108 SRII(PIXEL_RATE_CNTL, OTG, 3) 109 #endif 110 111 #define CS_COMMON_MASK_SH_LIST_DCN2_0(mask_sh)\ 112 CS_SF(DP_DTO0_PHASE, DP_DTO0_PHASE, mask_sh),\ 113 CS_SF(DP_DTO0_MODULO, DP_DTO0_MODULO, mask_sh),\ 114 CS_SF(PHYPLLA_PIXCLK_RESYNC_CNTL, PHYPLLA_DCCG_DEEP_COLOR_CNTL, mask_sh),\ 115 CS_SF(OTG0_PIXEL_RATE_CNTL, DP_DTO0_ENABLE, mask_sh) 116 117 #if defined(CONFIG_DRM_AMD_DC_DCN) 118 119 #define CS_COMMON_REG_LIST_DCN1_0(index, pllid) \ 120 SRI(PIXCLK_RESYNC_CNTL, PHYPLL, pllid),\ 121 SRII(PHASE, DP_DTO, 0),\ 122 SRII(PHASE, DP_DTO, 1),\ 123 SRII(PHASE, DP_DTO, 2),\ 124 SRII(PHASE, DP_DTO, 3),\ 125 SRII(MODULO, DP_DTO, 0),\ 126 SRII(MODULO, DP_DTO, 1),\ 127 SRII(MODULO, DP_DTO, 2),\ 128 SRII(MODULO, DP_DTO, 3),\ 129 SRII(PIXEL_RATE_CNTL, OTG, 0), \ 130 SRII(PIXEL_RATE_CNTL, OTG, 1), \ 131 SRII(PIXEL_RATE_CNTL, OTG, 2), \ 132 SRII(PIXEL_RATE_CNTL, OTG, 3) 133 134 #define CS_COMMON_MASK_SH_LIST_DCN1_0(mask_sh)\ 135 CS_SF(DP_DTO0_PHASE, DP_DTO0_PHASE, mask_sh),\ 136 CS_SF(DP_DTO0_MODULO, DP_DTO0_MODULO, mask_sh),\ 137 CS_SF(PHYPLLA_PIXCLK_RESYNC_CNTL, PHYPLLA_DCCG_DEEP_COLOR_CNTL, mask_sh),\ 138 CS_SF(OTG0_PIXEL_RATE_CNTL, DP_DTO0_ENABLE, mask_sh) 139 140 #endif 141 142 #define CS_REG_FIELD_LIST(type) \ 143 type PLL_REF_DIV_SRC; \ 144 type DCCG_DEEP_COLOR_CNTL1; \ 145 type PHYPLLA_DCCG_DEEP_COLOR_CNTL; \ 146 type PHYPLLA_PIXCLK_DOUBLE_RATE_ENABLE; \ 147 type PLL_POST_DIV_PIXCLK; \ 148 type PLL_REF_DIV; \ 149 type DP_DTO0_PHASE; \ 150 type DP_DTO0_MODULO; \ 151 type DP_DTO0_ENABLE; 152 153 struct dce110_clk_src_shift { 154 CS_REG_FIELD_LIST(uint8_t) 155 }; 156 157 struct dce110_clk_src_mask{ 158 CS_REG_FIELD_LIST(uint32_t) 159 }; 160 161 struct dce110_clk_src_regs { 162 uint32_t RESYNC_CNTL; 163 uint32_t PIXCLK_RESYNC_CNTL; 164 uint32_t PLL_CNTL; 165 166 /* below are for DTO. 167 * todo: should probably use different struct to not waste space 168 */ 169 uint32_t PHASE[MAX_PIPES]; 170 uint32_t MODULO[MAX_PIPES]; 171 uint32_t PIXEL_RATE_CNTL[MAX_PIPES]; 172 }; 173 174 struct dce110_clk_src { 175 struct clock_source base; 176 const struct dce110_clk_src_regs *regs; 177 const struct dce110_clk_src_mask *cs_mask; 178 const struct dce110_clk_src_shift *cs_shift; 179 struct dc_bios *bios; 180 181 struct spread_spectrum_data *dp_ss_params; 182 uint32_t dp_ss_params_cnt; 183 struct spread_spectrum_data *hdmi_ss_params; 184 uint32_t hdmi_ss_params_cnt; 185 struct spread_spectrum_data *dvi_ss_params; 186 uint32_t dvi_ss_params_cnt; 187 struct spread_spectrum_data *lvds_ss_params; 188 uint32_t lvds_ss_params_cnt; 189 190 uint32_t ext_clk_khz; 191 uint32_t ref_freq_khz; 192 193 struct calc_pll_clock_source calc_pll; 194 struct calc_pll_clock_source calc_pll_hdmi; 195 }; 196 197 bool dce110_clk_src_construct( 198 struct dce110_clk_src *clk_src, 199 struct dc_context *ctx, 200 struct dc_bios *bios, 201 enum clock_source_id, 202 const struct dce110_clk_src_regs *regs, 203 const struct dce110_clk_src_shift *cs_shift, 204 const struct dce110_clk_src_mask *cs_mask); 205 206 bool dce112_clk_src_construct( 207 struct dce110_clk_src *clk_src, 208 struct dc_context *ctx, 209 struct dc_bios *bios, 210 enum clock_source_id id, 211 const struct dce110_clk_src_regs *regs, 212 const struct dce110_clk_src_shift *cs_shift, 213 const struct dce110_clk_src_mask *cs_mask); 214 215 bool dcn20_clk_src_construct( 216 struct dce110_clk_src *clk_src, 217 struct dc_context *ctx, 218 struct dc_bios *bios, 219 enum clock_source_id id, 220 const struct dce110_clk_src_regs *regs, 221 const struct dce110_clk_src_shift *cs_shift, 222 const struct dce110_clk_src_mask *cs_mask); 223 224 #if defined(CONFIG_DRM_AMD_DC_DCN3_0) 225 bool dcn3_clk_src_construct( 226 struct dce110_clk_src *clk_src, 227 struct dc_context *ctx, 228 struct dc_bios *bios, 229 enum clock_source_id id, 230 const struct dce110_clk_src_regs *regs, 231 const struct dce110_clk_src_shift *cs_shift, 232 const struct dce110_clk_src_mask *cs_mask); 233 #endif 234 235 /* this table is use to find *1.001 and /1.001 pixel rates from non-precise pixel rate */ 236 struct pixel_rate_range_table_entry { 237 unsigned int range_min_khz; 238 unsigned int range_max_khz; 239 unsigned int target_pixel_rate_khz; 240 unsigned short mult_factor; 241 unsigned short div_factor; 242 }; 243 244 #if defined(CONFIG_DRM_AMD_DC_DCN3_0) 245 extern const struct pixel_rate_range_table_entry video_optimized_pixel_rates[]; 246 const struct pixel_rate_range_table_entry *look_up_in_video_optimized_rate_tlb( 247 unsigned int pixel_rate_khz); 248 #endif 249 #endif 250
