1 // SPDX-License-Identifier: GPL-2.0
2 //
3 // cs35l41.c -- CS35l41 ALSA SoC audio driver
4 //
5 // Copyright 2017-2021 Cirrus Logic, Inc.
6 //
7 // Author: David Rhodes <david.rhodes@cirrus.com>
8
9 #include <linux/acpi.h>
10 #include <linux/delay.h>
11 #include <linux/err.h>
12 #include <linux/init.h>
13 #include <linux/kernel.h>
14 #include <linux/module.h>
15 #include <linux/moduleparam.h>
16 #include <linux/of_device.h>
17 #include <linux/pm_runtime.h>
18 #include <linux/property.h>
19 #include <sound/initval.h>
20 #include <sound/pcm.h>
21 #include <sound/pcm_params.h>
22 #include <sound/soc.h>
23 #include <sound/soc-dapm.h>
24 #include <sound/tlv.h>
25
26 #include "cs35l41.h"
27
28 static const char * const cs35l41_supplies[CS35L41_NUM_SUPPLIES] = {
29 "VA",
30 "VP",
31 };
32
33 struct cs35l41_pll_sysclk_config {
34 int freq;
35 int clk_cfg;
36 };
37
38 static const struct cs35l41_pll_sysclk_config cs35l41_pll_sysclk[] = {
39 { 32768, 0x00 },
40 { 8000, 0x01 },
41 { 11025, 0x02 },
42 { 12000, 0x03 },
43 { 16000, 0x04 },
44 { 22050, 0x05 },
45 { 24000, 0x06 },
46 { 32000, 0x07 },
47 { 44100, 0x08 },
48 { 48000, 0x09 },
49 { 88200, 0x0A },
50 { 96000, 0x0B },
51 { 128000, 0x0C },
52 { 176400, 0x0D },
53 { 192000, 0x0E },
54 { 256000, 0x0F },
55 { 352800, 0x10 },
56 { 384000, 0x11 },
57 { 512000, 0x12 },
58 { 705600, 0x13 },
59 { 750000, 0x14 },
60 { 768000, 0x15 },
61 { 1000000, 0x16 },
62 { 1024000, 0x17 },
63 { 1200000, 0x18 },
64 { 1411200, 0x19 },
65 { 1500000, 0x1A },
66 { 1536000, 0x1B },
67 { 2000000, 0x1C },
68 { 2048000, 0x1D },
69 { 2400000, 0x1E },
70 { 2822400, 0x1F },
71 { 3000000, 0x20 },
72 { 3072000, 0x21 },
73 { 3200000, 0x22 },
74 { 4000000, 0x23 },
75 { 4096000, 0x24 },
76 { 4800000, 0x25 },
77 { 5644800, 0x26 },
78 { 6000000, 0x27 },
79 { 6144000, 0x28 },
80 { 6250000, 0x29 },
81 { 6400000, 0x2A },
82 { 6500000, 0x2B },
83 { 6750000, 0x2C },
84 { 7526400, 0x2D },
85 { 8000000, 0x2E },
86 { 8192000, 0x2F },
87 { 9600000, 0x30 },
88 { 11289600, 0x31 },
89 { 12000000, 0x32 },
90 { 12288000, 0x33 },
91 { 12500000, 0x34 },
92 { 12800000, 0x35 },
93 { 13000000, 0x36 },
94 { 13500000, 0x37 },
95 { 19200000, 0x38 },
96 { 22579200, 0x39 },
97 { 24000000, 0x3A },
98 { 24576000, 0x3B },
99 { 25000000, 0x3C },
100 { 25600000, 0x3D },
101 { 26000000, 0x3E },
102 { 27000000, 0x3F },
103 };
104
105 struct cs35l41_fs_mon_config {
106 int freq;
107 unsigned int fs1;
108 unsigned int fs2;
109 };
110
111 static const struct cs35l41_fs_mon_config cs35l41_fs_mon[] = {
112 { 32768, 2254, 3754 },
113 { 8000, 9220, 15364 },
114 { 11025, 6148, 10244 },
115 { 12000, 6148, 10244 },
116 { 16000, 4612, 7684 },
117 { 22050, 3076, 5124 },
118 { 24000, 3076, 5124 },
119 { 32000, 2308, 3844 },
120 { 44100, 1540, 2564 },
121 { 48000, 1540, 2564 },
122 { 88200, 772, 1284 },
123 { 96000, 772, 1284 },
124 { 128000, 580, 964 },
125 { 176400, 388, 644 },
126 { 192000, 388, 644 },
127 { 256000, 292, 484 },
128 { 352800, 196, 324 },
129 { 384000, 196, 324 },
130 { 512000, 148, 244 },
131 { 705600, 100, 164 },
132 { 750000, 100, 164 },
133 { 768000, 100, 164 },
134 { 1000000, 76, 124 },
135 { 1024000, 76, 124 },
136 { 1200000, 64, 104 },
137 { 1411200, 52, 84 },
138 { 1500000, 52, 84 },
139 { 1536000, 52, 84 },
140 { 2000000, 40, 64 },
141 { 2048000, 40, 64 },
142 { 2400000, 34, 54 },
143 { 2822400, 28, 44 },
144 { 3000000, 28, 44 },
145 { 3072000, 28, 44 },
146 { 3200000, 27, 42 },
147 { 4000000, 22, 34 },
148 { 4096000, 22, 34 },
149 { 4800000, 19, 29 },
150 { 5644800, 16, 24 },
151 { 6000000, 16, 24 },
152 { 6144000, 16, 24 },
153 { 12288000, 0, 0 },
154 };
155
cs35l41_get_fs_mon_config_index(int freq)156 static int cs35l41_get_fs_mon_config_index(int freq)
157 {
158 int i;
159
160 for (i = 0; i < ARRAY_SIZE(cs35l41_fs_mon); i++) {
161 if (cs35l41_fs_mon[i].freq == freq)
162 return i;
163 }
164
165 return -EINVAL;
166 }
167
168 static const DECLARE_TLV_DB_RANGE(dig_vol_tlv,
169 0, 0, TLV_DB_SCALE_ITEM(TLV_DB_GAIN_MUTE, 0, 1),
170 1, 913, TLV_DB_MINMAX_ITEM(-10200, 1200));
171 static DECLARE_TLV_DB_SCALE(amp_gain_tlv, 50, 100, 0);
172
173 static const struct snd_kcontrol_new dre_ctrl =
174 SOC_DAPM_SINGLE("Switch", CS35L41_PWR_CTRL3, 20, 1, 0);
175
176 static const char * const cs35l41_pcm_sftramp_text[] = {
177 "Off", ".5ms", "1ms", "2ms", "4ms", "8ms", "15ms", "30ms"
178 };
179
180 static SOC_ENUM_SINGLE_DECL(pcm_sft_ramp,
181 CS35L41_AMP_DIG_VOL_CTRL, 0,
182 cs35l41_pcm_sftramp_text);
183
cs35l41_dsp_preload_ev(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)184 static int cs35l41_dsp_preload_ev(struct snd_soc_dapm_widget *w,
185 struct snd_kcontrol *kcontrol, int event)
186 {
187 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
188 struct cs35l41_private *cs35l41 = snd_soc_component_get_drvdata(component);
189 int ret;
190
191 switch (event) {
192 case SND_SOC_DAPM_PRE_PMU:
193 if (cs35l41->dsp.cs_dsp.booted)
194 return 0;
195
196 return wm_adsp_early_event(w, kcontrol, event);
197 case SND_SOC_DAPM_PRE_PMD:
198 if (cs35l41->dsp.preloaded)
199 return 0;
200
201 if (cs35l41->dsp.cs_dsp.running) {
202 ret = wm_adsp_event(w, kcontrol, event);
203 if (ret)
204 return ret;
205 }
206
207 return wm_adsp_early_event(w, kcontrol, event);
208 default:
209 return 0;
210 }
211 }
212
cs35l41_dsp_audio_ev(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)213 static int cs35l41_dsp_audio_ev(struct snd_soc_dapm_widget *w,
214 struct snd_kcontrol *kcontrol, int event)
215 {
216 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
217 struct cs35l41_private *cs35l41 = snd_soc_component_get_drvdata(component);
218 unsigned int fw_status;
219 int ret;
220
221 switch (event) {
222 case SND_SOC_DAPM_POST_PMU:
223 if (!cs35l41->dsp.cs_dsp.running)
224 return wm_adsp_event(w, kcontrol, event);
225
226 ret = regmap_read(cs35l41->regmap, CS35L41_DSP_MBOX_2, &fw_status);
227 if (ret < 0) {
228 dev_err(cs35l41->dev,
229 "Failed to read firmware status: %d\n", ret);
230 return ret;
231 }
232
233 switch (fw_status) {
234 case CSPL_MBOX_STS_RUNNING:
235 case CSPL_MBOX_STS_PAUSED:
236 break;
237 default:
238 dev_err(cs35l41->dev, "Firmware status is invalid: %u\n",
239 fw_status);
240 return -EINVAL;
241 }
242
243 return cs35l41_set_cspl_mbox_cmd(cs35l41->dev, cs35l41->regmap,
244 CSPL_MBOX_CMD_RESUME);
245 case SND_SOC_DAPM_PRE_PMD:
246 return cs35l41_set_cspl_mbox_cmd(cs35l41->dev, cs35l41->regmap,
247 CSPL_MBOX_CMD_PAUSE);
248 default:
249 return 0;
250 }
251 }
252
253 static const char * const cs35l41_pcm_source_texts[] = {"ASP", "DSP"};
254 static const unsigned int cs35l41_pcm_source_values[] = {0x08, 0x32};
255 static SOC_VALUE_ENUM_SINGLE_DECL(cs35l41_pcm_source_enum,
256 CS35L41_DAC_PCM1_SRC,
257 0, CS35L41_ASP_SOURCE_MASK,
258 cs35l41_pcm_source_texts,
259 cs35l41_pcm_source_values);
260
261 static const struct snd_kcontrol_new pcm_source_mux =
262 SOC_DAPM_ENUM("PCM Source", cs35l41_pcm_source_enum);
263
264 static const char * const cs35l41_tx_input_texts[] = {
265 "Zero", "ASPRX1", "ASPRX2", "VMON", "IMON",
266 "VPMON", "VBSTMON", "DSPTX1", "DSPTX2"
267 };
268
269 static const unsigned int cs35l41_tx_input_values[] = {
270 0x00, CS35L41_INPUT_SRC_ASPRX1, CS35L41_INPUT_SRC_ASPRX2,
271 CS35L41_INPUT_SRC_VMON, CS35L41_INPUT_SRC_IMON, CS35L41_INPUT_SRC_VPMON,
272 CS35L41_INPUT_SRC_VBSTMON, CS35L41_INPUT_DSP_TX1, CS35L41_INPUT_DSP_TX2
273 };
274
275 static SOC_VALUE_ENUM_SINGLE_DECL(cs35l41_asptx1_enum,
276 CS35L41_ASP_TX1_SRC,
277 0, CS35L41_ASP_SOURCE_MASK,
278 cs35l41_tx_input_texts,
279 cs35l41_tx_input_values);
280
281 static const struct snd_kcontrol_new asp_tx1_mux =
282 SOC_DAPM_ENUM("ASPTX1 SRC", cs35l41_asptx1_enum);
283
284 static SOC_VALUE_ENUM_SINGLE_DECL(cs35l41_asptx2_enum,
285 CS35L41_ASP_TX2_SRC,
286 0, CS35L41_ASP_SOURCE_MASK,
287 cs35l41_tx_input_texts,
288 cs35l41_tx_input_values);
289
290 static const struct snd_kcontrol_new asp_tx2_mux =
291 SOC_DAPM_ENUM("ASPTX2 SRC", cs35l41_asptx2_enum);
292
293 static SOC_VALUE_ENUM_SINGLE_DECL(cs35l41_asptx3_enum,
294 CS35L41_ASP_TX3_SRC,
295 0, CS35L41_ASP_SOURCE_MASK,
296 cs35l41_tx_input_texts,
297 cs35l41_tx_input_values);
298
299 static const struct snd_kcontrol_new asp_tx3_mux =
300 SOC_DAPM_ENUM("ASPTX3 SRC", cs35l41_asptx3_enum);
301
302 static SOC_VALUE_ENUM_SINGLE_DECL(cs35l41_asptx4_enum,
303 CS35L41_ASP_TX4_SRC,
304 0, CS35L41_ASP_SOURCE_MASK,
305 cs35l41_tx_input_texts,
306 cs35l41_tx_input_values);
307
308 static const struct snd_kcontrol_new asp_tx4_mux =
309 SOC_DAPM_ENUM("ASPTX4 SRC", cs35l41_asptx4_enum);
310
311 static SOC_VALUE_ENUM_SINGLE_DECL(cs35l41_dsprx1_enum,
312 CS35L41_DSP1_RX1_SRC,
313 0, CS35L41_ASP_SOURCE_MASK,
314 cs35l41_tx_input_texts,
315 cs35l41_tx_input_values);
316
317 static const struct snd_kcontrol_new dsp_rx1_mux =
318 SOC_DAPM_ENUM("DSPRX1 SRC", cs35l41_dsprx1_enum);
319
320 static SOC_VALUE_ENUM_SINGLE_DECL(cs35l41_dsprx2_enum,
321 CS35L41_DSP1_RX2_SRC,
322 0, CS35L41_ASP_SOURCE_MASK,
323 cs35l41_tx_input_texts,
324 cs35l41_tx_input_values);
325
326 static const struct snd_kcontrol_new dsp_rx2_mux =
327 SOC_DAPM_ENUM("DSPRX2 SRC", cs35l41_dsprx2_enum);
328
329 static const struct snd_kcontrol_new cs35l41_aud_controls[] = {
330 SOC_SINGLE_SX_TLV("Digital PCM Volume", CS35L41_AMP_DIG_VOL_CTRL,
331 3, 0x4CF, 0x391, dig_vol_tlv),
332 SOC_SINGLE_TLV("Analog PCM Volume", CS35L41_AMP_GAIN_CTRL, 5, 0x14, 0,
333 amp_gain_tlv),
334 SOC_ENUM("PCM Soft Ramp", pcm_sft_ramp),
335 SOC_SINGLE("HW Noise Gate Enable", CS35L41_NG_CFG, 8, 63, 0),
336 SOC_SINGLE("HW Noise Gate Delay", CS35L41_NG_CFG, 4, 7, 0),
337 SOC_SINGLE("HW Noise Gate Threshold", CS35L41_NG_CFG, 0, 7, 0),
338 SOC_SINGLE("Aux Noise Gate CH1 Switch",
339 CS35L41_MIXER_NGATE_CH1_CFG, 16, 1, 0),
340 SOC_SINGLE("Aux Noise Gate CH1 Entry Delay",
341 CS35L41_MIXER_NGATE_CH1_CFG, 8, 15, 0),
342 SOC_SINGLE("Aux Noise Gate CH1 Threshold",
343 CS35L41_MIXER_NGATE_CH1_CFG, 0, 7, 0),
344 SOC_SINGLE("Aux Noise Gate CH2 Entry Delay",
345 CS35L41_MIXER_NGATE_CH2_CFG, 8, 15, 0),
346 SOC_SINGLE("Aux Noise Gate CH2 Switch",
347 CS35L41_MIXER_NGATE_CH2_CFG, 16, 1, 0),
348 SOC_SINGLE("Aux Noise Gate CH2 Threshold",
349 CS35L41_MIXER_NGATE_CH2_CFG, 0, 7, 0),
350 SOC_SINGLE("SCLK Force Switch", CS35L41_SP_FORMAT, CS35L41_SCLK_FRC_SHIFT, 1, 0),
351 SOC_SINGLE("LRCLK Force Switch", CS35L41_SP_FORMAT, CS35L41_LRCLK_FRC_SHIFT, 1, 0),
352 SOC_SINGLE("Invert Class D Switch", CS35L41_AMP_DIG_VOL_CTRL,
353 CS35L41_AMP_INV_PCM_SHIFT, 1, 0),
354 SOC_SINGLE("Amp Gain ZC Switch", CS35L41_AMP_GAIN_CTRL,
355 CS35L41_AMP_GAIN_ZC_SHIFT, 1, 0),
356 WM_ADSP2_PRELOAD_SWITCH("DSP1", 1),
357 WM_ADSP_FW_CONTROL("DSP1", 0),
358 };
359
cs35l41_boost_enable(struct cs35l41_private * cs35l41,unsigned int enable)360 static void cs35l41_boost_enable(struct cs35l41_private *cs35l41, unsigned int enable)
361 {
362 switch (cs35l41->hw_cfg.bst_type) {
363 case CS35L41_INT_BOOST:
364 case CS35L41_SHD_BOOST_ACTV:
365 enable = enable ? CS35L41_BST_EN_DEFAULT : CS35L41_BST_DIS_FET_OFF;
366 regmap_update_bits(cs35l41->regmap, CS35L41_PWR_CTRL2, CS35L41_BST_EN_MASK,
367 enable << CS35L41_BST_EN_SHIFT);
368 break;
369 default:
370 break;
371 }
372 }
373
374
cs35l41_error_release(struct cs35l41_private * cs35l41,unsigned int irq_err_bit,unsigned int rel_err_bit)375 static void cs35l41_error_release(struct cs35l41_private *cs35l41, unsigned int irq_err_bit,
376 unsigned int rel_err_bit)
377 {
378 regmap_write(cs35l41->regmap, CS35L41_IRQ1_STATUS1, irq_err_bit);
379 regmap_write(cs35l41->regmap, CS35L41_PROTECT_REL_ERR_IGN, 0);
380 regmap_update_bits(cs35l41->regmap, CS35L41_PROTECT_REL_ERR_IGN, rel_err_bit, rel_err_bit);
381 regmap_update_bits(cs35l41->regmap, CS35L41_PROTECT_REL_ERR_IGN, rel_err_bit, 0);
382 }
383
cs35l41_irq(int irq,void * data)384 static irqreturn_t cs35l41_irq(int irq, void *data)
385 {
386 struct cs35l41_private *cs35l41 = data;
387 unsigned int status[4] = { 0, 0, 0, 0 };
388 unsigned int masks[4] = { 0, 0, 0, 0 };
389 int ret = IRQ_NONE;
390 unsigned int i;
391
392 pm_runtime_get_sync(cs35l41->dev);
393
394 for (i = 0; i < ARRAY_SIZE(status); i++) {
395 regmap_read(cs35l41->regmap,
396 CS35L41_IRQ1_STATUS1 + (i * CS35L41_REGSTRIDE),
397 &status[i]);
398 regmap_read(cs35l41->regmap,
399 CS35L41_IRQ1_MASK1 + (i * CS35L41_REGSTRIDE),
400 &masks[i]);
401 }
402
403 /* Check to see if unmasked bits are active */
404 if (!(status[0] & ~masks[0]) && !(status[1] & ~masks[1]) &&
405 !(status[2] & ~masks[2]) && !(status[3] & ~masks[3]))
406 goto done;
407
408 if (status[3] & CS35L41_OTP_BOOT_DONE) {
409 regmap_update_bits(cs35l41->regmap, CS35L41_IRQ1_MASK4,
410 CS35L41_OTP_BOOT_DONE, CS35L41_OTP_BOOT_DONE);
411 }
412
413 /*
414 * The following interrupts require a
415 * protection release cycle to get the
416 * speaker out of Safe-Mode.
417 */
418 if (status[0] & CS35L41_AMP_SHORT_ERR) {
419 dev_crit_ratelimited(cs35l41->dev, "Amp short error\n");
420 cs35l41_error_release(cs35l41, CS35L41_AMP_SHORT_ERR, CS35L41_AMP_SHORT_ERR_RLS);
421 ret = IRQ_HANDLED;
422 }
423
424 if (status[0] & CS35L41_TEMP_WARN) {
425 dev_crit_ratelimited(cs35l41->dev, "Over temperature warning\n");
426 cs35l41_error_release(cs35l41, CS35L41_TEMP_WARN, CS35L41_TEMP_WARN_ERR_RLS);
427 ret = IRQ_HANDLED;
428 }
429
430 if (status[0] & CS35L41_TEMP_ERR) {
431 dev_crit_ratelimited(cs35l41->dev, "Over temperature error\n");
432 cs35l41_error_release(cs35l41, CS35L41_TEMP_ERR, CS35L41_TEMP_ERR_RLS);
433 ret = IRQ_HANDLED;
434 }
435
436 if (status[0] & CS35L41_BST_OVP_ERR) {
437 dev_crit_ratelimited(cs35l41->dev, "VBST Over Voltage error\n");
438 cs35l41_boost_enable(cs35l41, 0);
439 cs35l41_error_release(cs35l41, CS35L41_BST_OVP_ERR, CS35L41_BST_OVP_ERR_RLS);
440 cs35l41_boost_enable(cs35l41, 1);
441 ret = IRQ_HANDLED;
442 }
443
444 if (status[0] & CS35L41_BST_DCM_UVP_ERR) {
445 dev_crit_ratelimited(cs35l41->dev, "DCM VBST Under Voltage Error\n");
446 cs35l41_boost_enable(cs35l41, 0);
447 cs35l41_error_release(cs35l41, CS35L41_BST_DCM_UVP_ERR, CS35L41_BST_UVP_ERR_RLS);
448 cs35l41_boost_enable(cs35l41, 1);
449 ret = IRQ_HANDLED;
450 }
451
452 if (status[0] & CS35L41_BST_SHORT_ERR) {
453 dev_crit_ratelimited(cs35l41->dev, "LBST error: powering off!\n");
454 cs35l41_boost_enable(cs35l41, 0);
455 cs35l41_error_release(cs35l41, CS35L41_BST_SHORT_ERR, CS35L41_BST_SHORT_ERR_RLS);
456 cs35l41_boost_enable(cs35l41, 1);
457 ret = IRQ_HANDLED;
458 }
459
460 if (status[2] & CS35L41_PLL_LOCK) {
461 regmap_write(cs35l41->regmap, CS35L41_IRQ1_STATUS3, CS35L41_PLL_LOCK);
462 complete(&cs35l41->pll_lock);
463 ret = IRQ_HANDLED;
464 }
465
466 done:
467 pm_runtime_mark_last_busy(cs35l41->dev);
468 pm_runtime_put_autosuspend(cs35l41->dev);
469
470 return ret;
471 }
472
473 static const struct reg_sequence cs35l41_pup_patch[] = {
474 { CS35L41_TEST_KEY_CTL, 0x00000055 },
475 { CS35L41_TEST_KEY_CTL, 0x000000AA },
476 { 0x00002084, 0x002F1AA0 },
477 { CS35L41_TEST_KEY_CTL, 0x000000CC },
478 { CS35L41_TEST_KEY_CTL, 0x00000033 },
479 };
480
481 static const struct reg_sequence cs35l41_pdn_patch[] = {
482 { CS35L41_TEST_KEY_CTL, 0x00000055 },
483 { CS35L41_TEST_KEY_CTL, 0x000000AA },
484 { 0x00002084, 0x002F1AA3 },
485 { CS35L41_TEST_KEY_CTL, 0x000000CC },
486 { CS35L41_TEST_KEY_CTL, 0x00000033 },
487 };
488
cs35l41_main_amp_event(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)489 static int cs35l41_main_amp_event(struct snd_soc_dapm_widget *w,
490 struct snd_kcontrol *kcontrol, int event)
491 {
492 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
493 struct cs35l41_private *cs35l41 = snd_soc_component_get_drvdata(component);
494 int ret = 0;
495
496 switch (event) {
497 case SND_SOC_DAPM_PRE_PMU:
498 regmap_multi_reg_write_bypassed(cs35l41->regmap,
499 cs35l41_pup_patch,
500 ARRAY_SIZE(cs35l41_pup_patch));
501
502 ret = cs35l41_global_enable(cs35l41->dev, cs35l41->regmap, cs35l41->hw_cfg.bst_type,
503 1, &cs35l41->pll_lock, cs35l41->dsp.cs_dsp.running);
504 break;
505 case SND_SOC_DAPM_POST_PMD:
506 ret = cs35l41_global_enable(cs35l41->dev, cs35l41->regmap, cs35l41->hw_cfg.bst_type,
507 0, &cs35l41->pll_lock, cs35l41->dsp.cs_dsp.running);
508
509 regmap_multi_reg_write_bypassed(cs35l41->regmap,
510 cs35l41_pdn_patch,
511 ARRAY_SIZE(cs35l41_pdn_patch));
512 break;
513 default:
514 dev_err(cs35l41->dev, "Invalid event = 0x%x\n", event);
515 ret = -EINVAL;
516 }
517
518 return ret;
519 }
520
521 static const struct snd_soc_dapm_widget cs35l41_dapm_widgets[] = {
522 SND_SOC_DAPM_SPK("DSP1 Preload", NULL),
523 SND_SOC_DAPM_SUPPLY_S("DSP1 Preloader", 100, SND_SOC_NOPM, 0, 0,
524 cs35l41_dsp_preload_ev,
525 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_PRE_PMD),
526 SND_SOC_DAPM_OUT_DRV_E("DSP1", SND_SOC_NOPM, 0, 0, NULL, 0,
527 cs35l41_dsp_audio_ev,
528 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
529
530 SND_SOC_DAPM_OUTPUT("SPK"),
531
532 SND_SOC_DAPM_AIF_IN("ASPRX1", NULL, 0, CS35L41_SP_ENABLES, 16, 0),
533 SND_SOC_DAPM_AIF_IN("ASPRX2", NULL, 0, CS35L41_SP_ENABLES, 17, 0),
534 SND_SOC_DAPM_AIF_OUT("ASPTX1", NULL, 0, CS35L41_SP_ENABLES, 0, 0),
535 SND_SOC_DAPM_AIF_OUT("ASPTX2", NULL, 0, CS35L41_SP_ENABLES, 1, 0),
536 SND_SOC_DAPM_AIF_OUT("ASPTX3", NULL, 0, CS35L41_SP_ENABLES, 2, 0),
537 SND_SOC_DAPM_AIF_OUT("ASPTX4", NULL, 0, CS35L41_SP_ENABLES, 3, 0),
538
539 SND_SOC_DAPM_SIGGEN("VSENSE"),
540 SND_SOC_DAPM_SIGGEN("ISENSE"),
541 SND_SOC_DAPM_SIGGEN("VP"),
542 SND_SOC_DAPM_SIGGEN("VBST"),
543 SND_SOC_DAPM_SIGGEN("TEMP"),
544
545 SND_SOC_DAPM_SUPPLY("VMON", CS35L41_PWR_CTRL2, 12, 0, NULL, 0),
546 SND_SOC_DAPM_SUPPLY("IMON", CS35L41_PWR_CTRL2, 13, 0, NULL, 0),
547 SND_SOC_DAPM_SUPPLY("VPMON", CS35L41_PWR_CTRL2, 8, 0, NULL, 0),
548 SND_SOC_DAPM_SUPPLY("VBSTMON", CS35L41_PWR_CTRL2, 9, 0, NULL, 0),
549 SND_SOC_DAPM_SUPPLY("TEMPMON", CS35L41_PWR_CTRL2, 10, 0, NULL, 0),
550
551 SND_SOC_DAPM_ADC("VMON ADC", NULL, SND_SOC_NOPM, 0, 0),
552 SND_SOC_DAPM_ADC("IMON ADC", NULL, SND_SOC_NOPM, 0, 0),
553 SND_SOC_DAPM_ADC("VPMON ADC", NULL, SND_SOC_NOPM, 0, 0),
554 SND_SOC_DAPM_ADC("VBSTMON ADC", NULL, SND_SOC_NOPM, 0, 0),
555 SND_SOC_DAPM_ADC("TEMPMON ADC", NULL, SND_SOC_NOPM, 0, 0),
556
557 SND_SOC_DAPM_ADC("CLASS H", NULL, CS35L41_PWR_CTRL3, 4, 0),
558
559 SND_SOC_DAPM_OUT_DRV_E("Main AMP", CS35L41_PWR_CTRL2, 0, 0, NULL, 0,
560 cs35l41_main_amp_event,
561 SND_SOC_DAPM_POST_PMD | SND_SOC_DAPM_PRE_PMU),
562
563 SND_SOC_DAPM_MUX("ASP TX1 Source", SND_SOC_NOPM, 0, 0, &asp_tx1_mux),
564 SND_SOC_DAPM_MUX("ASP TX2 Source", SND_SOC_NOPM, 0, 0, &asp_tx2_mux),
565 SND_SOC_DAPM_MUX("ASP TX3 Source", SND_SOC_NOPM, 0, 0, &asp_tx3_mux),
566 SND_SOC_DAPM_MUX("ASP TX4 Source", SND_SOC_NOPM, 0, 0, &asp_tx4_mux),
567 SND_SOC_DAPM_MUX("DSP RX1 Source", SND_SOC_NOPM, 0, 0, &dsp_rx1_mux),
568 SND_SOC_DAPM_MUX("DSP RX2 Source", SND_SOC_NOPM, 0, 0, &dsp_rx2_mux),
569 SND_SOC_DAPM_MUX("PCM Source", SND_SOC_NOPM, 0, 0, &pcm_source_mux),
570 SND_SOC_DAPM_SWITCH("DRE", SND_SOC_NOPM, 0, 0, &dre_ctrl),
571 };
572
573 static const struct snd_soc_dapm_route cs35l41_audio_map[] = {
574 {"DSP RX1 Source", "ASPRX1", "ASPRX1"},
575 {"DSP RX1 Source", "ASPRX2", "ASPRX2"},
576 {"DSP RX2 Source", "ASPRX1", "ASPRX1"},
577 {"DSP RX2 Source", "ASPRX2", "ASPRX2"},
578
579 {"DSP1", NULL, "DSP RX1 Source"},
580 {"DSP1", NULL, "DSP RX2 Source"},
581
582 {"ASP TX1 Source", "VMON", "VMON ADC"},
583 {"ASP TX1 Source", "IMON", "IMON ADC"},
584 {"ASP TX1 Source", "VPMON", "VPMON ADC"},
585 {"ASP TX1 Source", "VBSTMON", "VBSTMON ADC"},
586 {"ASP TX1 Source", "DSPTX1", "DSP1"},
587 {"ASP TX1 Source", "DSPTX2", "DSP1"},
588 {"ASP TX1 Source", "ASPRX1", "ASPRX1" },
589 {"ASP TX1 Source", "ASPRX2", "ASPRX2" },
590 {"ASP TX2 Source", "VMON", "VMON ADC"},
591 {"ASP TX2 Source", "IMON", "IMON ADC"},
592 {"ASP TX2 Source", "VPMON", "VPMON ADC"},
593 {"ASP TX2 Source", "VBSTMON", "VBSTMON ADC"},
594 {"ASP TX2 Source", "DSPTX1", "DSP1"},
595 {"ASP TX2 Source", "DSPTX2", "DSP1"},
596 {"ASP TX2 Source", "ASPRX1", "ASPRX1" },
597 {"ASP TX2 Source", "ASPRX2", "ASPRX2" },
598 {"ASP TX3 Source", "VMON", "VMON ADC"},
599 {"ASP TX3 Source", "IMON", "IMON ADC"},
600 {"ASP TX3 Source", "VPMON", "VPMON ADC"},
601 {"ASP TX3 Source", "VBSTMON", "VBSTMON ADC"},
602 {"ASP TX3 Source", "DSPTX1", "DSP1"},
603 {"ASP TX3 Source", "DSPTX2", "DSP1"},
604 {"ASP TX3 Source", "ASPRX1", "ASPRX1" },
605 {"ASP TX3 Source", "ASPRX2", "ASPRX2" },
606 {"ASP TX4 Source", "VMON", "VMON ADC"},
607 {"ASP TX4 Source", "IMON", "IMON ADC"},
608 {"ASP TX4 Source", "VPMON", "VPMON ADC"},
609 {"ASP TX4 Source", "VBSTMON", "VBSTMON ADC"},
610 {"ASP TX4 Source", "DSPTX1", "DSP1"},
611 {"ASP TX4 Source", "DSPTX2", "DSP1"},
612 {"ASP TX4 Source", "ASPRX1", "ASPRX1" },
613 {"ASP TX4 Source", "ASPRX2", "ASPRX2" },
614 {"ASPTX1", NULL, "ASP TX1 Source"},
615 {"ASPTX2", NULL, "ASP TX2 Source"},
616 {"ASPTX3", NULL, "ASP TX3 Source"},
617 {"ASPTX4", NULL, "ASP TX4 Source"},
618 {"AMP Capture", NULL, "ASPTX1"},
619 {"AMP Capture", NULL, "ASPTX2"},
620 {"AMP Capture", NULL, "ASPTX3"},
621 {"AMP Capture", NULL, "ASPTX4"},
622
623 {"DSP1", NULL, "VMON"},
624 {"DSP1", NULL, "IMON"},
625 {"DSP1", NULL, "VPMON"},
626 {"DSP1", NULL, "VBSTMON"},
627 {"DSP1", NULL, "TEMPMON"},
628
629 {"VMON ADC", NULL, "VMON"},
630 {"IMON ADC", NULL, "IMON"},
631 {"VPMON ADC", NULL, "VPMON"},
632 {"VBSTMON ADC", NULL, "VBSTMON"},
633 {"TEMPMON ADC", NULL, "TEMPMON"},
634
635 {"VMON ADC", NULL, "VSENSE"},
636 {"IMON ADC", NULL, "ISENSE"},
637 {"VPMON ADC", NULL, "VP"},
638 {"VBSTMON ADC", NULL, "VBST"},
639 {"TEMPMON ADC", NULL, "TEMP"},
640
641 {"DSP1 Preload", NULL, "DSP1 Preloader"},
642 {"DSP1", NULL, "DSP1 Preloader"},
643
644 {"ASPRX1", NULL, "AMP Playback"},
645 {"ASPRX2", NULL, "AMP Playback"},
646 {"DRE", "Switch", "CLASS H"},
647 {"Main AMP", NULL, "CLASS H"},
648 {"Main AMP", NULL, "DRE"},
649 {"SPK", NULL, "Main AMP"},
650
651 {"PCM Source", "ASP", "ASPRX1"},
652 {"PCM Source", "DSP", "DSP1"},
653 {"CLASS H", NULL, "PCM Source"},
654 };
655
cs35l41_set_channel_map(struct snd_soc_dai * dai,unsigned int tx_n,unsigned int * tx_slot,unsigned int rx_n,unsigned int * rx_slot)656 static int cs35l41_set_channel_map(struct snd_soc_dai *dai, unsigned int tx_n,
657 unsigned int *tx_slot, unsigned int rx_n, unsigned int *rx_slot)
658 {
659 struct cs35l41_private *cs35l41 = snd_soc_component_get_drvdata(dai->component);
660
661 return cs35l41_set_channels(cs35l41->dev, cs35l41->regmap, tx_n, tx_slot, rx_n, rx_slot);
662 }
663
cs35l41_set_dai_fmt(struct snd_soc_dai * dai,unsigned int fmt)664 static int cs35l41_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
665 {
666 struct cs35l41_private *cs35l41 = snd_soc_component_get_drvdata(dai->component);
667 unsigned int daifmt = 0;
668
669 switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
670 case SND_SOC_DAIFMT_CBP_CFP:
671 daifmt |= CS35L41_SCLK_MSTR_MASK | CS35L41_LRCLK_MSTR_MASK;
672 break;
673 case SND_SOC_DAIFMT_CBC_CFC:
674 break;
675 default:
676 dev_warn(cs35l41->dev, "Mixed provider/consumer mode unsupported\n");
677 return -EINVAL;
678 }
679
680 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
681 case SND_SOC_DAIFMT_DSP_A:
682 break;
683 case SND_SOC_DAIFMT_I2S:
684 daifmt |= 2 << CS35L41_ASP_FMT_SHIFT;
685 break;
686 default:
687 dev_warn(cs35l41->dev, "Invalid or unsupported DAI format\n");
688 return -EINVAL;
689 }
690
691 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
692 case SND_SOC_DAIFMT_NB_IF:
693 daifmt |= CS35L41_LRCLK_INV_MASK;
694 break;
695 case SND_SOC_DAIFMT_IB_NF:
696 daifmt |= CS35L41_SCLK_INV_MASK;
697 break;
698 case SND_SOC_DAIFMT_IB_IF:
699 daifmt |= CS35L41_LRCLK_INV_MASK | CS35L41_SCLK_INV_MASK;
700 break;
701 case SND_SOC_DAIFMT_NB_NF:
702 break;
703 default:
704 dev_warn(cs35l41->dev, "Invalid DAI clock INV\n");
705 return -EINVAL;
706 }
707
708 return regmap_update_bits(cs35l41->regmap, CS35L41_SP_FORMAT,
709 CS35L41_SCLK_MSTR_MASK | CS35L41_LRCLK_MSTR_MASK |
710 CS35L41_ASP_FMT_MASK | CS35L41_LRCLK_INV_MASK |
711 CS35L41_SCLK_INV_MASK, daifmt);
712 }
713
714 struct cs35l41_global_fs_config {
715 int rate;
716 int fs_cfg;
717 };
718
719 static const struct cs35l41_global_fs_config cs35l41_fs_rates[] = {
720 { 12000, 0x01 },
721 { 24000, 0x02 },
722 { 48000, 0x03 },
723 { 96000, 0x04 },
724 { 192000, 0x05 },
725 { 11025, 0x09 },
726 { 22050, 0x0A },
727 { 44100, 0x0B },
728 { 88200, 0x0C },
729 { 176400, 0x0D },
730 { 8000, 0x11 },
731 { 16000, 0x12 },
732 { 32000, 0x13 },
733 };
734
cs35l41_pcm_hw_params(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * params,struct snd_soc_dai * dai)735 static int cs35l41_pcm_hw_params(struct snd_pcm_substream *substream,
736 struct snd_pcm_hw_params *params,
737 struct snd_soc_dai *dai)
738 {
739 struct cs35l41_private *cs35l41 = snd_soc_component_get_drvdata(dai->component);
740 unsigned int rate = params_rate(params);
741 u8 asp_wl;
742 int i;
743
744 for (i = 0; i < ARRAY_SIZE(cs35l41_fs_rates); i++) {
745 if (rate == cs35l41_fs_rates[i].rate)
746 break;
747 }
748
749 if (i >= ARRAY_SIZE(cs35l41_fs_rates)) {
750 dev_err(cs35l41->dev, "Unsupported rate: %u\n", rate);
751 return -EINVAL;
752 }
753
754 asp_wl = params_width(params);
755
756 if (i < ARRAY_SIZE(cs35l41_fs_rates))
757 regmap_update_bits(cs35l41->regmap, CS35L41_GLOBAL_CLK_CTRL,
758 CS35L41_GLOBAL_FS_MASK,
759 cs35l41_fs_rates[i].fs_cfg << CS35L41_GLOBAL_FS_SHIFT);
760
761 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
762 regmap_update_bits(cs35l41->regmap, CS35L41_SP_FORMAT,
763 CS35L41_ASP_WIDTH_RX_MASK,
764 asp_wl << CS35L41_ASP_WIDTH_RX_SHIFT);
765 regmap_update_bits(cs35l41->regmap, CS35L41_SP_RX_WL,
766 CS35L41_ASP_RX_WL_MASK,
767 asp_wl << CS35L41_ASP_RX_WL_SHIFT);
768 } else {
769 regmap_update_bits(cs35l41->regmap, CS35L41_SP_FORMAT,
770 CS35L41_ASP_WIDTH_TX_MASK,
771 asp_wl << CS35L41_ASP_WIDTH_TX_SHIFT);
772 regmap_update_bits(cs35l41->regmap, CS35L41_SP_TX_WL,
773 CS35L41_ASP_TX_WL_MASK,
774 asp_wl << CS35L41_ASP_TX_WL_SHIFT);
775 }
776
777 return 0;
778 }
779
cs35l41_get_clk_config(int freq)780 static int cs35l41_get_clk_config(int freq)
781 {
782 int i;
783
784 for (i = 0; i < ARRAY_SIZE(cs35l41_pll_sysclk); i++) {
785 if (cs35l41_pll_sysclk[i].freq == freq)
786 return cs35l41_pll_sysclk[i].clk_cfg;
787 }
788
789 return -EINVAL;
790 }
791
792 static const unsigned int cs35l41_src_rates[] = {
793 8000, 12000, 11025, 16000, 22050, 24000, 32000,
794 44100, 48000, 88200, 96000, 176400, 192000
795 };
796
797 static const struct snd_pcm_hw_constraint_list cs35l41_constraints = {
798 .count = ARRAY_SIZE(cs35l41_src_rates),
799 .list = cs35l41_src_rates,
800 };
801
cs35l41_pcm_startup(struct snd_pcm_substream * substream,struct snd_soc_dai * dai)802 static int cs35l41_pcm_startup(struct snd_pcm_substream *substream,
803 struct snd_soc_dai *dai)
804 {
805 struct cs35l41_private *cs35l41 = snd_soc_component_get_drvdata(dai->component);
806
807 reinit_completion(&cs35l41->pll_lock);
808
809 if (substream->runtime)
810 return snd_pcm_hw_constraint_list(substream->runtime, 0,
811 SNDRV_PCM_HW_PARAM_RATE,
812 &cs35l41_constraints);
813 return 0;
814 }
815
cs35l41_component_set_sysclk(struct snd_soc_component * component,int clk_id,int source,unsigned int freq,int dir)816 static int cs35l41_component_set_sysclk(struct snd_soc_component *component,
817 int clk_id, int source,
818 unsigned int freq, int dir)
819 {
820 struct cs35l41_private *cs35l41 = snd_soc_component_get_drvdata(component);
821 int extclk_cfg, clksrc;
822
823 switch (clk_id) {
824 case CS35L41_CLKID_SCLK:
825 clksrc = CS35L41_PLLSRC_SCLK;
826 break;
827 case CS35L41_CLKID_LRCLK:
828 clksrc = CS35L41_PLLSRC_LRCLK;
829 break;
830 case CS35L41_CLKID_MCLK:
831 clksrc = CS35L41_PLLSRC_MCLK;
832 break;
833 default:
834 dev_err(cs35l41->dev, "Invalid CLK Config\n");
835 return -EINVAL;
836 }
837
838 extclk_cfg = cs35l41_get_clk_config(freq);
839
840 if (extclk_cfg < 0) {
841 dev_err(cs35l41->dev, "Invalid CLK Config: %d, freq: %u\n",
842 extclk_cfg, freq);
843 return -EINVAL;
844 }
845
846 regmap_update_bits(cs35l41->regmap, CS35L41_PLL_CLK_CTRL,
847 CS35L41_PLL_OPENLOOP_MASK,
848 1 << CS35L41_PLL_OPENLOOP_SHIFT);
849 regmap_update_bits(cs35l41->regmap, CS35L41_PLL_CLK_CTRL,
850 CS35L41_REFCLK_FREQ_MASK,
851 extclk_cfg << CS35L41_REFCLK_FREQ_SHIFT);
852 regmap_update_bits(cs35l41->regmap, CS35L41_PLL_CLK_CTRL,
853 CS35L41_PLL_CLK_EN_MASK,
854 0 << CS35L41_PLL_CLK_EN_SHIFT);
855 regmap_update_bits(cs35l41->regmap, CS35L41_PLL_CLK_CTRL,
856 CS35L41_PLL_CLK_SEL_MASK, clksrc);
857 regmap_update_bits(cs35l41->regmap, CS35L41_PLL_CLK_CTRL,
858 CS35L41_PLL_OPENLOOP_MASK,
859 0 << CS35L41_PLL_OPENLOOP_SHIFT);
860 regmap_update_bits(cs35l41->regmap, CS35L41_PLL_CLK_CTRL,
861 CS35L41_PLL_CLK_EN_MASK,
862 1 << CS35L41_PLL_CLK_EN_SHIFT);
863
864 return 0;
865 }
866
cs35l41_dai_set_sysclk(struct snd_soc_dai * dai,int clk_id,unsigned int freq,int dir)867 static int cs35l41_dai_set_sysclk(struct snd_soc_dai *dai,
868 int clk_id, unsigned int freq, int dir)
869 {
870 struct cs35l41_private *cs35l41 = snd_soc_component_get_drvdata(dai->component);
871 unsigned int fs1_val;
872 unsigned int fs2_val;
873 unsigned int val;
874 int fsindex;
875
876 fsindex = cs35l41_get_fs_mon_config_index(freq);
877 if (fsindex < 0) {
878 dev_err(cs35l41->dev, "Invalid CLK Config freq: %u\n", freq);
879 return -EINVAL;
880 }
881
882 dev_dbg(cs35l41->dev, "Set DAI sysclk %d\n", freq);
883
884 if (freq <= 6144000) {
885 /* Use the lookup table */
886 fs1_val = cs35l41_fs_mon[fsindex].fs1;
887 fs2_val = cs35l41_fs_mon[fsindex].fs2;
888 } else {
889 /* Use hard-coded values */
890 fs1_val = 0x10;
891 fs2_val = 0x24;
892 }
893
894 val = fs1_val;
895 val |= (fs2_val << CS35L41_FS2_WINDOW_SHIFT) & CS35L41_FS2_WINDOW_MASK;
896 regmap_write(cs35l41->regmap, CS35L41_TST_FS_MON0, val);
897
898 return 0;
899 }
900
cs35l41_set_pdata(struct cs35l41_private * cs35l41)901 static int cs35l41_set_pdata(struct cs35l41_private *cs35l41)
902 {
903 struct cs35l41_hw_cfg *hw_cfg = &cs35l41->hw_cfg;
904 int ret;
905
906 if (!hw_cfg->valid)
907 return -EINVAL;
908
909 if (hw_cfg->bst_type == CS35L41_EXT_BOOST_NO_VSPK_SWITCH)
910 return -EINVAL;
911
912 /* Required */
913 ret = cs35l41_init_boost(cs35l41->dev, cs35l41->regmap, hw_cfg);
914 if (ret)
915 return ret;
916
917 /* Optional */
918 if (hw_cfg->dout_hiz <= CS35L41_ASP_DOUT_HIZ_MASK && hw_cfg->dout_hiz >= 0)
919 regmap_update_bits(cs35l41->regmap, CS35L41_SP_HIZ_CTRL, CS35L41_ASP_DOUT_HIZ_MASK,
920 hw_cfg->dout_hiz);
921
922 return 0;
923 }
924
925 static const struct snd_soc_dapm_route cs35l41_ext_bst_routes[] = {
926 {"Main AMP", NULL, "VSPK"},
927 };
928
929 static const struct snd_soc_dapm_widget cs35l41_ext_bst_widget[] = {
930 SND_SOC_DAPM_SUPPLY("VSPK", CS35L41_GPIO1_CTRL1, CS35L41_GPIO_LVL_SHIFT, 0, NULL, 0),
931 };
932
cs35l41_component_probe(struct snd_soc_component * component)933 static int cs35l41_component_probe(struct snd_soc_component *component)
934 {
935 struct cs35l41_private *cs35l41 = snd_soc_component_get_drvdata(component);
936 struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
937 int ret;
938
939 if (cs35l41->hw_cfg.bst_type == CS35L41_EXT_BOOST) {
940 ret = snd_soc_dapm_new_controls(dapm, cs35l41_ext_bst_widget,
941 ARRAY_SIZE(cs35l41_ext_bst_widget));
942 if (ret)
943 return ret;
944
945 ret = snd_soc_dapm_add_routes(dapm, cs35l41_ext_bst_routes,
946 ARRAY_SIZE(cs35l41_ext_bst_routes));
947 if (ret)
948 return ret;
949 }
950
951 return wm_adsp2_component_probe(&cs35l41->dsp, component);
952 }
953
cs35l41_component_remove(struct snd_soc_component * component)954 static void cs35l41_component_remove(struct snd_soc_component *component)
955 {
956 struct cs35l41_private *cs35l41 = snd_soc_component_get_drvdata(component);
957
958 wm_adsp2_component_remove(&cs35l41->dsp, component);
959 }
960
961 static const struct snd_soc_dai_ops cs35l41_ops = {
962 .startup = cs35l41_pcm_startup,
963 .set_fmt = cs35l41_set_dai_fmt,
964 .hw_params = cs35l41_pcm_hw_params,
965 .set_sysclk = cs35l41_dai_set_sysclk,
966 .set_channel_map = cs35l41_set_channel_map,
967 };
968
969 static struct snd_soc_dai_driver cs35l41_dai[] = {
970 {
971 .name = "cs35l41-pcm",
972 .id = 0,
973 .playback = {
974 .stream_name = "AMP Playback",
975 .channels_min = 1,
976 .channels_max = 2,
977 .rates = SNDRV_PCM_RATE_KNOT,
978 .formats = CS35L41_RX_FORMATS,
979 },
980 .capture = {
981 .stream_name = "AMP Capture",
982 .channels_min = 1,
983 .channels_max = 4,
984 .rates = SNDRV_PCM_RATE_KNOT,
985 .formats = CS35L41_TX_FORMATS,
986 },
987 .ops = &cs35l41_ops,
988 .symmetric_rate = 1,
989 },
990 };
991
992 static const struct snd_soc_component_driver soc_component_dev_cs35l41 = {
993 .name = "cs35l41-codec",
994 .probe = cs35l41_component_probe,
995 .remove = cs35l41_component_remove,
996
997 .dapm_widgets = cs35l41_dapm_widgets,
998 .num_dapm_widgets = ARRAY_SIZE(cs35l41_dapm_widgets),
999 .dapm_routes = cs35l41_audio_map,
1000 .num_dapm_routes = ARRAY_SIZE(cs35l41_audio_map),
1001
1002 .controls = cs35l41_aud_controls,
1003 .num_controls = ARRAY_SIZE(cs35l41_aud_controls),
1004 .set_sysclk = cs35l41_component_set_sysclk,
1005
1006 .endianness = 1,
1007 };
1008
cs35l41_handle_pdata(struct device * dev,struct cs35l41_hw_cfg * hw_cfg)1009 static int cs35l41_handle_pdata(struct device *dev, struct cs35l41_hw_cfg *hw_cfg)
1010 {
1011 struct cs35l41_gpio_cfg *gpio1 = &hw_cfg->gpio1;
1012 struct cs35l41_gpio_cfg *gpio2 = &hw_cfg->gpio2;
1013 unsigned int val;
1014 int ret;
1015
1016 /* Some ACPI systems received the Shared Boost feature before the upstream driver,
1017 * leaving those systems with deprecated _DSD properties.
1018 * To correctly configure those systems add shared-boost-active and shared-boost-passive
1019 * properties mapped to the correct value in boost-type.
1020 * These two are not DT properties and should not be used in new systems designs.
1021 */
1022 if (device_property_read_bool(dev, "cirrus,shared-boost-active")) {
1023 hw_cfg->bst_type = CS35L41_SHD_BOOST_ACTV;
1024 } else if (device_property_read_bool(dev, "cirrus,shared-boost-passive")) {
1025 hw_cfg->bst_type = CS35L41_SHD_BOOST_PASS;
1026 } else {
1027 ret = device_property_read_u32(dev, "cirrus,boost-type", &val);
1028 if (ret >= 0)
1029 hw_cfg->bst_type = val;
1030 }
1031
1032 ret = device_property_read_u32(dev, "cirrus,boost-peak-milliamp", &val);
1033 if (ret >= 0)
1034 hw_cfg->bst_ipk = val;
1035 else
1036 hw_cfg->bst_ipk = -1;
1037
1038 ret = device_property_read_u32(dev, "cirrus,boost-ind-nanohenry", &val);
1039 if (ret >= 0)
1040 hw_cfg->bst_ind = val;
1041 else
1042 hw_cfg->bst_ind = -1;
1043
1044 ret = device_property_read_u32(dev, "cirrus,boost-cap-microfarad", &val);
1045 if (ret >= 0)
1046 hw_cfg->bst_cap = val;
1047 else
1048 hw_cfg->bst_cap = -1;
1049
1050 ret = device_property_read_u32(dev, "cirrus,asp-sdout-hiz", &val);
1051 if (ret >= 0)
1052 hw_cfg->dout_hiz = val;
1053 else
1054 hw_cfg->dout_hiz = -1;
1055
1056 /* GPIO1 Pin Config */
1057 gpio1->pol_inv = device_property_read_bool(dev, "cirrus,gpio1-polarity-invert");
1058 gpio1->out_en = device_property_read_bool(dev, "cirrus,gpio1-output-enable");
1059 ret = device_property_read_u32(dev, "cirrus,gpio1-src-select", &val);
1060 if (ret >= 0) {
1061 gpio1->func = val;
1062 gpio1->valid = true;
1063 }
1064
1065 /* GPIO2 Pin Config */
1066 gpio2->pol_inv = device_property_read_bool(dev, "cirrus,gpio2-polarity-invert");
1067 gpio2->out_en = device_property_read_bool(dev, "cirrus,gpio2-output-enable");
1068 ret = device_property_read_u32(dev, "cirrus,gpio2-src-select", &val);
1069 if (ret >= 0) {
1070 gpio2->func = val;
1071 gpio2->valid = true;
1072 }
1073
1074 hw_cfg->valid = true;
1075
1076 return 0;
1077 }
1078
cs35l41_dsp_init(struct cs35l41_private * cs35l41)1079 static int cs35l41_dsp_init(struct cs35l41_private *cs35l41)
1080 {
1081 struct wm_adsp *dsp;
1082 int ret;
1083
1084 dsp = &cs35l41->dsp;
1085 dsp->part = "cs35l41";
1086 dsp->fw = 9; /* 9 is WM_ADSP_FW_SPK_PROT in wm_adsp.c */
1087 dsp->toggle_preload = true;
1088
1089 cs35l41_configure_cs_dsp(cs35l41->dev, cs35l41->regmap, &dsp->cs_dsp);
1090
1091 ret = cs35l41_write_fs_errata(cs35l41->dev, cs35l41->regmap);
1092 if (ret < 0)
1093 return ret;
1094
1095 ret = wm_halo_init(dsp);
1096 if (ret) {
1097 dev_err(cs35l41->dev, "wm_halo_init failed: %d\n", ret);
1098 return ret;
1099 }
1100
1101 ret = regmap_write(cs35l41->regmap, CS35L41_DSP1_RX5_SRC,
1102 CS35L41_INPUT_SRC_VPMON);
1103 if (ret < 0) {
1104 dev_err(cs35l41->dev, "Write INPUT_SRC_VPMON failed: %d\n", ret);
1105 goto err_dsp;
1106 }
1107 ret = regmap_write(cs35l41->regmap, CS35L41_DSP1_RX6_SRC,
1108 CS35L41_INPUT_SRC_CLASSH);
1109 if (ret < 0) {
1110 dev_err(cs35l41->dev, "Write INPUT_SRC_CLASSH failed: %d\n", ret);
1111 goto err_dsp;
1112 }
1113 ret = regmap_write(cs35l41->regmap, CS35L41_DSP1_RX7_SRC,
1114 CS35L41_INPUT_SRC_TEMPMON);
1115 if (ret < 0) {
1116 dev_err(cs35l41->dev, "Write INPUT_SRC_TEMPMON failed: %d\n", ret);
1117 goto err_dsp;
1118 }
1119 ret = regmap_write(cs35l41->regmap, CS35L41_DSP1_RX8_SRC,
1120 CS35L41_INPUT_SRC_RSVD);
1121 if (ret < 0) {
1122 dev_err(cs35l41->dev, "Write INPUT_SRC_RSVD failed: %d\n", ret);
1123 goto err_dsp;
1124 }
1125
1126 return 0;
1127
1128 err_dsp:
1129 wm_adsp2_remove(dsp);
1130
1131 return ret;
1132 }
1133
cs35l41_acpi_get_name(struct cs35l41_private * cs35l41)1134 static int cs35l41_acpi_get_name(struct cs35l41_private *cs35l41)
1135 {
1136 acpi_handle handle = ACPI_HANDLE(cs35l41->dev);
1137 const char *sub;
1138
1139 /* If there is no ACPI_HANDLE, there is no ACPI for this system, return 0 */
1140 if (!handle)
1141 return 0;
1142
1143 sub = acpi_get_subsystem_id(handle);
1144 if (IS_ERR(sub)) {
1145 /* If bad ACPI, return 0 and fallback to legacy firmware path, otherwise fail */
1146 if (PTR_ERR(sub) == -ENODATA)
1147 return 0;
1148 else
1149 return PTR_ERR(sub);
1150 }
1151
1152 cs35l41->dsp.system_name = sub;
1153 dev_dbg(cs35l41->dev, "Subsystem ID: %s\n", cs35l41->dsp.system_name);
1154
1155 return 0;
1156 }
1157
cs35l41_probe(struct cs35l41_private * cs35l41,const struct cs35l41_hw_cfg * hw_cfg)1158 int cs35l41_probe(struct cs35l41_private *cs35l41, const struct cs35l41_hw_cfg *hw_cfg)
1159 {
1160 u32 regid, reg_revid, i, mtl_revid, int_status, chipid_match;
1161 int irq_pol = 0;
1162 int ret;
1163
1164 if (hw_cfg) {
1165 cs35l41->hw_cfg = *hw_cfg;
1166 } else {
1167 ret = cs35l41_handle_pdata(cs35l41->dev, &cs35l41->hw_cfg);
1168 if (ret != 0)
1169 return ret;
1170 }
1171
1172 for (i = 0; i < CS35L41_NUM_SUPPLIES; i++)
1173 cs35l41->supplies[i].supply = cs35l41_supplies[i];
1174
1175 ret = devm_regulator_bulk_get(cs35l41->dev, CS35L41_NUM_SUPPLIES,
1176 cs35l41->supplies);
1177 if (ret != 0) {
1178 dev_err(cs35l41->dev, "Failed to request core supplies: %d\n", ret);
1179 return ret;
1180 }
1181
1182 ret = regulator_bulk_enable(CS35L41_NUM_SUPPLIES, cs35l41->supplies);
1183 if (ret != 0) {
1184 dev_err(cs35l41->dev, "Failed to enable core supplies: %d\n", ret);
1185 return ret;
1186 }
1187
1188 /* returning NULL can be an option if in stereo mode */
1189 cs35l41->reset_gpio = devm_gpiod_get_optional(cs35l41->dev, "reset",
1190 GPIOD_OUT_LOW);
1191 if (IS_ERR(cs35l41->reset_gpio)) {
1192 ret = PTR_ERR(cs35l41->reset_gpio);
1193 cs35l41->reset_gpio = NULL;
1194 if (ret == -EBUSY) {
1195 dev_info(cs35l41->dev,
1196 "Reset line busy, assuming shared reset\n");
1197 } else {
1198 dev_err(cs35l41->dev,
1199 "Failed to get reset GPIO: %d\n", ret);
1200 goto err;
1201 }
1202 }
1203 if (cs35l41->reset_gpio) {
1204 /* satisfy minimum reset pulse width spec */
1205 usleep_range(2000, 2100);
1206 gpiod_set_value_cansleep(cs35l41->reset_gpio, 1);
1207 }
1208
1209 usleep_range(2000, 2100);
1210
1211 ret = regmap_read_poll_timeout(cs35l41->regmap, CS35L41_IRQ1_STATUS4,
1212 int_status, int_status & CS35L41_OTP_BOOT_DONE,
1213 1000, 100000);
1214 if (ret) {
1215 dev_err(cs35l41->dev,
1216 "Failed waiting for OTP_BOOT_DONE: %d\n", ret);
1217 goto err;
1218 }
1219
1220 regmap_read(cs35l41->regmap, CS35L41_IRQ1_STATUS3, &int_status);
1221 if (int_status & CS35L41_OTP_BOOT_ERR) {
1222 dev_err(cs35l41->dev, "OTP Boot error\n");
1223 ret = -EINVAL;
1224 goto err;
1225 }
1226
1227 ret = regmap_read(cs35l41->regmap, CS35L41_DEVID, ®id);
1228 if (ret < 0) {
1229 dev_err(cs35l41->dev, "Get Device ID failed: %d\n", ret);
1230 goto err;
1231 }
1232
1233 ret = regmap_read(cs35l41->regmap, CS35L41_REVID, ®_revid);
1234 if (ret < 0) {
1235 dev_err(cs35l41->dev, "Get Revision ID failed: %d\n", ret);
1236 goto err;
1237 }
1238
1239 mtl_revid = reg_revid & CS35L41_MTLREVID_MASK;
1240
1241 /* CS35L41 will have even MTLREVID
1242 * CS35L41R will have odd MTLREVID
1243 */
1244 chipid_match = (mtl_revid % 2) ? CS35L41R_CHIP_ID : CS35L41_CHIP_ID;
1245 if (regid != chipid_match) {
1246 dev_err(cs35l41->dev, "CS35L41 Device ID (%X). Expected ID %X\n",
1247 regid, chipid_match);
1248 ret = -ENODEV;
1249 goto err;
1250 }
1251
1252 cs35l41_test_key_unlock(cs35l41->dev, cs35l41->regmap);
1253
1254 ret = cs35l41_register_errata_patch(cs35l41->dev, cs35l41->regmap, reg_revid);
1255 if (ret)
1256 goto err;
1257
1258 ret = cs35l41_otp_unpack(cs35l41->dev, cs35l41->regmap);
1259 if (ret < 0) {
1260 dev_err(cs35l41->dev, "OTP Unpack failed: %d\n", ret);
1261 goto err;
1262 }
1263
1264 cs35l41_test_key_lock(cs35l41->dev, cs35l41->regmap);
1265
1266 irq_pol = cs35l41_gpio_config(cs35l41->regmap, &cs35l41->hw_cfg);
1267
1268 /* Set interrupt masks for critical errors */
1269 regmap_write(cs35l41->regmap, CS35L41_IRQ1_MASK1,
1270 CS35L41_INT1_MASK_DEFAULT);
1271 if (cs35l41->hw_cfg.bst_type == CS35L41_SHD_BOOST_PASS ||
1272 cs35l41->hw_cfg.bst_type == CS35L41_SHD_BOOST_ACTV)
1273 regmap_update_bits(cs35l41->regmap, CS35L41_IRQ1_MASK3, CS35L41_INT3_PLL_LOCK_MASK,
1274 0 << CS35L41_INT3_PLL_LOCK_SHIFT);
1275
1276 ret = devm_request_threaded_irq(cs35l41->dev, cs35l41->irq, NULL, cs35l41_irq,
1277 IRQF_ONESHOT | IRQF_SHARED | irq_pol,
1278 "cs35l41", cs35l41);
1279 if (ret != 0) {
1280 dev_err(cs35l41->dev, "Failed to request IRQ: %d\n", ret);
1281 goto err;
1282 }
1283
1284 ret = cs35l41_set_pdata(cs35l41);
1285 if (ret < 0) {
1286 dev_err(cs35l41->dev, "Set pdata failed: %d\n", ret);
1287 goto err;
1288 }
1289
1290 ret = cs35l41_acpi_get_name(cs35l41);
1291 if (ret < 0)
1292 goto err;
1293
1294 ret = cs35l41_dsp_init(cs35l41);
1295 if (ret < 0)
1296 goto err;
1297
1298 init_completion(&cs35l41->pll_lock);
1299
1300 pm_runtime_set_autosuspend_delay(cs35l41->dev, 3000);
1301 pm_runtime_use_autosuspend(cs35l41->dev);
1302 pm_runtime_mark_last_busy(cs35l41->dev);
1303 pm_runtime_set_active(cs35l41->dev);
1304 pm_runtime_get_noresume(cs35l41->dev);
1305 pm_runtime_enable(cs35l41->dev);
1306
1307 ret = devm_snd_soc_register_component(cs35l41->dev,
1308 &soc_component_dev_cs35l41,
1309 cs35l41_dai, ARRAY_SIZE(cs35l41_dai));
1310 if (ret < 0) {
1311 dev_err(cs35l41->dev, "Register codec failed: %d\n", ret);
1312 goto err_pm;
1313 }
1314
1315 pm_runtime_put_autosuspend(cs35l41->dev);
1316
1317 dev_info(cs35l41->dev, "Cirrus Logic CS35L41 (%x), Revision: %02X\n",
1318 regid, reg_revid);
1319
1320 return 0;
1321
1322 err_pm:
1323 pm_runtime_disable(cs35l41->dev);
1324 pm_runtime_put_noidle(cs35l41->dev);
1325
1326 wm_adsp2_remove(&cs35l41->dsp);
1327 err:
1328 cs35l41_safe_reset(cs35l41->regmap, cs35l41->hw_cfg.bst_type);
1329 regulator_bulk_disable(CS35L41_NUM_SUPPLIES, cs35l41->supplies);
1330 gpiod_set_value_cansleep(cs35l41->reset_gpio, 0);
1331
1332 return ret;
1333 }
1334 EXPORT_SYMBOL_GPL(cs35l41_probe);
1335
cs35l41_remove(struct cs35l41_private * cs35l41)1336 void cs35l41_remove(struct cs35l41_private *cs35l41)
1337 {
1338 pm_runtime_get_sync(cs35l41->dev);
1339 pm_runtime_disable(cs35l41->dev);
1340
1341 regmap_write(cs35l41->regmap, CS35L41_IRQ1_MASK1, 0xFFFFFFFF);
1342 if (cs35l41->hw_cfg.bst_type == CS35L41_SHD_BOOST_PASS ||
1343 cs35l41->hw_cfg.bst_type == CS35L41_SHD_BOOST_ACTV)
1344 regmap_update_bits(cs35l41->regmap, CS35L41_IRQ1_MASK3, CS35L41_INT3_PLL_LOCK_MASK,
1345 1 << CS35L41_INT3_PLL_LOCK_SHIFT);
1346 kfree(cs35l41->dsp.system_name);
1347 wm_adsp2_remove(&cs35l41->dsp);
1348 cs35l41_safe_reset(cs35l41->regmap, cs35l41->hw_cfg.bst_type);
1349
1350 pm_runtime_put_noidle(cs35l41->dev);
1351
1352 regulator_bulk_disable(CS35L41_NUM_SUPPLIES, cs35l41->supplies);
1353 gpiod_set_value_cansleep(cs35l41->reset_gpio, 0);
1354 }
1355 EXPORT_SYMBOL_GPL(cs35l41_remove);
1356
cs35l41_runtime_suspend(struct device * dev)1357 static int __maybe_unused cs35l41_runtime_suspend(struct device *dev)
1358 {
1359 struct cs35l41_private *cs35l41 = dev_get_drvdata(dev);
1360
1361 dev_dbg(cs35l41->dev, "Runtime suspend\n");
1362
1363 if (!cs35l41->dsp.preloaded || !cs35l41->dsp.cs_dsp.running)
1364 return 0;
1365
1366 cs35l41_enter_hibernate(dev, cs35l41->regmap, cs35l41->hw_cfg.bst_type);
1367
1368 regcache_cache_only(cs35l41->regmap, true);
1369 regcache_mark_dirty(cs35l41->regmap);
1370
1371 return 0;
1372 }
1373
cs35l41_runtime_resume(struct device * dev)1374 static int __maybe_unused cs35l41_runtime_resume(struct device *dev)
1375 {
1376 struct cs35l41_private *cs35l41 = dev_get_drvdata(dev);
1377 int ret;
1378
1379 dev_dbg(cs35l41->dev, "Runtime resume\n");
1380
1381 if (!cs35l41->dsp.preloaded || !cs35l41->dsp.cs_dsp.running)
1382 return 0;
1383
1384 regcache_cache_only(cs35l41->regmap, false);
1385
1386 ret = cs35l41_exit_hibernate(cs35l41->dev, cs35l41->regmap);
1387 if (ret)
1388 return ret;
1389
1390 /* Test key needs to be unlocked to allow the OTP settings to re-apply */
1391 cs35l41_test_key_unlock(cs35l41->dev, cs35l41->regmap);
1392 ret = regcache_sync(cs35l41->regmap);
1393 cs35l41_test_key_lock(cs35l41->dev, cs35l41->regmap);
1394 if (ret) {
1395 dev_err(cs35l41->dev, "Failed to restore register cache: %d\n", ret);
1396 return ret;
1397 }
1398 cs35l41_init_boost(cs35l41->dev, cs35l41->regmap, &cs35l41->hw_cfg);
1399
1400 return 0;
1401 }
1402
cs35l41_sys_suspend(struct device * dev)1403 static int __maybe_unused cs35l41_sys_suspend(struct device *dev)
1404 {
1405 struct cs35l41_private *cs35l41 = dev_get_drvdata(dev);
1406
1407 dev_dbg(cs35l41->dev, "System suspend, disabling IRQ\n");
1408 disable_irq(cs35l41->irq);
1409
1410 return 0;
1411 }
1412
cs35l41_sys_suspend_noirq(struct device * dev)1413 static int __maybe_unused cs35l41_sys_suspend_noirq(struct device *dev)
1414 {
1415 struct cs35l41_private *cs35l41 = dev_get_drvdata(dev);
1416
1417 dev_dbg(cs35l41->dev, "Late system suspend, reenabling IRQ\n");
1418 enable_irq(cs35l41->irq);
1419
1420 return 0;
1421 }
1422
cs35l41_sys_resume_noirq(struct device * dev)1423 static int __maybe_unused cs35l41_sys_resume_noirq(struct device *dev)
1424 {
1425 struct cs35l41_private *cs35l41 = dev_get_drvdata(dev);
1426
1427 dev_dbg(cs35l41->dev, "Early system resume, disabling IRQ\n");
1428 disable_irq(cs35l41->irq);
1429
1430 return 0;
1431 }
1432
cs35l41_sys_resume(struct device * dev)1433 static int __maybe_unused cs35l41_sys_resume(struct device *dev)
1434 {
1435 struct cs35l41_private *cs35l41 = dev_get_drvdata(dev);
1436
1437 dev_dbg(cs35l41->dev, "System resume, reenabling IRQ\n");
1438 enable_irq(cs35l41->irq);
1439
1440 return 0;
1441 }
1442
1443 const struct dev_pm_ops cs35l41_pm_ops = {
1444 SET_RUNTIME_PM_OPS(cs35l41_runtime_suspend, cs35l41_runtime_resume, NULL)
1445
1446 SET_SYSTEM_SLEEP_PM_OPS(cs35l41_sys_suspend, cs35l41_sys_resume)
1447 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(cs35l41_sys_suspend_noirq, cs35l41_sys_resume_noirq)
1448 };
1449 EXPORT_SYMBOL_GPL(cs35l41_pm_ops);
1450
1451 MODULE_DESCRIPTION("ASoC CS35L41 driver");
1452 MODULE_AUTHOR("David Rhodes, Cirrus Logic Inc, <david.rhodes@cirrus.com>");
1453 MODULE_LICENSE("GPL");
1454
