1/* 2 * Broadcom BCM470X / BCM5301X ARM platform code. 3 * Generic DTS part for all BCM53010, BCM53011, BCM53012, BCM53014, BCM53015, 4 * BCM53016, BCM53017, BCM53018, BCM4707, BCM4708 and BCM4709 SoCs 5 * 6 * Copyright 2013-2014 Hauke Mehrtens <hauke@hauke-m.de> 7 * 8 * Licensed under the GNU/GPL. See COPYING for details. 9 */ 10 11#include <dt-bindings/clock/bcm-nsp.h> 12#include <dt-bindings/gpio/gpio.h> 13#include <dt-bindings/input/input.h> 14#include <dt-bindings/interrupt-controller/irq.h> 15#include <dt-bindings/interrupt-controller/arm-gic.h> 16 17/ { 18 #address-cells = <1>; 19 #size-cells = <1>; 20 interrupt-parent = <&gic>; 21 22 chipcommonA@18000000 { 23 compatible = "simple-bus"; 24 ranges = <0x00000000 0x18000000 0x00001000>; 25 #address-cells = <1>; 26 #size-cells = <1>; 27 28 uart0: serial@300 { 29 compatible = "ns16550"; 30 reg = <0x0300 0x100>; 31 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 32 clocks = <&iprocslow>; 33 status = "disabled"; 34 }; 35 36 uart1: serial@400 { 37 compatible = "ns16550"; 38 reg = <0x0400 0x100>; 39 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 40 clocks = <&iprocslow>; 41 pinctrl-names = "default"; 42 pinctrl-0 = <&pinmux_uart1>; 43 status = "disabled"; 44 }; 45 }; 46 47 mpcore@19000000 { 48 compatible = "simple-bus"; 49 ranges = <0x00000000 0x19000000 0x00023000>; 50 #address-cells = <1>; 51 #size-cells = <1>; 52 53 a9pll: arm_clk@0 { 54 #clock-cells = <0>; 55 compatible = "brcm,nsp-armpll"; 56 clocks = <&osc>; 57 reg = <0x00000 0x1000>; 58 }; 59 60 scu@20000 { 61 compatible = "arm,cortex-a9-scu"; 62 reg = <0x20000 0x100>; 63 }; 64 65 timer@20200 { 66 compatible = "arm,cortex-a9-global-timer"; 67 reg = <0x20200 0x100>; 68 interrupts = <GIC_PPI 11 IRQ_TYPE_EDGE_RISING>; 69 clocks = <&periph_clk>; 70 }; 71 72 timer@20600 { 73 compatible = "arm,cortex-a9-twd-timer"; 74 reg = <0x20600 0x20>; 75 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | 76 IRQ_TYPE_EDGE_RISING)>; 77 clocks = <&periph_clk>; 78 }; 79 80 watchdog@20620 { 81 compatible = "arm,cortex-a9-twd-wdt"; 82 reg = <0x20620 0x20>; 83 interrupts = <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | 84 IRQ_TYPE_EDGE_RISING)>; 85 clocks = <&periph_clk>; 86 }; 87 88 gic: interrupt-controller@21000 { 89 compatible = "arm,cortex-a9-gic"; 90 #interrupt-cells = <3>; 91 #address-cells = <0>; 92 interrupt-controller; 93 reg = <0x21000 0x1000>, 94 <0x20100 0x100>; 95 }; 96 97 L2: cache-controller@22000 { 98 compatible = "arm,pl310-cache"; 99 reg = <0x22000 0x1000>; 100 cache-unified; 101 arm,shared-override; 102 prefetch-data = <1>; 103 prefetch-instr = <1>; 104 cache-level = <2>; 105 }; 106 }; 107 108 pmu { 109 compatible = "arm,cortex-a9-pmu"; 110 interrupts = 111 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 112 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 113 }; 114 115 clocks { 116 #address-cells = <1>; 117 #size-cells = <1>; 118 ranges; 119 120 osc: oscillator { 121 #clock-cells = <0>; 122 compatible = "fixed-clock"; 123 clock-frequency = <25000000>; 124 }; 125 126 iprocmed: iprocmed { 127 #clock-cells = <0>; 128 compatible = "fixed-factor-clock"; 129 clocks = <&genpll BCM_NSP_GENPLL_IPROCFAST_CLK>; 130 clock-div = <2>; 131 clock-mult = <1>; 132 }; 133 134 iprocslow: iprocslow { 135 #clock-cells = <0>; 136 compatible = "fixed-factor-clock"; 137 clocks = <&genpll BCM_NSP_GENPLL_IPROCFAST_CLK>; 138 clock-div = <4>; 139 clock-mult = <1>; 140 }; 141 142 periph_clk: periph_clk { 143 #clock-cells = <0>; 144 compatible = "fixed-factor-clock"; 145 clocks = <&a9pll>; 146 clock-div = <2>; 147 clock-mult = <1>; 148 }; 149 }; 150 151 usb2_phy: usb2-phy@1800c000 { 152 compatible = "brcm,ns-usb2-phy"; 153 reg = <0x1800c000 0x1000>; 154 reg-names = "dmu"; 155 #phy-cells = <0>; 156 clocks = <&genpll BCM_NSP_GENPLL_USB_PHY_REF_CLK>; 157 clock-names = "phy-ref-clk"; 158 }; 159 160 axi@18000000 { 161 compatible = "brcm,bus-axi"; 162 reg = <0x18000000 0x1000>; 163 ranges = <0x00000000 0x18000000 0x00100000>; 164 #address-cells = <1>; 165 #size-cells = <1>; 166 167 #interrupt-cells = <1>; 168 interrupt-map-mask = <0x000fffff 0xffff>; 169 interrupt-map = 170 /* ChipCommon */ 171 <0x00000000 0 &gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, 172 173 /* Switch Register Access Block */ 174 <0x00007000 0 &gic GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, 175 <0x00007000 1 &gic GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 176 <0x00007000 2 &gic GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 177 <0x00007000 3 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 178 <0x00007000 4 &gic GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 179 <0x00007000 5 &gic GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 180 <0x00007000 6 &gic GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 181 <0x00007000 7 &gic GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 182 <0x00007000 8 &gic GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 183 <0x00007000 9 &gic GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 184 <0x00007000 10 &gic GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 185 <0x00007000 11 &gic GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 186 <0x00007000 12 &gic GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 187 188 /* PCIe Controller 0 */ 189 <0x00012000 0 &gic GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, 190 <0x00012000 1 &gic GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>, 191 <0x00012000 2 &gic GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, 192 <0x00012000 3 &gic GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, 193 <0x00012000 4 &gic GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 194 <0x00012000 5 &gic GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 195 196 /* PCIe Controller 1 */ 197 <0x00013000 0 &gic GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, 198 <0x00013000 1 &gic GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 199 <0x00013000 2 &gic GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, 200 <0x00013000 3 &gic GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 201 <0x00013000 4 &gic GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 202 <0x00013000 5 &gic GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, 203 204 /* PCIe Controller 2 */ 205 <0x00014000 0 &gic GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, 206 <0x00014000 1 &gic GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, 207 <0x00014000 2 &gic GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, 208 <0x00014000 3 &gic GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 209 <0x00014000 4 &gic GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 210 <0x00014000 5 &gic GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, 211 212 /* USB 2.0 Controller */ 213 <0x00021000 0 &gic GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>, 214 215 /* USB 3.0 Controller */ 216 <0x00023000 0 &gic GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>, 217 218 /* Ethernet Controller 0 */ 219 <0x00024000 0 &gic GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 220 221 /* Ethernet Controller 1 */ 222 <0x00025000 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, 223 224 /* Ethernet Controller 2 */ 225 <0x00026000 0 &gic GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 226 227 /* Ethernet Controller 3 */ 228 <0x00027000 0 &gic GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, 229 230 /* NAND Controller */ 231 <0x00028000 0 &gic GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, 232 <0x00028000 1 &gic GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 233 <0x00028000 2 &gic GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>, 234 <0x00028000 3 &gic GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>, 235 <0x00028000 4 &gic GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, 236 <0x00028000 5 &gic GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>, 237 <0x00028000 6 &gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, 238 <0x00028000 7 &gic GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 239 240 chipcommon: chipcommon@0 { 241 reg = <0x00000000 0x1000>; 242 243 gpio-controller; 244 #gpio-cells = <2>; 245 }; 246 247 pcie0: pcie@12000 { 248 reg = <0x00012000 0x1000>; 249 }; 250 251 pcie1: pcie@13000 { 252 reg = <0x00013000 0x1000>; 253 }; 254 255 pcie2: pcie@14000 { 256 reg = <0x00014000 0x1000>; 257 }; 258 259 usb2: usb2@21000 { 260 reg = <0x00021000 0x1000>; 261 262 #address-cells = <1>; 263 #size-cells = <1>; 264 ranges; 265 266 interrupt-parent = <&gic>; 267 268 ehci: ehci@21000 { 269 #usb-cells = <0>; 270 271 compatible = "generic-ehci"; 272 reg = <0x00021000 0x1000>; 273 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 274 phys = <&usb2_phy>; 275 276 #address-cells = <1>; 277 #size-cells = <0>; 278 279 ehci_port1: port@1 { 280 reg = <1>; 281 #trigger-source-cells = <0>; 282 }; 283 284 ehci_port2: port@2 { 285 reg = <2>; 286 #trigger-source-cells = <0>; 287 }; 288 }; 289 290 ohci: ohci@22000 { 291 #usb-cells = <0>; 292 293 compatible = "generic-ohci"; 294 reg = <0x00022000 0x1000>; 295 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 296 297 #address-cells = <1>; 298 #size-cells = <0>; 299 300 ohci_port1: port@1 { 301 reg = <1>; 302 #trigger-source-cells = <0>; 303 }; 304 305 ohci_port2: port@2 { 306 reg = <2>; 307 #trigger-source-cells = <0>; 308 }; 309 }; 310 }; 311 312 usb3: usb3@23000 { 313 reg = <0x00023000 0x1000>; 314 315 #address-cells = <1>; 316 #size-cells = <1>; 317 ranges; 318 319 interrupt-parent = <&gic>; 320 321 xhci: xhci@23000 { 322 #usb-cells = <0>; 323 324 compatible = "generic-xhci"; 325 reg = <0x00023000 0x1000>; 326 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; 327 phys = <&usb3_phy>; 328 phy-names = "usb"; 329 330 #address-cells = <1>; 331 #size-cells = <0>; 332 333 xhci_port1: port@1 { 334 reg = <1>; 335 #trigger-source-cells = <0>; 336 }; 337 }; 338 }; 339 340 gmac0: ethernet@24000 { 341 reg = <0x24000 0x800>; 342 }; 343 344 gmac1: ethernet@25000 { 345 reg = <0x25000 0x800>; 346 }; 347 348 gmac2: ethernet@26000 { 349 reg = <0x26000 0x800>; 350 }; 351 352 gmac3: ethernet@27000 { 353 reg = <0x27000 0x800>; 354 }; 355 }; 356 357 pwm: pwm@18002000 { 358 compatible = "brcm,iproc-pwm"; 359 reg = <0x18002000 0x28>; 360 clocks = <&osc>; 361 #pwm-cells = <3>; 362 status = "disabled"; 363 }; 364 365 mdio: mdio@18003000 { 366 compatible = "brcm,iproc-mdio"; 367 reg = <0x18003000 0x8>; 368 #size-cells = <0>; 369 #address-cells = <1>; 370 }; 371 372 mdio-bus-mux@18003000 { 373 compatible = "mdio-mux-mmioreg"; 374 mdio-parent-bus = <&mdio>; 375 #address-cells = <1>; 376 #size-cells = <0>; 377 reg = <0x18003000 0x4>; 378 mux-mask = <0x200>; 379 380 mdio@0 { 381 reg = <0x0>; 382 #address-cells = <1>; 383 #size-cells = <0>; 384 385 usb3_phy: usb3-phy@10 { 386 compatible = "brcm,ns-ax-usb3-phy"; 387 reg = <0x10>; 388 usb3-dmp-syscon = <&usb3_dmp>; 389 #phy-cells = <0>; 390 status = "disabled"; 391 }; 392 }; 393 }; 394 395 usb3_dmp: syscon@18105000 { 396 reg = <0x18105000 0x1000>; 397 }; 398 399 uart2: serial@18008000 { 400 compatible = "ns16550a"; 401 reg = <0x18008000 0x20>; 402 clocks = <&iprocslow>; 403 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 404 reg-shift = <2>; 405 status = "disabled"; 406 }; 407 408 i2c0: i2c@18009000 { 409 compatible = "brcm,iproc-i2c"; 410 reg = <0x18009000 0x50>; 411 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; 412 #address-cells = <1>; 413 #size-cells = <0>; 414 clock-frequency = <100000>; 415 status = "disabled"; 416 }; 417 418 dmu@1800c000 { 419 compatible = "simple-bus"; 420 ranges = <0 0x1800c000 0x1000>; 421 #address-cells = <1>; 422 #size-cells = <1>; 423 424 cru@100 { 425 compatible = "simple-bus"; 426 reg = <0x100 0x1a4>; 427 ranges; 428 #address-cells = <1>; 429 #size-cells = <1>; 430 431 pin-controller@1c0 { 432 compatible = "brcm,bcm4708-pinmux"; 433 reg = <0x1c0 0x24>; 434 reg-names = "cru_gpio_control"; 435 436 spi-pins { 437 groups = "spi_grp"; 438 function = "spi"; 439 }; 440 441 pinmux_i2c: i2c { 442 groups = "i2c_grp"; 443 function = "i2c"; 444 }; 445 446 pinmux_pwm: pwm { 447 groups = "pwm0_grp", "pwm1_grp", 448 "pwm2_grp", "pwm3_grp"; 449 function = "pwm"; 450 }; 451 452 pinmux_uart1: uart1 { 453 groups = "uart1_grp"; 454 function = "uart1"; 455 }; 456 }; 457 }; 458 }; 459 460 lcpll0: lcpll0@1800c100 { 461 #clock-cells = <1>; 462 compatible = "brcm,nsp-lcpll0"; 463 reg = <0x1800c100 0x14>; 464 clocks = <&osc>; 465 clock-output-names = "lcpll0", "pcie_phy", "sdio", 466 "ddr_phy"; 467 }; 468 469 genpll: genpll@1800c140 { 470 #clock-cells = <1>; 471 compatible = "brcm,nsp-genpll"; 472 reg = <0x1800c140 0x24>; 473 clocks = <&osc>; 474 clock-output-names = "genpll", "phy", "ethernetclk", 475 "usbclk", "iprocfast", "sata1", 476 "sata2"; 477 }; 478 479 thermal: thermal@1800c2c0 { 480 compatible = "brcm,ns-thermal"; 481 reg = <0x1800c2c0 0x10>; 482 #thermal-sensor-cells = <0>; 483 }; 484 485 srab: srab@18007000 { 486 compatible = "brcm,bcm5301x-srab"; 487 reg = <0x18007000 0x1000>; 488 489 status = "disabled"; 490 491 /* ports are defined in board DTS */ 492 }; 493 494 rng: rng@18004000 { 495 compatible = "brcm,bcm5301x-rng"; 496 reg = <0x18004000 0x14>; 497 }; 498 499 nand: nand@18028000 { 500 compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1", "brcm,brcmnand"; 501 reg = <0x18028000 0x600>, <0x1811a408 0x600>, <0x18028f00 0x20>; 502 reg-names = "nand", "iproc-idm", "iproc-ext"; 503 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; 504 505 #address-cells = <1>; 506 #size-cells = <0>; 507 508 brcm,nand-has-wp; 509 }; 510 511 spi@18029200 { 512 compatible = "brcm,spi-nsp-qspi", "brcm,spi-bcm-qspi"; 513 reg = <0x18029200 0x184>, 514 <0x18029000 0x124>, 515 <0x1811b408 0x004>, 516 <0x180293a0 0x01c>; 517 reg-names = "mspi", "bspi", "intr_regs", "intr_status_reg"; 518 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, 519 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, 520 <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>, 521 <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>, 522 <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, 523 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>, 524 <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 525 interrupt-names = "spi_lr_fullness_reached", 526 "spi_lr_session_aborted", 527 "spi_lr_impatient", 528 "spi_lr_session_done", 529 "spi_lr_overhead", 530 "mspi_done", 531 "mspi_halted"; 532 clocks = <&iprocmed>; 533 clock-names = "iprocmed"; 534 num-cs = <2>; 535 #address-cells = <1>; 536 #size-cells = <0>; 537 538 spi_nor: spi-nor@0 { 539 compatible = "jedec,spi-nor"; 540 reg = <0>; 541 spi-max-frequency = <20000000>; 542 status = "disabled"; 543 544 partitions { 545 compatible = "brcm,bcm947xx-cfe-partitions"; 546 }; 547 }; 548 }; 549 550 thermal-zones { 551 cpu_thermal: cpu-thermal { 552 polling-delay-passive = <0>; 553 polling-delay = <1000>; 554 coefficients = <(-556) 418000>; 555 thermal-sensors = <&thermal>; 556 557 trips { 558 cpu-crit { 559 temperature = <125000>; 560 hysteresis = <0>; 561 type = "critical"; 562 }; 563 }; 564 565 cooling-maps { 566 }; 567 }; 568 }; 569}; 570
