1/* 2 * BSD LICENSE 3 * 4 * Copyright(c) 2015 Broadcom Corporation. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 10 * * Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * * Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in 14 * the documentation and/or other materials provided with the 15 * distribution. 16 * * Neither the name of Broadcom Corporation nor the names of its 17 * contributors may be used to endorse or promote products derived 18 * from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 21 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 22 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 23 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 24 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 25 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 26 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 30 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33#include <dt-bindings/interrupt-controller/arm-gic.h> 34#include <dt-bindings/interrupt-controller/irq.h> 35#include <dt-bindings/clock/bcm-nsp.h> 36 37/ { 38 #address-cells = <1>; 39 #size-cells = <1>; 40 compatible = "brcm,nsp"; 41 model = "Broadcom Northstar Plus SoC"; 42 interrupt-parent = <&gic>; 43 44 aliases { 45 serial0 = &uart0; 46 serial1 = &uart1; 47 ethernet0 = &amac0; 48 ethernet1 = &amac1; 49 ethernet2 = &amac2; 50 }; 51 52 cpus { 53 #address-cells = <1>; 54 #size-cells = <0>; 55 56 cpu0: cpu@0 { 57 device_type = "cpu"; 58 compatible = "arm,cortex-a9"; 59 next-level-cache = <&L2>; 60 reg = <0x0>; 61 }; 62 63 cpu1: cpu@1 { 64 device_type = "cpu"; 65 compatible = "arm,cortex-a9"; 66 next-level-cache = <&L2>; 67 enable-method = "brcm,bcm-nsp-smp"; 68 secondary-boot-reg = <0xffff0fec>; 69 reg = <0x1>; 70 }; 71 }; 72 73 pmu { 74 compatible = "arm,cortex-a9-pmu"; 75 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH 76 GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 77 interrupt-affinity = <&cpu0>, <&cpu1>; 78 }; 79 80 mpcore@19000000 { 81 compatible = "simple-bus"; 82 ranges = <0x00000000 0x19000000 0x00023000>; 83 #address-cells = <1>; 84 #size-cells = <1>; 85 86 a9pll: arm_clk@0 { 87 #clock-cells = <0>; 88 compatible = "brcm,nsp-armpll"; 89 clocks = <&osc>; 90 reg = <0x00000 0x1000>; 91 }; 92 93 timer@20200 { 94 compatible = "arm,cortex-a9-global-timer"; 95 reg = <0x20200 0x100>; 96 interrupts = <GIC_PPI 11 IRQ_TYPE_EDGE_RISING>; 97 clocks = <&periph_clk>; 98 }; 99 100 twd-timer@20600 { 101 compatible = "arm,cortex-a9-twd-timer"; 102 reg = <0x20600 0x20>; 103 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | 104 IRQ_TYPE_EDGE_RISING)>; 105 clocks = <&periph_clk>; 106 }; 107 108 twd-watchdog@20620 { 109 compatible = "arm,cortex-a9-twd-wdt"; 110 reg = <0x20620 0x20>; 111 interrupts = <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | 112 IRQ_TYPE_LEVEL_HIGH)>; 113 clocks = <&periph_clk>; 114 }; 115 116 gic: interrupt-controller@21000 { 117 compatible = "arm,cortex-a9-gic"; 118 #interrupt-cells = <3>; 119 #address-cells = <0>; 120 interrupt-controller; 121 reg = <0x21000 0x1000>, 122 <0x20100 0x100>; 123 }; 124 125 L2: cache-controller@22000 { 126 compatible = "arm,pl310-cache"; 127 reg = <0x22000 0x1000>; 128 cache-unified; 129 cache-level = <2>; 130 }; 131 }; 132 133 clocks { 134 #address-cells = <1>; 135 #size-cells = <1>; 136 ranges; 137 138 osc: oscillator { 139 #clock-cells = <0>; 140 compatible = "fixed-clock"; 141 clock-frequency = <25000000>; 142 }; 143 144 iprocmed: iprocmed { 145 #clock-cells = <0>; 146 compatible = "fixed-factor-clock"; 147 clocks = <&genpll BCM_NSP_GENPLL_IPROCFAST_CLK>; 148 clock-div = <2>; 149 clock-mult = <1>; 150 }; 151 152 iprocslow: iprocslow { 153 #clock-cells = <0>; 154 compatible = "fixed-factor-clock"; 155 clocks = <&genpll BCM_NSP_GENPLL_IPROCFAST_CLK>; 156 clock-div = <4>; 157 clock-mult = <1>; 158 }; 159 160 periph_clk: periph_clk { 161 #clock-cells = <0>; 162 compatible = "fixed-factor-clock"; 163 clocks = <&a9pll>; 164 clock-div = <2>; 165 clock-mult = <1>; 166 }; 167 }; 168 169 axi@18000000 { 170 compatible = "simple-bus"; 171 ranges = <0x00000000 0x18000000 0x0011c40c>; 172 #address-cells = <1>; 173 #size-cells = <1>; 174 175 gpioa: gpio@20 { 176 compatible = "brcm,nsp-gpio-a"; 177 reg = <0x0020 0x70>, 178 <0x3f1c4 0x1c>; 179 #gpio-cells = <2>; 180 gpio-controller; 181 ngpios = <32>; 182 interrupt-controller; 183 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 184 gpio-ranges = <&pinctrl 0 0 32>; 185 }; 186 187 uart0: serial@300 { 188 compatible = "ns16550a"; 189 reg = <0x0300 0x100>; 190 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 191 clocks = <&osc>; 192 status = "disabled"; 193 }; 194 195 uart1: serial@400 { 196 compatible = "ns16550a"; 197 reg = <0x0400 0x100>; 198 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 199 clocks = <&osc>; 200 status = "disabled"; 201 }; 202 203 dma: dma@20000 { 204 compatible = "arm,pl330", "arm,primecell"; 205 reg = <0x20000 0x1000>; 206 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, 207 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>, 208 <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, 209 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>, 210 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, 211 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>, 212 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, 213 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, 214 <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 215 clocks = <&iprocslow>; 216 clock-names = "apb_pclk"; 217 #dma-cells = <1>; 218 dma-coherent; 219 status = "disabled"; 220 }; 221 222 sdio: sdhci@21000 { 223 compatible = "brcm,sdhci-iproc-cygnus"; 224 reg = <0x21000 0x100>; 225 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>; 226 sdhci,auto-cmd12; 227 clocks = <&lcpll0 BCM_NSP_LCPLL0_SDIO_CLK>; 228 dma-coherent; 229 status = "disabled"; 230 }; 231 232 amac0: ethernet@22000 { 233 compatible = "brcm,nsp-amac"; 234 reg = <0x022000 0x1000>, 235 <0x110000 0x1000>; 236 reg-names = "amac_base", "idm_base"; 237 interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>; 238 dma-coherent; 239 status = "disabled"; 240 }; 241 242 amac1: ethernet@23000 { 243 compatible = "brcm,nsp-amac"; 244 reg = <0x023000 0x1000>, 245 <0x111000 0x1000>; 246 reg-names = "amac_base", "idm_base"; 247 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; 248 dma-coherent; 249 status = "disabled"; 250 }; 251 252 amac2: ethernet@24000 { 253 compatible = "brcm,nsp-amac"; 254 reg = <0x024000 0x1000>, 255 <0x112000 0x1000>; 256 reg-names = "amac_base", "idm_base"; 257 interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>; 258 dma-coherent; 259 status = "disabled"; 260 }; 261 262 mailbox: mailbox@25c00 { 263 compatible = "brcm,iproc-fa2-mbox"; 264 reg = <0x25c00 0x400>; 265 interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>; 266 #mbox-cells = <1>; 267 brcm,rx-status-len = <32>; 268 brcm,use-bcm-hdr; 269 dma-coherent; 270 }; 271 272 nand: nand@26000 { 273 compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1"; 274 reg = <0x026000 0x600>, 275 <0x11b408 0x600>, 276 <0x026f00 0x20>; 277 reg-names = "nand", "iproc-idm", "iproc-ext"; 278 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; 279 280 #address-cells = <1>; 281 #size-cells = <0>; 282 283 brcm,nand-has-wp; 284 }; 285 286 qspi: spi@27200 { 287 compatible = "brcm,spi-nsp-qspi", "brcm,spi-bcm-qspi"; 288 reg = <0x027200 0x184>, 289 <0x027000 0x124>, 290 <0x11c408 0x004>, 291 <0x0273a0 0x01c>; 292 reg-names = "mspi", "bspi", "intr_regs", 293 "intr_status_reg"; 294 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, 295 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, 296 <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>, 297 <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>, 298 <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, 299 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>, 300 <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 301 interrupt-names = "spi_lr_fullness_reached", 302 "spi_lr_session_aborted", 303 "spi_lr_impatient", 304 "spi_lr_session_done", 305 "spi_lr_overhead", 306 "mspi_done", 307 "mspi_halted"; 308 clocks = <&iprocmed>; 309 clock-names = "iprocmed"; 310 num-cs = <2>; 311 #address-cells = <1>; 312 #size-cells = <0>; 313 }; 314 315 xhci: usb@29000 { 316 compatible = "generic-xhci"; 317 reg = <0x29000 0x1000>; 318 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; 319 phys = <&usb3_phy>; 320 phy-names = "usb3-phy"; 321 dma-coherent; 322 status = "disabled"; 323 }; 324 325 ehci0: usb@2a000 { 326 compatible = "generic-ehci"; 327 reg = <0x2a000 0x100>; 328 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 329 dma-coherent; 330 status = "disabled"; 331 }; 332 333 ohci0: usb@2b000 { 334 compatible = "generic-ohci"; 335 reg = <0x2b000 0x100>; 336 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 337 dma-coherent; 338 status = "disabled"; 339 }; 340 341 crypto@2f000 { 342 compatible = "brcm,spum-nsp-crypto"; 343 reg = <0x2f000 0x900>; 344 mboxes = <&mailbox 0>; 345 }; 346 347 gpiob: gpio@30000 { 348 compatible = "brcm,iproc-nsp-gpio", "brcm,iproc-gpio"; 349 reg = <0x30000 0x50>; 350 #gpio-cells = <2>; 351 gpio-controller; 352 ngpios = <4>; 353 interrupt-controller; 354 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 355 }; 356 357 pwm: pwm@31000 { 358 compatible = "brcm,iproc-pwm"; 359 reg = <0x31000 0x28>; 360 clocks = <&osc>; 361 #pwm-cells = <3>; 362 status = "disabled"; 363 }; 364 365 rng: rng@33000 { 366 compatible = "brcm,bcm-nsp-rng"; 367 reg = <0x33000 0x14>; 368 }; 369 370 ccbtimer0: timer@34000 { 371 compatible = "arm,sp804", "arm,primecell"; 372 reg = <0x34000 0x1000>; 373 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>, 374 <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; 375 clocks = <&iprocslow>; 376 clock-names = "apb_pclk"; 377 }; 378 379 ccbtimer1: timer@35000 { 380 compatible = "arm,sp804", "arm,primecell"; 381 reg = <0x35000 0x1000>; 382 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, 383 <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; 384 clocks = <&iprocslow>; 385 clock-names = "apb_pclk"; 386 }; 387 388 srab: srab@36000 { 389 compatible = "brcm,nsp-srab"; 390 reg = <0x36000 0x1000>, 391 <0x3f308 0x8>, 392 <0x3f410 0xc>; 393 reg-names = "srab", "mux_config", "sgmii"; 394 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, 395 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 396 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 397 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 398 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 399 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 400 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 401 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 402 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 403 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 404 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 405 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 406 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 407 interrupt-names = "link_state_p0", 408 "link_state_p1", 409 "link_state_p2", 410 "link_state_p3", 411 "link_state_p4", 412 "link_state_p5", 413 "link_state_p7", 414 "link_state_p8", 415 "phy", 416 "ts", 417 "imp_sleep_timer_p5", 418 "imp_sleep_timer_p7", 419 "imp_sleep_timer_p8"; 420 status = "disabled"; 421 422 /* ports are defined in board DTS */ 423 }; 424 425 i2c0: i2c@38000 { 426 compatible = "brcm,iproc-i2c"; 427 reg = <0x38000 0x50>; 428 #address-cells = <1>; 429 #size-cells = <0>; 430 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 431 clock-frequency = <100000>; 432 dma-coherent; 433 status = "disabled"; 434 }; 435 436 watchdog@39000 { 437 compatible = "arm,sp805", "arm,primecell"; 438 reg = <0x39000 0x1000>; 439 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>; 440 clocks = <&iprocslow>, <&iprocslow>; 441 clock-names = "wdog_clk", "apb_pclk"; 442 }; 443 444 lcpll0: lcpll0@3f100 { 445 #clock-cells = <1>; 446 compatible = "brcm,nsp-lcpll0"; 447 reg = <0x3f100 0x14>; 448 clocks = <&osc>; 449 clock-output-names = "lcpll0", "pcie_phy", "sdio", 450 "ddr_phy"; 451 }; 452 453 genpll: genpll@3f140 { 454 #clock-cells = <1>; 455 compatible = "brcm,nsp-genpll"; 456 reg = <0x3f140 0x24>; 457 clocks = <&osc>; 458 clock-output-names = "genpll", "phy", "ethernetclk", 459 "usbclk", "iprocfast", "sata1", 460 "sata2"; 461 }; 462 463 pinctrl: pinctrl@3f1c0 { 464 compatible = "brcm,nsp-pinmux"; 465 reg = <0x3f1c0 0x04>, 466 <0x30028 0x04>, 467 <0x3f408 0x04>; 468 }; 469 470 thermal: thermal@3f2c0 { 471 compatible = "brcm,ns-thermal"; 472 reg = <0x3f2c0 0x10>; 473 #thermal-sensor-cells = <0>; 474 }; 475 476 sata_phy: sata_phy@40100 { 477 compatible = "brcm,iproc-nsp-sata-phy"; 478 reg = <0x40100 0x340>; 479 reg-names = "phy"; 480 #address-cells = <1>; 481 #size-cells = <0>; 482 483 sata_phy0: sata-phy@0 { 484 reg = <0>; 485 #phy-cells = <0>; 486 status = "disabled"; 487 }; 488 489 sata_phy1: sata-phy@1 { 490 reg = <1>; 491 #phy-cells = <0>; 492 status = "disabled"; 493 }; 494 }; 495 496 sata: ahci@41000 { 497 compatible = "brcm,bcm-nsp-ahci"; 498 reg-names = "ahci", "top-ctrl"; 499 reg = <0x41000 0x1000>, <0x40020 0x1c>; 500 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 501 #address-cells = <1>; 502 #size-cells = <0>; 503 dma-coherent; 504 status = "disabled"; 505 506 sata0: sata-port@0 { 507 reg = <0>; 508 phys = <&sata_phy0>; 509 phy-names = "sata-phy"; 510 }; 511 512 sata1: sata-port@1 { 513 reg = <1>; 514 phys = <&sata_phy1>; 515 phy-names = "sata-phy"; 516 }; 517 }; 518 519 usb3_phy: usb3-phy@104000 { 520 compatible = "brcm,ns-bx-usb3-phy"; 521 reg = <0x104000 0x1000>, 522 <0x032000 0x1000>; 523 reg-names = "dmp", "ccb-mii"; 524 #phy-cells = <0>; 525 status = "disabled"; 526 }; 527 }; 528 529 pcie0: pcie@18012000 { 530 compatible = "brcm,iproc-pcie"; 531 reg = <0x18012000 0x1000>; 532 533 #interrupt-cells = <1>; 534 interrupt-map-mask = <0 0 0 0>; 535 interrupt-map = <0 0 0 0 &gic GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>; 536 537 linux,pci-domain = <0>; 538 539 bus-range = <0x00 0xff>; 540 541 #address-cells = <3>; 542 #size-cells = <2>; 543 device_type = "pci"; 544 545 /* Note: The HW does not support I/O resources. So, 546 * only the memory resource range is being specified. 547 */ 548 ranges = <0x82000000 0 0x08000000 0x08000000 0 0x8000000>; 549 550 dma-coherent; 551 status = "disabled"; 552 553 msi-parent = <&msi0>; 554 msi0: msi-controller { 555 compatible = "brcm,iproc-msi"; 556 msi-controller; 557 interrupt-parent = <&gic>; 558 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>, 559 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, 560 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, 561 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>; 562 brcm,pcie-msi-inten; 563 }; 564 }; 565 566 pcie1: pcie@18013000 { 567 compatible = "brcm,iproc-pcie"; 568 reg = <0x18013000 0x1000>; 569 570 #interrupt-cells = <1>; 571 interrupt-map-mask = <0 0 0 0>; 572 interrupt-map = <0 0 0 0 &gic GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>; 573 574 linux,pci-domain = <1>; 575 576 bus-range = <0x00 0xff>; 577 578 #address-cells = <3>; 579 #size-cells = <2>; 580 device_type = "pci"; 581 582 /* Note: The HW does not support I/O resources. So, 583 * only the memory resource range is being specified. 584 */ 585 ranges = <0x82000000 0 0x40000000 0x40000000 0 0x8000000>; 586 587 dma-coherent; 588 status = "disabled"; 589 590 msi-parent = <&msi1>; 591 msi1: msi-controller { 592 compatible = "brcm,iproc-msi"; 593 msi-controller; 594 interrupt-parent = <&gic>; 595 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 596 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, 597 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 598 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; 599 brcm,pcie-msi-inten; 600 }; 601 }; 602 603 pcie2: pcie@18014000 { 604 compatible = "brcm,iproc-pcie"; 605 reg = <0x18014000 0x1000>; 606 607 #interrupt-cells = <1>; 608 interrupt-map-mask = <0 0 0 0>; 609 interrupt-map = <0 0 0 0 &gic GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 610 611 linux,pci-domain = <2>; 612 613 bus-range = <0x00 0xff>; 614 615 #address-cells = <3>; 616 #size-cells = <2>; 617 device_type = "pci"; 618 619 /* Note: The HW does not support I/O resources. So, 620 * only the memory resource range is being specified. 621 */ 622 ranges = <0x82000000 0 0x48000000 0x48000000 0 0x8000000>; 623 624 dma-coherent; 625 status = "disabled"; 626 627 msi-parent = <&msi2>; 628 msi2: msi-controller { 629 compatible = "brcm,iproc-msi"; 630 msi-controller; 631 interrupt-parent = <&gic>; 632 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>, 633 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, 634 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 635 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>; 636 brcm,pcie-msi-inten; 637 }; 638 }; 639 640 thermal-zones { 641 cpu-thermal { 642 polling-delay-passive = <0>; 643 polling-delay = <1000>; 644 coefficients = <(-556) 418000>; 645 thermal-sensors = <&thermal>; 646 647 trips { 648 cpu-crit { 649 temperature = <125000>; 650 hysteresis = <0>; 651 type = "critical"; 652 }; 653 }; 654 655 cooling-maps { 656 }; 657 }; 658 }; 659}; 660
