1 /* 2 * Copyright (C) 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included 12 * in all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN 18 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 19 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 20 */ 21 #ifndef _athub_2_1_0_SH_MASK_HEADER 22 #define _athub_2_1_0_SH_MASK_HEADER 23 24 25 // addressBlock: athub_atsdec 26 //ATHUB_ATS_MODE_CNTL 27 #define ATHUB_ATS_MODE_CNTL__HOST_TRANS_ENABLE__SHIFT 0x0 28 #define ATHUB_ATS_MODE_CNTL__CONSOLE_IOV_ENABLE__SHIFT 0x1 29 #define ATHUB_ATS_MODE_CNTL__HOST_TRANS_ENABLE_MASK 0x00000001L 30 #define ATHUB_ATS_MODE_CNTL__CONSOLE_IOV_ENABLE_MASK 0x00000002L 31 //ATHUB_SHARED_VIRT_RESET_REQ 32 #define ATHUB_SHARED_VIRT_RESET_REQ__VF__SHIFT 0x0 33 #define ATHUB_SHARED_VIRT_RESET_REQ__PF__SHIFT 0x1f 34 #define ATHUB_SHARED_VIRT_RESET_REQ__VF_MASK 0x7FFFFFFFL 35 #define ATHUB_SHARED_VIRT_RESET_REQ__PF_MASK 0x80000000L 36 //ATHUB_SHARED_ACTIVE_FCN_ID 37 #define ATHUB_SHARED_ACTIVE_FCN_ID__VFID__SHIFT 0x0 38 #define ATHUB_SHARED_ACTIVE_FCN_ID__VF__SHIFT 0x1f 39 #define ATHUB_SHARED_ACTIVE_FCN_ID__VFID_MASK 0x0000001FL 40 #define ATHUB_SHARED_ACTIVE_FCN_ID__VF_MASK 0x80000000L 41 //ATC_ATS_CNTL 42 #define ATC_ATS_CNTL__DISABLE_ATC__SHIFT 0x0 43 #define ATC_ATS_CNTL__DISABLE_PRI__SHIFT 0x1 44 #define ATC_ATS_CNTL__DISABLE_PASID__SHIFT 0x2 45 #define ATC_ATS_CNTL__CREDITS_ATS_RPB__SHIFT 0x8 46 #define ATC_ATS_CNTL__INVALIDATION_LOG_KEEP_ORDER__SHIFT 0x14 47 #define ATC_ATS_CNTL__TRANS_LOG_KEEP_ORDER__SHIFT 0x15 48 #define ATC_ATS_CNTL__TRANS_EXE_RETURN__SHIFT 0x16 49 #define ATC_ATS_CNTL__GUEST_TRANS_MISS_MODE__SHIFT 0x18 50 #define ATC_ATS_CNTL__KEEP_VMID_BUSY_BY_INTR__SHIFT 0x19 51 #define ATC_ATS_CNTL__DISABLE_ATC_MASK 0x00000001L 52 #define ATC_ATS_CNTL__DISABLE_PRI_MASK 0x00000002L 53 #define ATC_ATS_CNTL__DISABLE_PASID_MASK 0x00000004L 54 #define ATC_ATS_CNTL__CREDITS_ATS_RPB_MASK 0x00003F00L 55 #define ATC_ATS_CNTL__INVALIDATION_LOG_KEEP_ORDER_MASK 0x00100000L 56 #define ATC_ATS_CNTL__TRANS_LOG_KEEP_ORDER_MASK 0x00200000L 57 #define ATC_ATS_CNTL__TRANS_EXE_RETURN_MASK 0x00C00000L 58 #define ATC_ATS_CNTL__GUEST_TRANS_MISS_MODE_MASK 0x01000000L 59 #define ATC_ATS_CNTL__KEEP_VMID_BUSY_BY_INTR_MASK 0x02000000L 60 //ATC_ATS_FAULT_CNTL 61 #define ATC_ATS_FAULT_CNTL__FAULT_REGISTER_LOG__SHIFT 0x0 62 #define ATC_ATS_FAULT_CNTL__FAULT_INTERRUPT_TABLE__SHIFT 0xa 63 #define ATC_ATS_FAULT_CNTL__FAULT_CRASH_TABLE__SHIFT 0x14 64 #define ATC_ATS_FAULT_CNTL__FAULT_REGISTER_LOG_MASK 0x000001FFL 65 #define ATC_ATS_FAULT_CNTL__FAULT_INTERRUPT_TABLE_MASK 0x0007FC00L 66 #define ATC_ATS_FAULT_CNTL__FAULT_CRASH_TABLE_MASK 0x1FF00000L 67 //ATC_ATS_DEFAULT_PAGE_LOW 68 #define ATC_ATS_DEFAULT_PAGE_LOW__DEFAULT_PAGE__SHIFT 0x0 69 #define ATC_ATS_DEFAULT_PAGE_LOW__DEFAULT_PAGE_MASK 0xFFFFFFFFL 70 //ATC_TRANS_FAULT_RSPCNTRL 71 #define ATC_TRANS_FAULT_RSPCNTRL__VMID0__SHIFT 0x0 72 #define ATC_TRANS_FAULT_RSPCNTRL__VMID1__SHIFT 0x1 73 #define ATC_TRANS_FAULT_RSPCNTRL__VMID2__SHIFT 0x2 74 #define ATC_TRANS_FAULT_RSPCNTRL__VMID3__SHIFT 0x3 75 #define ATC_TRANS_FAULT_RSPCNTRL__VMID4__SHIFT 0x4 76 #define ATC_TRANS_FAULT_RSPCNTRL__VMID5__SHIFT 0x5 77 #define ATC_TRANS_FAULT_RSPCNTRL__VMID6__SHIFT 0x6 78 #define ATC_TRANS_FAULT_RSPCNTRL__VMID7__SHIFT 0x7 79 #define ATC_TRANS_FAULT_RSPCNTRL__VMID8__SHIFT 0x8 80 #define ATC_TRANS_FAULT_RSPCNTRL__VMID9__SHIFT 0x9 81 #define ATC_TRANS_FAULT_RSPCNTRL__VMID10__SHIFT 0xa 82 #define ATC_TRANS_FAULT_RSPCNTRL__VMID11__SHIFT 0xb 83 #define ATC_TRANS_FAULT_RSPCNTRL__VMID12__SHIFT 0xc 84 #define ATC_TRANS_FAULT_RSPCNTRL__VMID13__SHIFT 0xd 85 #define ATC_TRANS_FAULT_RSPCNTRL__VMID14__SHIFT 0xe 86 #define ATC_TRANS_FAULT_RSPCNTRL__VMID15__SHIFT 0xf 87 #define ATC_TRANS_FAULT_RSPCNTRL__VMID16__SHIFT 0x10 88 #define ATC_TRANS_FAULT_RSPCNTRL__VMID17__SHIFT 0x11 89 #define ATC_TRANS_FAULT_RSPCNTRL__VMID18__SHIFT 0x12 90 #define ATC_TRANS_FAULT_RSPCNTRL__VMID19__SHIFT 0x13 91 #define ATC_TRANS_FAULT_RSPCNTRL__VMID20__SHIFT 0x14 92 #define ATC_TRANS_FAULT_RSPCNTRL__VMID21__SHIFT 0x15 93 #define ATC_TRANS_FAULT_RSPCNTRL__VMID22__SHIFT 0x16 94 #define ATC_TRANS_FAULT_RSPCNTRL__VMID23__SHIFT 0x17 95 #define ATC_TRANS_FAULT_RSPCNTRL__VMID24__SHIFT 0x18 96 #define ATC_TRANS_FAULT_RSPCNTRL__VMID25__SHIFT 0x19 97 #define ATC_TRANS_FAULT_RSPCNTRL__VMID26__SHIFT 0x1a 98 #define ATC_TRANS_FAULT_RSPCNTRL__VMID27__SHIFT 0x1b 99 #define ATC_TRANS_FAULT_RSPCNTRL__VMID28__SHIFT 0x1c 100 #define ATC_TRANS_FAULT_RSPCNTRL__VMID29__SHIFT 0x1d 101 #define ATC_TRANS_FAULT_RSPCNTRL__VMID30__SHIFT 0x1e 102 #define ATC_TRANS_FAULT_RSPCNTRL__VMID31__SHIFT 0x1f 103 #define ATC_TRANS_FAULT_RSPCNTRL__VMID0_MASK 0x00000001L 104 #define ATC_TRANS_FAULT_RSPCNTRL__VMID1_MASK 0x00000002L 105 #define ATC_TRANS_FAULT_RSPCNTRL__VMID2_MASK 0x00000004L 106 #define ATC_TRANS_FAULT_RSPCNTRL__VMID3_MASK 0x00000008L 107 #define ATC_TRANS_FAULT_RSPCNTRL__VMID4_MASK 0x00000010L 108 #define ATC_TRANS_FAULT_RSPCNTRL__VMID5_MASK 0x00000020L 109 #define ATC_TRANS_FAULT_RSPCNTRL__VMID6_MASK 0x00000040L 110 #define ATC_TRANS_FAULT_RSPCNTRL__VMID7_MASK 0x00000080L 111 #define ATC_TRANS_FAULT_RSPCNTRL__VMID8_MASK 0x00000100L 112 #define ATC_TRANS_FAULT_RSPCNTRL__VMID9_MASK 0x00000200L 113 #define ATC_TRANS_FAULT_RSPCNTRL__VMID10_MASK 0x00000400L 114 #define ATC_TRANS_FAULT_RSPCNTRL__VMID11_MASK 0x00000800L 115 #define ATC_TRANS_FAULT_RSPCNTRL__VMID12_MASK 0x00001000L 116 #define ATC_TRANS_FAULT_RSPCNTRL__VMID13_MASK 0x00002000L 117 #define ATC_TRANS_FAULT_RSPCNTRL__VMID14_MASK 0x00004000L 118 #define ATC_TRANS_FAULT_RSPCNTRL__VMID15_MASK 0x00008000L 119 #define ATC_TRANS_FAULT_RSPCNTRL__VMID16_MASK 0x00010000L 120 #define ATC_TRANS_FAULT_RSPCNTRL__VMID17_MASK 0x00020000L 121 #define ATC_TRANS_FAULT_RSPCNTRL__VMID18_MASK 0x00040000L 122 #define ATC_TRANS_FAULT_RSPCNTRL__VMID19_MASK 0x00080000L 123 #define ATC_TRANS_FAULT_RSPCNTRL__VMID20_MASK 0x00100000L 124 #define ATC_TRANS_FAULT_RSPCNTRL__VMID21_MASK 0x00200000L 125 #define ATC_TRANS_FAULT_RSPCNTRL__VMID22_MASK 0x00400000L 126 #define ATC_TRANS_FAULT_RSPCNTRL__VMID23_MASK 0x00800000L 127 #define ATC_TRANS_FAULT_RSPCNTRL__VMID24_MASK 0x01000000L 128 #define ATC_TRANS_FAULT_RSPCNTRL__VMID25_MASK 0x02000000L 129 #define ATC_TRANS_FAULT_RSPCNTRL__VMID26_MASK 0x04000000L 130 #define ATC_TRANS_FAULT_RSPCNTRL__VMID27_MASK 0x08000000L 131 #define ATC_TRANS_FAULT_RSPCNTRL__VMID28_MASK 0x10000000L 132 #define ATC_TRANS_FAULT_RSPCNTRL__VMID29_MASK 0x20000000L 133 #define ATC_TRANS_FAULT_RSPCNTRL__VMID30_MASK 0x40000000L 134 #define ATC_TRANS_FAULT_RSPCNTRL__VMID31_MASK 0x80000000L 135 //ATHUB_MISC_CNTL 136 #define ATHUB_MISC_CNTL__CG_OFFDLY__SHIFT 0x0 137 #define ATHUB_MISC_CNTL__CG_ENABLE__SHIFT 0x6 138 #define ATHUB_MISC_CNTL__CG_MEM_LS_ENABLE__SHIFT 0x7 139 #define ATHUB_MISC_CNTL__PG_ENABLE__SHIFT 0x8 140 #define ATHUB_MISC_CNTL__PG_OFFDLY__SHIFT 0x9 141 #define ATHUB_MISC_CNTL__ALWAYS_BUSY__SHIFT 0xf 142 #define ATHUB_MISC_CNTL__CG_STATUS__SHIFT 0x10 143 #define ATHUB_MISC_CNTL__PG_STATUS__SHIFT 0x11 144 #define ATHUB_MISC_CNTL__RPB_BUSY__SHIFT 0x12 145 #define ATHUB_MISC_CNTL__XPB_BUSY__SHIFT 0x13 146 #define ATHUB_MISC_CNTL__ATS_BUSY__SHIFT 0x14 147 #define ATHUB_MISC_CNTL__SDPNCS_BUSY__SHIFT 0x15 148 #define ATHUB_MISC_CNTL__DFPORT_BUSY__SHIFT 0x16 149 #define ATHUB_MISC_CNTL__SWITCH_CNTL__SHIFT 0x17 150 #define ATHUB_MISC_CNTL__CG_OFFDLY_MASK 0x0000003FL 151 #define ATHUB_MISC_CNTL__CG_ENABLE_MASK 0x00000040L 152 #define ATHUB_MISC_CNTL__CG_MEM_LS_ENABLE_MASK 0x00000080L 153 #define ATHUB_MISC_CNTL__PG_ENABLE_MASK 0x00000100L 154 #define ATHUB_MISC_CNTL__PG_OFFDLY_MASK 0x00007E00L 155 #define ATHUB_MISC_CNTL__ALWAYS_BUSY_MASK 0x00008000L 156 #define ATHUB_MISC_CNTL__CG_STATUS_MASK 0x00010000L 157 #define ATHUB_MISC_CNTL__PG_STATUS_MASK 0x00020000L 158 #define ATHUB_MISC_CNTL__RPB_BUSY_MASK 0x00040000L 159 #define ATHUB_MISC_CNTL__XPB_BUSY_MASK 0x00080000L 160 #define ATHUB_MISC_CNTL__ATS_BUSY_MASK 0x00100000L 161 #define ATHUB_MISC_CNTL__SDPNCS_BUSY_MASK 0x00200000L 162 #define ATHUB_MISC_CNTL__DFPORT_BUSY_MASK 0x00400000L 163 #define ATHUB_MISC_CNTL__SWITCH_CNTL_MASK 0x00800000L 164 //ATHUB_MEM_POWER_LS 165 #define ATHUB_MEM_POWER_LS__LS_SETUP__SHIFT 0x0 166 #define ATHUB_MEM_POWER_LS__LS_HOLD__SHIFT 0x6 167 #define ATHUB_MEM_POWER_LS__LS_SETUP_MASK 0x0000003FL 168 #define ATHUB_MEM_POWER_LS__LS_HOLD_MASK 0x00000FC0L 169 //ATC_ATS_SDPPORT_CNTL 170 #define ATC_ATS_SDPPORT_CNTL__ATS_INV_SELF_ACTIVATE__SHIFT 0x0 171 #define ATC_ATS_SDPPORT_CNTL__ATS_INV_CFG_MODE__SHIFT 0x1 172 #define ATC_ATS_SDPPORT_CNTL__ATS_INV_HALT_THRESHOLD__SHIFT 0x3 173 #define ATC_ATS_SDPPORT_CNTL__UTCL2_TRANS_SELF_ACTIVATE__SHIFT 0x7 174 #define ATC_ATS_SDPPORT_CNTL__UTCL2_TRANS_QUICK_COMACK__SHIFT 0x8 175 #define ATC_ATS_SDPPORT_CNTL__UTCL2_TRANS_HALT_THRESHOLD__SHIFT 0x9 176 #define ATC_ATS_SDPPORT_CNTL__UTCL2_TRANS_PASSIVE_MODE__SHIFT 0xd 177 #define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_RDY_MODE__SHIFT 0xe 178 #define ATC_ATS_SDPPORT_CNTL__UTCL2_MMHUB_RDY_MODE__SHIFT 0xf 179 #define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_RDRSPCKEN__SHIFT 0x10 180 #define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_RDRSPCKENRCV__SHIFT 0x11 181 #define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_RDRSPDATACKEN__SHIFT 0x12 182 #define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_RDRSPDATACKENRCV__SHIFT 0x13 183 #define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_WRRSPCKEN__SHIFT 0x14 184 #define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_WRRSPCKENRCV__SHIFT 0x15 185 #define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_REQCKEN__SHIFT 0x16 186 #define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_REQCKENRCV__SHIFT 0x17 187 #define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_ORIGDATACKEN__SHIFT 0x18 188 #define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_ORIGDATACKENRCV__SHIFT 0x19 189 #define ATC_ATS_SDPPORT_CNTL__ATS_INV_SELF_ACTIVATE_MASK 0x00000001L 190 #define ATC_ATS_SDPPORT_CNTL__ATS_INV_CFG_MODE_MASK 0x00000006L 191 #define ATC_ATS_SDPPORT_CNTL__ATS_INV_HALT_THRESHOLD_MASK 0x00000078L 192 #define ATC_ATS_SDPPORT_CNTL__UTCL2_TRANS_SELF_ACTIVATE_MASK 0x00000080L 193 #define ATC_ATS_SDPPORT_CNTL__UTCL2_TRANS_QUICK_COMACK_MASK 0x00000100L 194 #define ATC_ATS_SDPPORT_CNTL__UTCL2_TRANS_HALT_THRESHOLD_MASK 0x00001E00L 195 #define ATC_ATS_SDPPORT_CNTL__UTCL2_TRANS_PASSIVE_MODE_MASK 0x00002000L 196 #define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_RDY_MODE_MASK 0x00004000L 197 #define ATC_ATS_SDPPORT_CNTL__UTCL2_MMHUB_RDY_MODE_MASK 0x00008000L 198 #define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_RDRSPCKEN_MASK 0x00010000L 199 #define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_RDRSPCKENRCV_MASK 0x00020000L 200 #define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_RDRSPDATACKEN_MASK 0x00040000L 201 #define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_RDRSPDATACKENRCV_MASK 0x00080000L 202 #define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_WRRSPCKEN_MASK 0x00100000L 203 #define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_WRRSPCKENRCV_MASK 0x00200000L 204 #define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_REQCKEN_MASK 0x00400000L 205 #define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_REQCKENRCV_MASK 0x00800000L 206 #define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_ORIGDATACKEN_MASK 0x01000000L 207 #define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_ORIGDATACKENRCV_MASK 0x02000000L 208 //ATC_ATS_CNTL2 209 #define ATC_ATS_CNTL2__CREDITS_ATS_RPB_MMTR__SHIFT 0x0 210 #define ATC_ATS_CNTL2__CREDITS_ATS_RPB_GFXTR__SHIFT 0x8 211 #define ATC_ATS_CNTL2__CREDITS_ATS_RPB_PRINV__SHIFT 0x10 212 #define ATC_ATS_CNTL2__TRANSLATION_STALL__SHIFT 0x18 213 #define ATC_ATS_CNTL2__INV_PASID_CONSOLE_IOV__SHIFT 0x19 214 #define ATC_ATS_CNTL2__GC_MM_TRANS_SWITCH__SHIFT 0x1a 215 #define ATC_ATS_CNTL2__GC_TRANS_CONTROL__SHIFT 0x1b 216 #define ATC_ATS_CNTL2__MM_TRANS_CONTROL__SHIFT 0x1c 217 #define ATC_ATS_CNTL2__RESERVED__SHIFT 0x1d 218 #define ATC_ATS_CNTL2__CREDITS_ATS_RPB_MMTR_MASK 0x000000FFL 219 #define ATC_ATS_CNTL2__CREDITS_ATS_RPB_GFXTR_MASK 0x0000FF00L 220 #define ATC_ATS_CNTL2__CREDITS_ATS_RPB_PRINV_MASK 0x00FF0000L 221 #define ATC_ATS_CNTL2__TRANSLATION_STALL_MASK 0x01000000L 222 #define ATC_ATS_CNTL2__INV_PASID_CONSOLE_IOV_MASK 0x02000000L 223 #define ATC_ATS_CNTL2__GC_MM_TRANS_SWITCH_MASK 0x04000000L 224 #define ATC_ATS_CNTL2__GC_TRANS_CONTROL_MASK 0x08000000L 225 #define ATC_ATS_CNTL2__MM_TRANS_CONTROL_MASK 0x10000000L 226 #define ATC_ATS_CNTL2__RESERVED_MASK 0xE0000000L 227 //ATC_ATS_TR_QOS_CNTL 228 #define ATC_ATS_TR_QOS_CNTL__MM_TR_WQ_CREDITS__SHIFT 0x0 229 #define ATC_ATS_TR_QOS_CNTL__GFX_TR_WQ_CREDITS__SHIFT 0x8 230 #define ATC_ATS_TR_QOS_CNTL__GFX_MM_TR_ARB_MODE_AGGR__SHIFT 0x10 231 #define ATC_ATS_TR_QOS_CNTL__GFX_MM_TR_RATIO_AGGR__SHIFT 0x12 232 #define ATC_ATS_TR_QOS_CNTL__GFX_MM_TR_ARB_MODE_WQ__SHIFT 0x18 233 #define ATC_ATS_TR_QOS_CNTL__GFX_MM_TR_RATIO_WQ__SHIFT 0x1a 234 #define ATC_ATS_TR_QOS_CNTL__MM_TR_WQ_CREDITS_MASK 0x000000FFL 235 #define ATC_ATS_TR_QOS_CNTL__GFX_TR_WQ_CREDITS_MASK 0x0000FF00L 236 #define ATC_ATS_TR_QOS_CNTL__GFX_MM_TR_ARB_MODE_AGGR_MASK 0x00030000L 237 #define ATC_ATS_TR_QOS_CNTL__GFX_MM_TR_RATIO_AGGR_MASK 0x00FC0000L 238 #define ATC_ATS_TR_QOS_CNTL__GFX_MM_TR_ARB_MODE_WQ_MASK 0x03000000L 239 #define ATC_ATS_TR_QOS_CNTL__GFX_MM_TR_RATIO_WQ_MASK 0xFC000000L 240 //ATC_ATS_MISC_CNTL 241 #define ATC_ATS_MISC_CNTL__MM_32K_GROUPING_EN_HOST__SHIFT 0x0 242 #define ATC_ATS_MISC_CNTL__GFX_32K_GROUPING_EN_HOST__SHIFT 0x1 243 #define ATC_ATS_MISC_CNTL__MM_32K_GROUPING_EN_GUEST__SHIFT 0x2 244 #define ATC_ATS_MISC_CNTL__GFX_32K_GROUPING_EN_GUEST__SHIFT 0x3 245 #define ATC_ATS_MISC_CNTL__RESERVED__SHIFT 0x4 246 #define ATC_ATS_MISC_CNTL__MM_32K_GROUPING_EN_HOST_MASK 0x00000001L 247 #define ATC_ATS_MISC_CNTL__GFX_32K_GROUPING_EN_HOST_MASK 0x00000002L 248 #define ATC_ATS_MISC_CNTL__MM_32K_GROUPING_EN_GUEST_MASK 0x00000004L 249 #define ATC_ATS_MISC_CNTL__GFX_32K_GROUPING_EN_GUEST_MASK 0x00000008L 250 #define ATC_ATS_MISC_CNTL__RESERVED_MASK 0xFFFFFFF0L 251 //ATC_PERFCOUNTER0_CFG 252 #define ATC_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 253 #define ATC_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 254 #define ATC_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 255 #define ATC_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c 256 #define ATC_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d 257 #define ATC_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL 258 #define ATC_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L 259 #define ATC_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L 260 #define ATC_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L 261 #define ATC_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L 262 //ATC_PERFCOUNTER1_CFG 263 #define ATC_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 264 #define ATC_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 265 #define ATC_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 266 #define ATC_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c 267 #define ATC_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d 268 #define ATC_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL 269 #define ATC_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L 270 #define ATC_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L 271 #define ATC_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L 272 #define ATC_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L 273 //ATC_PERFCOUNTER2_CFG 274 #define ATC_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0 275 #define ATC_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8 276 #define ATC_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18 277 #define ATC_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c 278 #define ATC_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d 279 #define ATC_PERFCOUNTER2_CFG__PERF_SEL_MASK 0x000000FFL 280 #define ATC_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0x0000FF00L 281 #define ATC_PERFCOUNTER2_CFG__PERF_MODE_MASK 0x0F000000L 282 #define ATC_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000L 283 #define ATC_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000L 284 //ATC_PERFCOUNTER3_CFG 285 #define ATC_PERFCOUNTER3_CFG__PERF_SEL__SHIFT 0x0 286 #define ATC_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT 0x8 287 #define ATC_PERFCOUNTER3_CFG__PERF_MODE__SHIFT 0x18 288 #define ATC_PERFCOUNTER3_CFG__ENABLE__SHIFT 0x1c 289 #define ATC_PERFCOUNTER3_CFG__CLEAR__SHIFT 0x1d 290 #define ATC_PERFCOUNTER3_CFG__PERF_SEL_MASK 0x000000FFL 291 #define ATC_PERFCOUNTER3_CFG__PERF_SEL_END_MASK 0x0000FF00L 292 #define ATC_PERFCOUNTER3_CFG__PERF_MODE_MASK 0x0F000000L 293 #define ATC_PERFCOUNTER3_CFG__ENABLE_MASK 0x10000000L 294 #define ATC_PERFCOUNTER3_CFG__CLEAR_MASK 0x20000000L 295 //ATC_PERFCOUNTER_RSLT_CNTL 296 #define ATC_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 297 #define ATC_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 298 #define ATC_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 299 #define ATC_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 300 #define ATC_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 301 #define ATC_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a 302 #define ATC_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL 303 #define ATC_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L 304 #define ATC_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L 305 #define ATC_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L 306 #define ATC_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L 307 #define ATC_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L 308 //ATC_PERFCOUNTER_LO 309 #define ATC_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 310 #define ATC_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL 311 //ATC_PERFCOUNTER_HI 312 #define ATC_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 313 #define ATC_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 314 #define ATC_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL 315 #define ATC_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L 316 //ATS_IH_CREDIT 317 #define ATS_IH_CREDIT__CREDIT_VALUE__SHIFT 0x0 318 #define ATS_IH_CREDIT__IH_CLIENT_ID__SHIFT 0x10 319 #define ATS_IH_CREDIT__CREDIT_VALUE_MASK 0x00000003L 320 #define ATS_IH_CREDIT__IH_CLIENT_ID_MASK 0x00FF0000L 321 //ATHUB_IH_CREDIT 322 #define ATHUB_IH_CREDIT__CREDIT_VALUE__SHIFT 0x0 323 #define ATHUB_IH_CREDIT__IH_CLIENT_ID__SHIFT 0x10 324 #define ATHUB_IH_CREDIT__CREDIT_VALUE_MASK 0x00000003L 325 #define ATHUB_IH_CREDIT__IH_CLIENT_ID_MASK 0x00FF0000L 326 //ATC_ATS_GFX_ATCL2_STATUS 327 #define ATC_ATS_GFX_ATCL2_STATUS__POWERED_DOWN__SHIFT 0x0 328 #define ATC_ATS_GFX_ATCL2_STATUS__POWERED_DOWN_MASK 0x00000001L 329 //ATC_ATS_MMHUB_ATCL2_STATUS 330 #define ATC_ATS_MMHUB_ATCL2_STATUS__POWERED_DOWN__SHIFT 0x0 331 #define ATC_ATS_MMHUB_ATCL2_STATUS__POWERED_DOWN_MASK 0x00000001L 332 //ATC_ATS_FAULT_STATUS_INFO 333 #define ATC_ATS_FAULT_STATUS_INFO__FAULT_TYPE__SHIFT 0x0 334 #define ATC_ATS_FAULT_STATUS_INFO__VMID__SHIFT 0xa 335 #define ATC_ATS_FAULT_STATUS_INFO__EXTRA_INFO__SHIFT 0xf 336 #define ATC_ATS_FAULT_STATUS_INFO__EXTRA_INFO2__SHIFT 0x10 337 #define ATC_ATS_FAULT_STATUS_INFO__INVALIDATION__SHIFT 0x11 338 #define ATC_ATS_FAULT_STATUS_INFO__PAGE_REQUEST__SHIFT 0x12 339 #define ATC_ATS_FAULT_STATUS_INFO__STATUS__SHIFT 0x13 340 #define ATC_ATS_FAULT_STATUS_INFO__PAGE_ADDR_HIGH__SHIFT 0x18 341 #define ATC_ATS_FAULT_STATUS_INFO__FAULT_TYPE_MASK 0x000001FFL 342 #define ATC_ATS_FAULT_STATUS_INFO__VMID_MASK 0x00007C00L 343 #define ATC_ATS_FAULT_STATUS_INFO__EXTRA_INFO_MASK 0x00008000L 344 #define ATC_ATS_FAULT_STATUS_INFO__EXTRA_INFO2_MASK 0x00010000L 345 #define ATC_ATS_FAULT_STATUS_INFO__INVALIDATION_MASK 0x00020000L 346 #define ATC_ATS_FAULT_STATUS_INFO__PAGE_REQUEST_MASK 0x00040000L 347 #define ATC_ATS_FAULT_STATUS_INFO__STATUS_MASK 0x00F80000L 348 #define ATC_ATS_FAULT_STATUS_INFO__PAGE_ADDR_HIGH_MASK 0x0F000000L 349 //ATC_ATS_FAULT_STATUS_ADDR 350 #define ATC_ATS_FAULT_STATUS_ADDR__PAGE_ADDR__SHIFT 0x0 351 #define ATC_ATS_FAULT_STATUS_ADDR__PAGE_ADDR_MASK 0xFFFFFFFFL 352 //ATC_ATS_FAULT_STATUS_INFO2 353 #define ATC_ATS_FAULT_STATUS_INFO2__VF__SHIFT 0x0 354 #define ATC_ATS_FAULT_STATUS_INFO2__VFID__SHIFT 0x1 355 #define ATC_ATS_FAULT_STATUS_INFO2__MMHUB_INV_VMID__SHIFT 0x9 356 #define ATC_ATS_FAULT_STATUS_INFO2__VF_MASK 0x00000001L 357 #define ATC_ATS_FAULT_STATUS_INFO2__VFID_MASK 0x0000003EL 358 #define ATC_ATS_FAULT_STATUS_INFO2__MMHUB_INV_VMID_MASK 0x00003E00L 359 //ATHUB_PCIE_ATS_CNTL 360 #define ATHUB_PCIE_ATS_CNTL__STU__SHIFT 0x10 361 #define ATHUB_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0x1f 362 #define ATHUB_PCIE_ATS_CNTL__STU_MASK 0x001F0000L 363 #define ATHUB_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x80000000L 364 //ATHUB_PCIE_PASID_CNTL 365 #define ATHUB_PCIE_PASID_CNTL__PASID_EN__SHIFT 0x10 366 #define ATHUB_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE__SHIFT 0x11 367 #define ATHUB_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE__SHIFT 0x12 368 #define ATHUB_PCIE_PASID_CNTL__PASID_EN_MASK 0x00010000L 369 #define ATHUB_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE_MASK 0x00020000L 370 #define ATHUB_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE_MASK 0x00040000L 371 //ATHUB_PCIE_PAGE_REQ_CNTL 372 #define ATHUB_PCIE_PAGE_REQ_CNTL__PRI_ENABLE__SHIFT 0x0 373 #define ATHUB_PCIE_PAGE_REQ_CNTL__PRI_RESET__SHIFT 0x1 374 #define ATHUB_PCIE_PAGE_REQ_CNTL__PRI_ENABLE_MASK 0x00000001L 375 #define ATHUB_PCIE_PAGE_REQ_CNTL__PRI_RESET_MASK 0x00000002L 376 //ATHUB_PCIE_OUTSTAND_PAGE_REQ_ALLOC 377 #define ATHUB_PCIE_OUTSTAND_PAGE_REQ_ALLOC__OUTSTAND_PAGE_REQ_ALLOC__SHIFT 0x0 378 #define ATHUB_PCIE_OUTSTAND_PAGE_REQ_ALLOC__OUTSTAND_PAGE_REQ_ALLOC_MASK 0xFFFFFFFFL 379 //ATHUB_COMMAND 380 #define ATHUB_COMMAND__BUS_MASTER_EN__SHIFT 0x2 381 #define ATHUB_COMMAND__BUS_MASTER_EN_MASK 0x00000004L 382 //ATHUB_PCIE_ATS_CNTL_VF_0 383 #define ATHUB_PCIE_ATS_CNTL_VF_0__ATC_ENABLE__SHIFT 0x1f 384 #define ATHUB_PCIE_ATS_CNTL_VF_0__ATC_ENABLE_MASK 0x80000000L 385 //ATHUB_PCIE_ATS_CNTL_VF_1 386 #define ATHUB_PCIE_ATS_CNTL_VF_1__ATC_ENABLE__SHIFT 0x1f 387 #define ATHUB_PCIE_ATS_CNTL_VF_1__ATC_ENABLE_MASK 0x80000000L 388 //ATHUB_PCIE_ATS_CNTL_VF_2 389 #define ATHUB_PCIE_ATS_CNTL_VF_2__ATC_ENABLE__SHIFT 0x1f 390 #define ATHUB_PCIE_ATS_CNTL_VF_2__ATC_ENABLE_MASK 0x80000000L 391 //ATHUB_PCIE_ATS_CNTL_VF_3 392 #define ATHUB_PCIE_ATS_CNTL_VF_3__ATC_ENABLE__SHIFT 0x1f 393 #define ATHUB_PCIE_ATS_CNTL_VF_3__ATC_ENABLE_MASK 0x80000000L 394 //ATHUB_PCIE_ATS_CNTL_VF_4 395 #define ATHUB_PCIE_ATS_CNTL_VF_4__ATC_ENABLE__SHIFT 0x1f 396 #define ATHUB_PCIE_ATS_CNTL_VF_4__ATC_ENABLE_MASK 0x80000000L 397 //ATHUB_PCIE_ATS_CNTL_VF_5 398 #define ATHUB_PCIE_ATS_CNTL_VF_5__ATC_ENABLE__SHIFT 0x1f 399 #define ATHUB_PCIE_ATS_CNTL_VF_5__ATC_ENABLE_MASK 0x80000000L 400 //ATHUB_PCIE_ATS_CNTL_VF_6 401 #define ATHUB_PCIE_ATS_CNTL_VF_6__ATC_ENABLE__SHIFT 0x1f 402 #define ATHUB_PCIE_ATS_CNTL_VF_6__ATC_ENABLE_MASK 0x80000000L 403 //ATHUB_PCIE_ATS_CNTL_VF_7 404 #define ATHUB_PCIE_ATS_CNTL_VF_7__ATC_ENABLE__SHIFT 0x1f 405 #define ATHUB_PCIE_ATS_CNTL_VF_7__ATC_ENABLE_MASK 0x80000000L 406 //ATHUB_PCIE_ATS_CNTL_VF_8 407 #define ATHUB_PCIE_ATS_CNTL_VF_8__ATC_ENABLE__SHIFT 0x1f 408 #define ATHUB_PCIE_ATS_CNTL_VF_8__ATC_ENABLE_MASK 0x80000000L 409 //ATHUB_PCIE_ATS_CNTL_VF_9 410 #define ATHUB_PCIE_ATS_CNTL_VF_9__ATC_ENABLE__SHIFT 0x1f 411 #define ATHUB_PCIE_ATS_CNTL_VF_9__ATC_ENABLE_MASK 0x80000000L 412 //ATHUB_PCIE_ATS_CNTL_VF_10 413 #define ATHUB_PCIE_ATS_CNTL_VF_10__ATC_ENABLE__SHIFT 0x1f 414 #define ATHUB_PCIE_ATS_CNTL_VF_10__ATC_ENABLE_MASK 0x80000000L 415 //ATHUB_PCIE_ATS_CNTL_VF_11 416 #define ATHUB_PCIE_ATS_CNTL_VF_11__ATC_ENABLE__SHIFT 0x1f 417 #define ATHUB_PCIE_ATS_CNTL_VF_11__ATC_ENABLE_MASK 0x80000000L 418 //ATHUB_PCIE_ATS_CNTL_VF_12 419 #define ATHUB_PCIE_ATS_CNTL_VF_12__ATC_ENABLE__SHIFT 0x1f 420 #define ATHUB_PCIE_ATS_CNTL_VF_12__ATC_ENABLE_MASK 0x80000000L 421 //ATHUB_PCIE_ATS_CNTL_VF_13 422 #define ATHUB_PCIE_ATS_CNTL_VF_13__ATC_ENABLE__SHIFT 0x1f 423 #define ATHUB_PCIE_ATS_CNTL_VF_13__ATC_ENABLE_MASK 0x80000000L 424 //ATHUB_PCIE_ATS_CNTL_VF_14 425 #define ATHUB_PCIE_ATS_CNTL_VF_14__ATC_ENABLE__SHIFT 0x1f 426 #define ATHUB_PCIE_ATS_CNTL_VF_14__ATC_ENABLE_MASK 0x80000000L 427 //ATHUB_PCIE_ATS_CNTL_VF_15 428 #define ATHUB_PCIE_ATS_CNTL_VF_15__ATC_ENABLE__SHIFT 0x1f 429 #define ATHUB_PCIE_ATS_CNTL_VF_15__ATC_ENABLE_MASK 0x80000000L 430 //ATHUB_PCIE_ATS_CNTL_VF_16 431 #define ATHUB_PCIE_ATS_CNTL_VF_16__ATC_ENABLE__SHIFT 0x1f 432 #define ATHUB_PCIE_ATS_CNTL_VF_16__ATC_ENABLE_MASK 0x80000000L 433 //ATHUB_PCIE_ATS_CNTL_VF_17 434 #define ATHUB_PCIE_ATS_CNTL_VF_17__ATC_ENABLE__SHIFT 0x1f 435 #define ATHUB_PCIE_ATS_CNTL_VF_17__ATC_ENABLE_MASK 0x80000000L 436 //ATHUB_PCIE_ATS_CNTL_VF_18 437 #define ATHUB_PCIE_ATS_CNTL_VF_18__ATC_ENABLE__SHIFT 0x1f 438 #define ATHUB_PCIE_ATS_CNTL_VF_18__ATC_ENABLE_MASK 0x80000000L 439 //ATHUB_PCIE_ATS_CNTL_VF_19 440 #define ATHUB_PCIE_ATS_CNTL_VF_19__ATC_ENABLE__SHIFT 0x1f 441 #define ATHUB_PCIE_ATS_CNTL_VF_19__ATC_ENABLE_MASK 0x80000000L 442 //ATHUB_PCIE_ATS_CNTL_VF_20 443 #define ATHUB_PCIE_ATS_CNTL_VF_20__ATC_ENABLE__SHIFT 0x1f 444 #define ATHUB_PCIE_ATS_CNTL_VF_20__ATC_ENABLE_MASK 0x80000000L 445 //ATHUB_PCIE_ATS_CNTL_VF_21 446 #define ATHUB_PCIE_ATS_CNTL_VF_21__ATC_ENABLE__SHIFT 0x1f 447 #define ATHUB_PCIE_ATS_CNTL_VF_21__ATC_ENABLE_MASK 0x80000000L 448 //ATHUB_PCIE_ATS_CNTL_VF_22 449 #define ATHUB_PCIE_ATS_CNTL_VF_22__ATC_ENABLE__SHIFT 0x1f 450 #define ATHUB_PCIE_ATS_CNTL_VF_22__ATC_ENABLE_MASK 0x80000000L 451 //ATHUB_PCIE_ATS_CNTL_VF_23 452 #define ATHUB_PCIE_ATS_CNTL_VF_23__ATC_ENABLE__SHIFT 0x1f 453 #define ATHUB_PCIE_ATS_CNTL_VF_23__ATC_ENABLE_MASK 0x80000000L 454 //ATHUB_PCIE_ATS_CNTL_VF_24 455 #define ATHUB_PCIE_ATS_CNTL_VF_24__ATC_ENABLE__SHIFT 0x1f 456 #define ATHUB_PCIE_ATS_CNTL_VF_24__ATC_ENABLE_MASK 0x80000000L 457 //ATHUB_PCIE_ATS_CNTL_VF_25 458 #define ATHUB_PCIE_ATS_CNTL_VF_25__ATC_ENABLE__SHIFT 0x1f 459 #define ATHUB_PCIE_ATS_CNTL_VF_25__ATC_ENABLE_MASK 0x80000000L 460 //ATHUB_PCIE_ATS_CNTL_VF_26 461 #define ATHUB_PCIE_ATS_CNTL_VF_26__ATC_ENABLE__SHIFT 0x1f 462 #define ATHUB_PCIE_ATS_CNTL_VF_26__ATC_ENABLE_MASK 0x80000000L 463 //ATHUB_PCIE_ATS_CNTL_VF_27 464 #define ATHUB_PCIE_ATS_CNTL_VF_27__ATC_ENABLE__SHIFT 0x1f 465 #define ATHUB_PCIE_ATS_CNTL_VF_27__ATC_ENABLE_MASK 0x80000000L 466 //ATHUB_PCIE_ATS_CNTL_VF_28 467 #define ATHUB_PCIE_ATS_CNTL_VF_28__ATC_ENABLE__SHIFT 0x1f 468 #define ATHUB_PCIE_ATS_CNTL_VF_28__ATC_ENABLE_MASK 0x80000000L 469 //ATHUB_PCIE_ATS_CNTL_VF_29 470 #define ATHUB_PCIE_ATS_CNTL_VF_29__ATC_ENABLE__SHIFT 0x1f 471 #define ATHUB_PCIE_ATS_CNTL_VF_29__ATC_ENABLE_MASK 0x80000000L 472 //ATHUB_PCIE_ATS_CNTL_VF_30 473 #define ATHUB_PCIE_ATS_CNTL_VF_30__ATC_ENABLE__SHIFT 0x1f 474 #define ATHUB_PCIE_ATS_CNTL_VF_30__ATC_ENABLE_MASK 0x80000000L 475 //ATC_VMID_PASID_MAPPING_UPDATE_STATUS 476 #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID0_REMAPPING_FINISHED__SHIFT 0x0 477 #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID1_REMAPPING_FINISHED__SHIFT 0x1 478 #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID2_REMAPPING_FINISHED__SHIFT 0x2 479 #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID3_REMAPPING_FINISHED__SHIFT 0x3 480 #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID4_REMAPPING_FINISHED__SHIFT 0x4 481 #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID5_REMAPPING_FINISHED__SHIFT 0x5 482 #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID6_REMAPPING_FINISHED__SHIFT 0x6 483 #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID7_REMAPPING_FINISHED__SHIFT 0x7 484 #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID8_REMAPPING_FINISHED__SHIFT 0x8 485 #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID9_REMAPPING_FINISHED__SHIFT 0x9 486 #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID10_REMAPPING_FINISHED__SHIFT 0xa 487 #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID11_REMAPPING_FINISHED__SHIFT 0xb 488 #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID12_REMAPPING_FINISHED__SHIFT 0xc 489 #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID13_REMAPPING_FINISHED__SHIFT 0xd 490 #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID14_REMAPPING_FINISHED__SHIFT 0xe 491 #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID15_REMAPPING_FINISHED__SHIFT 0xf 492 #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID16_REMAPPING_FINISHED__SHIFT 0x10 493 #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID17_REMAPPING_FINISHED__SHIFT 0x11 494 #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID18_REMAPPING_FINISHED__SHIFT 0x12 495 #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID19_REMAPPING_FINISHED__SHIFT 0x13 496 #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID20_REMAPPING_FINISHED__SHIFT 0x14 497 #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID21_REMAPPING_FINISHED__SHIFT 0x15 498 #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID22_REMAPPING_FINISHED__SHIFT 0x16 499 #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID23_REMAPPING_FINISHED__SHIFT 0x17 500 #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID24_REMAPPING_FINISHED__SHIFT 0x18 501 #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID25_REMAPPING_FINISHED__SHIFT 0x19 502 #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID26_REMAPPING_FINISHED__SHIFT 0x1a 503 #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID27_REMAPPING_FINISHED__SHIFT 0x1b 504 #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID28_REMAPPING_FINISHED__SHIFT 0x1c 505 #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID29_REMAPPING_FINISHED__SHIFT 0x1d 506 #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID30_REMAPPING_FINISHED__SHIFT 0x1e 507 #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID31_REMAPPING_FINISHED__SHIFT 0x1f 508 #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID0_REMAPPING_FINISHED_MASK 0x00000001L 509 #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID1_REMAPPING_FINISHED_MASK 0x00000002L 510 #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID2_REMAPPING_FINISHED_MASK 0x00000004L 511 #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID3_REMAPPING_FINISHED_MASK 0x00000008L 512 #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID4_REMAPPING_FINISHED_MASK 0x00000010L 513 #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID5_REMAPPING_FINISHED_MASK 0x00000020L 514 #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID6_REMAPPING_FINISHED_MASK 0x00000040L 515 #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID7_REMAPPING_FINISHED_MASK 0x00000080L 516 #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID8_REMAPPING_FINISHED_MASK 0x00000100L 517 #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID9_REMAPPING_FINISHED_MASK 0x00000200L 518 #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID10_REMAPPING_FINISHED_MASK 0x00000400L 519 #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID11_REMAPPING_FINISHED_MASK 0x00000800L 520 #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID12_REMAPPING_FINISHED_MASK 0x00001000L 521 #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID13_REMAPPING_FINISHED_MASK 0x00002000L 522 #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID14_REMAPPING_FINISHED_MASK 0x00004000L 523 #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID15_REMAPPING_FINISHED_MASK 0x00008000L 524 #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID16_REMAPPING_FINISHED_MASK 0x00010000L 525 #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID17_REMAPPING_FINISHED_MASK 0x00020000L 526 #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID18_REMAPPING_FINISHED_MASK 0x00040000L 527 #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID19_REMAPPING_FINISHED_MASK 0x00080000L 528 #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID20_REMAPPING_FINISHED_MASK 0x00100000L 529 #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID21_REMAPPING_FINISHED_MASK 0x00200000L 530 #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID22_REMAPPING_FINISHED_MASK 0x00400000L 531 #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID23_REMAPPING_FINISHED_MASK 0x00800000L 532 #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID24_REMAPPING_FINISHED_MASK 0x01000000L 533 #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID25_REMAPPING_FINISHED_MASK 0x02000000L 534 #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID26_REMAPPING_FINISHED_MASK 0x04000000L 535 #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID27_REMAPPING_FINISHED_MASK 0x08000000L 536 #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID28_REMAPPING_FINISHED_MASK 0x10000000L 537 #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID29_REMAPPING_FINISHED_MASK 0x20000000L 538 #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID30_REMAPPING_FINISHED_MASK 0x40000000L 539 #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID31_REMAPPING_FINISHED_MASK 0x80000000L 540 //ATC_ATS_VMID_STATUS 541 #define ATC_ATS_VMID_STATUS__VMID0_OUTSTANDING__SHIFT 0x0 542 #define ATC_ATS_VMID_STATUS__VMID1_OUTSTANDING__SHIFT 0x1 543 #define ATC_ATS_VMID_STATUS__VMID2_OUTSTANDING__SHIFT 0x2 544 #define ATC_ATS_VMID_STATUS__VMID3_OUTSTANDING__SHIFT 0x3 545 #define ATC_ATS_VMID_STATUS__VMID4_OUTSTANDING__SHIFT 0x4 546 #define ATC_ATS_VMID_STATUS__VMID5_OUTSTANDING__SHIFT 0x5 547 #define ATC_ATS_VMID_STATUS__VMID6_OUTSTANDING__SHIFT 0x6 548 #define ATC_ATS_VMID_STATUS__VMID7_OUTSTANDING__SHIFT 0x7 549 #define ATC_ATS_VMID_STATUS__VMID8_OUTSTANDING__SHIFT 0x8 550 #define ATC_ATS_VMID_STATUS__VMID9_OUTSTANDING__SHIFT 0x9 551 #define ATC_ATS_VMID_STATUS__VMID10_OUTSTANDING__SHIFT 0xa 552 #define ATC_ATS_VMID_STATUS__VMID11_OUTSTANDING__SHIFT 0xb 553 #define ATC_ATS_VMID_STATUS__VMID12_OUTSTANDING__SHIFT 0xc 554 #define ATC_ATS_VMID_STATUS__VMID13_OUTSTANDING__SHIFT 0xd 555 #define ATC_ATS_VMID_STATUS__VMID14_OUTSTANDING__SHIFT 0xe 556 #define ATC_ATS_VMID_STATUS__VMID15_OUTSTANDING__SHIFT 0xf 557 #define ATC_ATS_VMID_STATUS__VMID16_OUTSTANDING__SHIFT 0x10 558 #define ATC_ATS_VMID_STATUS__VMID17_OUTSTANDING__SHIFT 0x11 559 #define ATC_ATS_VMID_STATUS__VMID18_OUTSTANDING__SHIFT 0x12 560 #define ATC_ATS_VMID_STATUS__VMID19_OUTSTANDING__SHIFT 0x13 561 #define ATC_ATS_VMID_STATUS__VMID20_OUTSTANDING__SHIFT 0x14 562 #define ATC_ATS_VMID_STATUS__VMID21_OUTSTANDING__SHIFT 0x15 563 #define ATC_ATS_VMID_STATUS__VMID22_OUTSTANDING__SHIFT 0x16 564 #define ATC_ATS_VMID_STATUS__VMID23_OUTSTANDING__SHIFT 0x17 565 #define ATC_ATS_VMID_STATUS__VMID24_OUTSTANDING__SHIFT 0x18 566 #define ATC_ATS_VMID_STATUS__VMID25_OUTSTANDING__SHIFT 0x19 567 #define ATC_ATS_VMID_STATUS__VMID26_OUTSTANDING__SHIFT 0x1a 568 #define ATC_ATS_VMID_STATUS__VMID27_OUTSTANDING__SHIFT 0x1b 569 #define ATC_ATS_VMID_STATUS__VMID28_OUTSTANDING__SHIFT 0x1c 570 #define ATC_ATS_VMID_STATUS__VMID29_OUTSTANDING__SHIFT 0x1d 571 #define ATC_ATS_VMID_STATUS__VMID30_OUTSTANDING__SHIFT 0x1e 572 #define ATC_ATS_VMID_STATUS__VMID31_OUTSTANDING__SHIFT 0x1f 573 #define ATC_ATS_VMID_STATUS__VMID0_OUTSTANDING_MASK 0x00000001L 574 #define ATC_ATS_VMID_STATUS__VMID1_OUTSTANDING_MASK 0x00000002L 575 #define ATC_ATS_VMID_STATUS__VMID2_OUTSTANDING_MASK 0x00000004L 576 #define ATC_ATS_VMID_STATUS__VMID3_OUTSTANDING_MASK 0x00000008L 577 #define ATC_ATS_VMID_STATUS__VMID4_OUTSTANDING_MASK 0x00000010L 578 #define ATC_ATS_VMID_STATUS__VMID5_OUTSTANDING_MASK 0x00000020L 579 #define ATC_ATS_VMID_STATUS__VMID6_OUTSTANDING_MASK 0x00000040L 580 #define ATC_ATS_VMID_STATUS__VMID7_OUTSTANDING_MASK 0x00000080L 581 #define ATC_ATS_VMID_STATUS__VMID8_OUTSTANDING_MASK 0x00000100L 582 #define ATC_ATS_VMID_STATUS__VMID9_OUTSTANDING_MASK 0x00000200L 583 #define ATC_ATS_VMID_STATUS__VMID10_OUTSTANDING_MASK 0x00000400L 584 #define ATC_ATS_VMID_STATUS__VMID11_OUTSTANDING_MASK 0x00000800L 585 #define ATC_ATS_VMID_STATUS__VMID12_OUTSTANDING_MASK 0x00001000L 586 #define ATC_ATS_VMID_STATUS__VMID13_OUTSTANDING_MASK 0x00002000L 587 #define ATC_ATS_VMID_STATUS__VMID14_OUTSTANDING_MASK 0x00004000L 588 #define ATC_ATS_VMID_STATUS__VMID15_OUTSTANDING_MASK 0x00008000L 589 #define ATC_ATS_VMID_STATUS__VMID16_OUTSTANDING_MASK 0x00010000L 590 #define ATC_ATS_VMID_STATUS__VMID17_OUTSTANDING_MASK 0x00020000L 591 #define ATC_ATS_VMID_STATUS__VMID18_OUTSTANDING_MASK 0x00040000L 592 #define ATC_ATS_VMID_STATUS__VMID19_OUTSTANDING_MASK 0x00080000L 593 #define ATC_ATS_VMID_STATUS__VMID20_OUTSTANDING_MASK 0x00100000L 594 #define ATC_ATS_VMID_STATUS__VMID21_OUTSTANDING_MASK 0x00200000L 595 #define ATC_ATS_VMID_STATUS__VMID22_OUTSTANDING_MASK 0x00400000L 596 #define ATC_ATS_VMID_STATUS__VMID23_OUTSTANDING_MASK 0x00800000L 597 #define ATC_ATS_VMID_STATUS__VMID24_OUTSTANDING_MASK 0x01000000L 598 #define ATC_ATS_VMID_STATUS__VMID25_OUTSTANDING_MASK 0x02000000L 599 #define ATC_ATS_VMID_STATUS__VMID26_OUTSTANDING_MASK 0x04000000L 600 #define ATC_ATS_VMID_STATUS__VMID27_OUTSTANDING_MASK 0x08000000L 601 #define ATC_ATS_VMID_STATUS__VMID28_OUTSTANDING_MASK 0x10000000L 602 #define ATC_ATS_VMID_STATUS__VMID29_OUTSTANDING_MASK 0x20000000L 603 #define ATC_ATS_VMID_STATUS__VMID30_OUTSTANDING_MASK 0x40000000L 604 #define ATC_ATS_VMID_STATUS__VMID31_OUTSTANDING_MASK 0x80000000L 605 //ATC_ATS_STATUS 606 #define ATC_ATS_STATUS__BUSY__SHIFT 0x0 607 #define ATC_ATS_STATUS__CRASHED__SHIFT 0x1 608 #define ATC_ATS_STATUS__DEADLOCK_DETECTION__SHIFT 0x2 609 #define ATC_ATS_STATUS__FLUSH_INVALIDATION_OUTSTANDING__SHIFT 0x3 610 #define ATC_ATS_STATUS__NONFLUSH_INVALIDATION_OUTSTANDING__SHIFT 0x6 611 #define ATC_ATS_STATUS__BUSY_MASK 0x00000001L 612 #define ATC_ATS_STATUS__CRASHED_MASK 0x00000002L 613 #define ATC_ATS_STATUS__DEADLOCK_DETECTION_MASK 0x00000004L 614 #define ATC_ATS_STATUS__FLUSH_INVALIDATION_OUTSTANDING_MASK 0x00000038L 615 #define ATC_ATS_STATUS__NONFLUSH_INVALIDATION_OUTSTANDING_MASK 0x000001C0L 616 //ATC_ATS_VMID_SNAPSHOT_GFX_STAT 617 #define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID0__SHIFT 0x0 618 #define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID1__SHIFT 0x1 619 #define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID2__SHIFT 0x2 620 #define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID3__SHIFT 0x3 621 #define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID4__SHIFT 0x4 622 #define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID5__SHIFT 0x5 623 #define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID6__SHIFT 0x6 624 #define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID7__SHIFT 0x7 625 #define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID8__SHIFT 0x8 626 #define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID9__SHIFT 0x9 627 #define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID10__SHIFT 0xa 628 #define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID11__SHIFT 0xb 629 #define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID12__SHIFT 0xc 630 #define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID13__SHIFT 0xd 631 #define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID14__SHIFT 0xe 632 #define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID15__SHIFT 0xf 633 #define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID0_MASK 0x00000001L 634 #define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID1_MASK 0x00000002L 635 #define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID2_MASK 0x00000004L 636 #define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID3_MASK 0x00000008L 637 #define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID4_MASK 0x00000010L 638 #define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID5_MASK 0x00000020L 639 #define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID6_MASK 0x00000040L 640 #define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID7_MASK 0x00000080L 641 #define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID8_MASK 0x00000100L 642 #define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID9_MASK 0x00000200L 643 #define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID10_MASK 0x00000400L 644 #define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID11_MASK 0x00000800L 645 #define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID12_MASK 0x00001000L 646 #define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID13_MASK 0x00002000L 647 #define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID14_MASK 0x00004000L 648 #define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID15_MASK 0x00008000L 649 //ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT 650 #define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID0__SHIFT 0x0 651 #define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID1__SHIFT 0x1 652 #define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID2__SHIFT 0x2 653 #define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID3__SHIFT 0x3 654 #define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID4__SHIFT 0x4 655 #define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID5__SHIFT 0x5 656 #define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID6__SHIFT 0x6 657 #define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID7__SHIFT 0x7 658 #define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID8__SHIFT 0x8 659 #define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID9__SHIFT 0x9 660 #define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID10__SHIFT 0xa 661 #define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID11__SHIFT 0xb 662 #define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID12__SHIFT 0xc 663 #define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID13__SHIFT 0xd 664 #define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID14__SHIFT 0xe 665 #define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID15__SHIFT 0xf 666 #define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID0_MASK 0x00000001L 667 #define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID1_MASK 0x00000002L 668 #define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID2_MASK 0x00000004L 669 #define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID3_MASK 0x00000008L 670 #define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID4_MASK 0x00000010L 671 #define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID5_MASK 0x00000020L 672 #define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID6_MASK 0x00000040L 673 #define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID7_MASK 0x00000080L 674 #define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID8_MASK 0x00000100L 675 #define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID9_MASK 0x00000200L 676 #define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID10_MASK 0x00000400L 677 #define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID11_MASK 0x00000800L 678 #define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID12_MASK 0x00001000L 679 #define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID13_MASK 0x00002000L 680 #define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID14_MASK 0x00004000L 681 #define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID15_MASK 0x00008000L 682 //ATC_VMID0_PASID_MAPPING 683 #define ATC_VMID0_PASID_MAPPING__PASID__SHIFT 0x0 684 #define ATC_VMID0_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e 685 #define ATC_VMID0_PASID_MAPPING__VALID__SHIFT 0x1f 686 #define ATC_VMID0_PASID_MAPPING__PASID_MASK 0x0000FFFFL 687 #define ATC_VMID0_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L 688 #define ATC_VMID0_PASID_MAPPING__VALID_MASK 0x80000000L 689 //ATC_VMID1_PASID_MAPPING 690 #define ATC_VMID1_PASID_MAPPING__PASID__SHIFT 0x0 691 #define ATC_VMID1_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e 692 #define ATC_VMID1_PASID_MAPPING__VALID__SHIFT 0x1f 693 #define ATC_VMID1_PASID_MAPPING__PASID_MASK 0x0000FFFFL 694 #define ATC_VMID1_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L 695 #define ATC_VMID1_PASID_MAPPING__VALID_MASK 0x80000000L 696 //ATC_VMID2_PASID_MAPPING 697 #define ATC_VMID2_PASID_MAPPING__PASID__SHIFT 0x0 698 #define ATC_VMID2_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e 699 #define ATC_VMID2_PASID_MAPPING__VALID__SHIFT 0x1f 700 #define ATC_VMID2_PASID_MAPPING__PASID_MASK 0x0000FFFFL 701 #define ATC_VMID2_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L 702 #define ATC_VMID2_PASID_MAPPING__VALID_MASK 0x80000000L 703 //ATC_VMID3_PASID_MAPPING 704 #define ATC_VMID3_PASID_MAPPING__PASID__SHIFT 0x0 705 #define ATC_VMID3_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e 706 #define ATC_VMID3_PASID_MAPPING__VALID__SHIFT 0x1f 707 #define ATC_VMID3_PASID_MAPPING__PASID_MASK 0x0000FFFFL 708 #define ATC_VMID3_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L 709 #define ATC_VMID3_PASID_MAPPING__VALID_MASK 0x80000000L 710 //ATC_VMID4_PASID_MAPPING 711 #define ATC_VMID4_PASID_MAPPING__PASID__SHIFT 0x0 712 #define ATC_VMID4_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e 713 #define ATC_VMID4_PASID_MAPPING__VALID__SHIFT 0x1f 714 #define ATC_VMID4_PASID_MAPPING__PASID_MASK 0x0000FFFFL 715 #define ATC_VMID4_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L 716 #define ATC_VMID4_PASID_MAPPING__VALID_MASK 0x80000000L 717 //ATC_VMID5_PASID_MAPPING 718 #define ATC_VMID5_PASID_MAPPING__PASID__SHIFT 0x0 719 #define ATC_VMID5_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e 720 #define ATC_VMID5_PASID_MAPPING__VALID__SHIFT 0x1f 721 #define ATC_VMID5_PASID_MAPPING__PASID_MASK 0x0000FFFFL 722 #define ATC_VMID5_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L 723 #define ATC_VMID5_PASID_MAPPING__VALID_MASK 0x80000000L 724 //ATC_VMID6_PASID_MAPPING 725 #define ATC_VMID6_PASID_MAPPING__PASID__SHIFT 0x0 726 #define ATC_VMID6_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e 727 #define ATC_VMID6_PASID_MAPPING__VALID__SHIFT 0x1f 728 #define ATC_VMID6_PASID_MAPPING__PASID_MASK 0x0000FFFFL 729 #define ATC_VMID6_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L 730 #define ATC_VMID6_PASID_MAPPING__VALID_MASK 0x80000000L 731 //ATC_VMID7_PASID_MAPPING 732 #define ATC_VMID7_PASID_MAPPING__PASID__SHIFT 0x0 733 #define ATC_VMID7_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e 734 #define ATC_VMID7_PASID_MAPPING__VALID__SHIFT 0x1f 735 #define ATC_VMID7_PASID_MAPPING__PASID_MASK 0x0000FFFFL 736 #define ATC_VMID7_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L 737 #define ATC_VMID7_PASID_MAPPING__VALID_MASK 0x80000000L 738 //ATC_VMID8_PASID_MAPPING 739 #define ATC_VMID8_PASID_MAPPING__PASID__SHIFT 0x0 740 #define ATC_VMID8_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e 741 #define ATC_VMID8_PASID_MAPPING__VALID__SHIFT 0x1f 742 #define ATC_VMID8_PASID_MAPPING__PASID_MASK 0x0000FFFFL 743 #define ATC_VMID8_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L 744 #define ATC_VMID8_PASID_MAPPING__VALID_MASK 0x80000000L 745 //ATC_VMID9_PASID_MAPPING 746 #define ATC_VMID9_PASID_MAPPING__PASID__SHIFT 0x0 747 #define ATC_VMID9_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e 748 #define ATC_VMID9_PASID_MAPPING__VALID__SHIFT 0x1f 749 #define ATC_VMID9_PASID_MAPPING__PASID_MASK 0x0000FFFFL 750 #define ATC_VMID9_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L 751 #define ATC_VMID9_PASID_MAPPING__VALID_MASK 0x80000000L 752 //ATC_VMID10_PASID_MAPPING 753 #define ATC_VMID10_PASID_MAPPING__PASID__SHIFT 0x0 754 #define ATC_VMID10_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e 755 #define ATC_VMID10_PASID_MAPPING__VALID__SHIFT 0x1f 756 #define ATC_VMID10_PASID_MAPPING__PASID_MASK 0x0000FFFFL 757 #define ATC_VMID10_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L 758 #define ATC_VMID10_PASID_MAPPING__VALID_MASK 0x80000000L 759 //ATC_VMID11_PASID_MAPPING 760 #define ATC_VMID11_PASID_MAPPING__PASID__SHIFT 0x0 761 #define ATC_VMID11_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e 762 #define ATC_VMID11_PASID_MAPPING__VALID__SHIFT 0x1f 763 #define ATC_VMID11_PASID_MAPPING__PASID_MASK 0x0000FFFFL 764 #define ATC_VMID11_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L 765 #define ATC_VMID11_PASID_MAPPING__VALID_MASK 0x80000000L 766 //ATC_VMID12_PASID_MAPPING 767 #define ATC_VMID12_PASID_MAPPING__PASID__SHIFT 0x0 768 #define ATC_VMID12_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e 769 #define ATC_VMID12_PASID_MAPPING__VALID__SHIFT 0x1f 770 #define ATC_VMID12_PASID_MAPPING__PASID_MASK 0x0000FFFFL 771 #define ATC_VMID12_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L 772 #define ATC_VMID12_PASID_MAPPING__VALID_MASK 0x80000000L 773 //ATC_VMID13_PASID_MAPPING 774 #define ATC_VMID13_PASID_MAPPING__PASID__SHIFT 0x0 775 #define ATC_VMID13_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e 776 #define ATC_VMID13_PASID_MAPPING__VALID__SHIFT 0x1f 777 #define ATC_VMID13_PASID_MAPPING__PASID_MASK 0x0000FFFFL 778 #define ATC_VMID13_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L 779 #define ATC_VMID13_PASID_MAPPING__VALID_MASK 0x80000000L 780 //ATC_VMID14_PASID_MAPPING 781 #define ATC_VMID14_PASID_MAPPING__PASID__SHIFT 0x0 782 #define ATC_VMID14_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e 783 #define ATC_VMID14_PASID_MAPPING__VALID__SHIFT 0x1f 784 #define ATC_VMID14_PASID_MAPPING__PASID_MASK 0x0000FFFFL 785 #define ATC_VMID14_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L 786 #define ATC_VMID14_PASID_MAPPING__VALID_MASK 0x80000000L 787 //ATC_VMID15_PASID_MAPPING 788 #define ATC_VMID15_PASID_MAPPING__PASID__SHIFT 0x0 789 #define ATC_VMID15_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e 790 #define ATC_VMID15_PASID_MAPPING__VALID__SHIFT 0x1f 791 #define ATC_VMID15_PASID_MAPPING__PASID_MASK 0x0000FFFFL 792 #define ATC_VMID15_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L 793 #define ATC_VMID15_PASID_MAPPING__VALID_MASK 0x80000000L 794 //ATC_VMID16_PASID_MAPPING 795 #define ATC_VMID16_PASID_MAPPING__PASID__SHIFT 0x0 796 #define ATC_VMID16_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e 797 #define ATC_VMID16_PASID_MAPPING__VALID__SHIFT 0x1f 798 #define ATC_VMID16_PASID_MAPPING__PASID_MASK 0x0000FFFFL 799 #define ATC_VMID16_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L 800 #define ATC_VMID16_PASID_MAPPING__VALID_MASK 0x80000000L 801 //ATC_VMID17_PASID_MAPPING 802 #define ATC_VMID17_PASID_MAPPING__PASID__SHIFT 0x0 803 #define ATC_VMID17_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e 804 #define ATC_VMID17_PASID_MAPPING__VALID__SHIFT 0x1f 805 #define ATC_VMID17_PASID_MAPPING__PASID_MASK 0x0000FFFFL 806 #define ATC_VMID17_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L 807 #define ATC_VMID17_PASID_MAPPING__VALID_MASK 0x80000000L 808 //ATC_VMID18_PASID_MAPPING 809 #define ATC_VMID18_PASID_MAPPING__PASID__SHIFT 0x0 810 #define ATC_VMID18_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e 811 #define ATC_VMID18_PASID_MAPPING__VALID__SHIFT 0x1f 812 #define ATC_VMID18_PASID_MAPPING__PASID_MASK 0x0000FFFFL 813 #define ATC_VMID18_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L 814 #define ATC_VMID18_PASID_MAPPING__VALID_MASK 0x80000000L 815 //ATC_VMID19_PASID_MAPPING 816 #define ATC_VMID19_PASID_MAPPING__PASID__SHIFT 0x0 817 #define ATC_VMID19_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e 818 #define ATC_VMID19_PASID_MAPPING__VALID__SHIFT 0x1f 819 #define ATC_VMID19_PASID_MAPPING__PASID_MASK 0x0000FFFFL 820 #define ATC_VMID19_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L 821 #define ATC_VMID19_PASID_MAPPING__VALID_MASK 0x80000000L 822 //ATC_VMID20_PASID_MAPPING 823 #define ATC_VMID20_PASID_MAPPING__PASID__SHIFT 0x0 824 #define ATC_VMID20_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e 825 #define ATC_VMID20_PASID_MAPPING__VALID__SHIFT 0x1f 826 #define ATC_VMID20_PASID_MAPPING__PASID_MASK 0x0000FFFFL 827 #define ATC_VMID20_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L 828 #define ATC_VMID20_PASID_MAPPING__VALID_MASK 0x80000000L 829 //ATC_VMID21_PASID_MAPPING 830 #define ATC_VMID21_PASID_MAPPING__PASID__SHIFT 0x0 831 #define ATC_VMID21_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e 832 #define ATC_VMID21_PASID_MAPPING__VALID__SHIFT 0x1f 833 #define ATC_VMID21_PASID_MAPPING__PASID_MASK 0x0000FFFFL 834 #define ATC_VMID21_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L 835 #define ATC_VMID21_PASID_MAPPING__VALID_MASK 0x80000000L 836 //ATC_VMID22_PASID_MAPPING 837 #define ATC_VMID22_PASID_MAPPING__PASID__SHIFT 0x0 838 #define ATC_VMID22_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e 839 #define ATC_VMID22_PASID_MAPPING__VALID__SHIFT 0x1f 840 #define ATC_VMID22_PASID_MAPPING__PASID_MASK 0x0000FFFFL 841 #define ATC_VMID22_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L 842 #define ATC_VMID22_PASID_MAPPING__VALID_MASK 0x80000000L 843 //ATC_VMID23_PASID_MAPPING 844 #define ATC_VMID23_PASID_MAPPING__PASID__SHIFT 0x0 845 #define ATC_VMID23_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e 846 #define ATC_VMID23_PASID_MAPPING__VALID__SHIFT 0x1f 847 #define ATC_VMID23_PASID_MAPPING__PASID_MASK 0x0000FFFFL 848 #define ATC_VMID23_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L 849 #define ATC_VMID23_PASID_MAPPING__VALID_MASK 0x80000000L 850 //ATC_VMID24_PASID_MAPPING 851 #define ATC_VMID24_PASID_MAPPING__PASID__SHIFT 0x0 852 #define ATC_VMID24_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e 853 #define ATC_VMID24_PASID_MAPPING__VALID__SHIFT 0x1f 854 #define ATC_VMID24_PASID_MAPPING__PASID_MASK 0x0000FFFFL 855 #define ATC_VMID24_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L 856 #define ATC_VMID24_PASID_MAPPING__VALID_MASK 0x80000000L 857 //ATC_VMID25_PASID_MAPPING 858 #define ATC_VMID25_PASID_MAPPING__PASID__SHIFT 0x0 859 #define ATC_VMID25_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e 860 #define ATC_VMID25_PASID_MAPPING__VALID__SHIFT 0x1f 861 #define ATC_VMID25_PASID_MAPPING__PASID_MASK 0x0000FFFFL 862 #define ATC_VMID25_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L 863 #define ATC_VMID25_PASID_MAPPING__VALID_MASK 0x80000000L 864 //ATC_VMID26_PASID_MAPPING 865 #define ATC_VMID26_PASID_MAPPING__PASID__SHIFT 0x0 866 #define ATC_VMID26_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e 867 #define ATC_VMID26_PASID_MAPPING__VALID__SHIFT 0x1f 868 #define ATC_VMID26_PASID_MAPPING__PASID_MASK 0x0000FFFFL 869 #define ATC_VMID26_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L 870 #define ATC_VMID26_PASID_MAPPING__VALID_MASK 0x80000000L 871 //ATC_VMID27_PASID_MAPPING 872 #define ATC_VMID27_PASID_MAPPING__PASID__SHIFT 0x0 873 #define ATC_VMID27_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e 874 #define ATC_VMID27_PASID_MAPPING__VALID__SHIFT 0x1f 875 #define ATC_VMID27_PASID_MAPPING__PASID_MASK 0x0000FFFFL 876 #define ATC_VMID27_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L 877 #define ATC_VMID27_PASID_MAPPING__VALID_MASK 0x80000000L 878 //ATC_VMID28_PASID_MAPPING 879 #define ATC_VMID28_PASID_MAPPING__PASID__SHIFT 0x0 880 #define ATC_VMID28_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e 881 #define ATC_VMID28_PASID_MAPPING__VALID__SHIFT 0x1f 882 #define ATC_VMID28_PASID_MAPPING__PASID_MASK 0x0000FFFFL 883 #define ATC_VMID28_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L 884 #define ATC_VMID28_PASID_MAPPING__VALID_MASK 0x80000000L 885 //ATC_VMID29_PASID_MAPPING 886 #define ATC_VMID29_PASID_MAPPING__PASID__SHIFT 0x0 887 #define ATC_VMID29_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e 888 #define ATC_VMID29_PASID_MAPPING__VALID__SHIFT 0x1f 889 #define ATC_VMID29_PASID_MAPPING__PASID_MASK 0x0000FFFFL 890 #define ATC_VMID29_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L 891 #define ATC_VMID29_PASID_MAPPING__VALID_MASK 0x80000000L 892 //ATC_VMID30_PASID_MAPPING 893 #define ATC_VMID30_PASID_MAPPING__PASID__SHIFT 0x0 894 #define ATC_VMID30_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e 895 #define ATC_VMID30_PASID_MAPPING__VALID__SHIFT 0x1f 896 #define ATC_VMID30_PASID_MAPPING__PASID_MASK 0x0000FFFFL 897 #define ATC_VMID30_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L 898 #define ATC_VMID30_PASID_MAPPING__VALID_MASK 0x80000000L 899 //ATC_VMID31_PASID_MAPPING 900 #define ATC_VMID31_PASID_MAPPING__PASID__SHIFT 0x0 901 #define ATC_VMID31_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e 902 #define ATC_VMID31_PASID_MAPPING__VALID__SHIFT 0x1f 903 #define ATC_VMID31_PASID_MAPPING__PASID_MASK 0x0000FFFFL 904 #define ATC_VMID31_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L 905 #define ATC_VMID31_PASID_MAPPING__VALID_MASK 0x80000000L 906 907 908 // addressBlock: athub_xpbdec 909 //XPB_RTR_SRC_APRTR0 910 #define XPB_RTR_SRC_APRTR0__BASE_ADDR__SHIFT 0x0 911 #define XPB_RTR_SRC_APRTR0__BASE_ADDR_MASK 0x7FFFFFFFL 912 //XPB_RTR_SRC_APRTR1 913 #define XPB_RTR_SRC_APRTR1__BASE_ADDR__SHIFT 0x0 914 #define XPB_RTR_SRC_APRTR1__BASE_ADDR_MASK 0x7FFFFFFFL 915 //XPB_RTR_SRC_APRTR2 916 #define XPB_RTR_SRC_APRTR2__BASE_ADDR__SHIFT 0x0 917 #define XPB_RTR_SRC_APRTR2__BASE_ADDR_MASK 0x7FFFFFFFL 918 //XPB_RTR_SRC_APRTR3 919 #define XPB_RTR_SRC_APRTR3__BASE_ADDR__SHIFT 0x0 920 #define XPB_RTR_SRC_APRTR3__BASE_ADDR_MASK 0x7FFFFFFFL 921 //XPB_RTR_SRC_APRTR4 922 #define XPB_RTR_SRC_APRTR4__BASE_ADDR__SHIFT 0x0 923 #define XPB_RTR_SRC_APRTR4__BASE_ADDR_MASK 0x7FFFFFFFL 924 //XPB_RTR_SRC_APRTR5 925 #define XPB_RTR_SRC_APRTR5__BASE_ADDR__SHIFT 0x0 926 #define XPB_RTR_SRC_APRTR5__BASE_ADDR_MASK 0x7FFFFFFFL 927 //XPB_RTR_SRC_APRTR6 928 #define XPB_RTR_SRC_APRTR6__BASE_ADDR__SHIFT 0x0 929 #define XPB_RTR_SRC_APRTR6__BASE_ADDR_MASK 0x7FFFFFFFL 930 //XPB_RTR_SRC_APRTR7 931 #define XPB_RTR_SRC_APRTR7__BASE_ADDR__SHIFT 0x0 932 #define XPB_RTR_SRC_APRTR7__BASE_ADDR_MASK 0x7FFFFFFFL 933 //XPB_RTR_SRC_APRTR8 934 #define XPB_RTR_SRC_APRTR8__BASE_ADDR__SHIFT 0x0 935 #define XPB_RTR_SRC_APRTR8__BASE_ADDR_MASK 0x7FFFFFFFL 936 //XPB_RTR_SRC_APRTR9 937 #define XPB_RTR_SRC_APRTR9__BASE_ADDR__SHIFT 0x0 938 #define XPB_RTR_SRC_APRTR9__BASE_ADDR_MASK 0x7FFFFFFFL 939 //XPB_RTR_SRC_APRTR10 940 #define XPB_RTR_SRC_APRTR10__BASE_ADDR__SHIFT 0x0 941 #define XPB_RTR_SRC_APRTR10__BASE_ADDR_MASK 0x7FFFFFFFL 942 //XPB_RTR_SRC_APRTR11 943 #define XPB_RTR_SRC_APRTR11__BASE_ADDR__SHIFT 0x0 944 #define XPB_RTR_SRC_APRTR11__BASE_ADDR_MASK 0x7FFFFFFFL 945 //XPB_RTR_SRC_APRTR12 946 #define XPB_RTR_SRC_APRTR12__BASE_ADDR__SHIFT 0x0 947 #define XPB_RTR_SRC_APRTR12__BASE_ADDR_MASK 0x7FFFFFFFL 948 //XPB_RTR_SRC_APRTR13 949 #define XPB_RTR_SRC_APRTR13__BASE_ADDR__SHIFT 0x0 950 #define XPB_RTR_SRC_APRTR13__BASE_ADDR_MASK 0x7FFFFFFFL 951 //XPB_RTR_DEST_MAP0 952 #define XPB_RTR_DEST_MAP0__NMR__SHIFT 0x0 953 #define XPB_RTR_DEST_MAP0__DEST_OFFSET__SHIFT 0x1 954 #define XPB_RTR_DEST_MAP0__DEST_SEL__SHIFT 0x14 955 #define XPB_RTR_DEST_MAP0__DEST_SEL_RPB__SHIFT 0x18 956 #define XPB_RTR_DEST_MAP0__SIDE_OK__SHIFT 0x19 957 #define XPB_RTR_DEST_MAP0__APRTR_SIZE__SHIFT 0x1a 958 #define XPB_RTR_DEST_MAP0__NMR_MASK 0x00000001L 959 #define XPB_RTR_DEST_MAP0__DEST_OFFSET_MASK 0x000FFFFEL 960 #define XPB_RTR_DEST_MAP0__DEST_SEL_MASK 0x00F00000L 961 #define XPB_RTR_DEST_MAP0__DEST_SEL_RPB_MASK 0x01000000L 962 #define XPB_RTR_DEST_MAP0__SIDE_OK_MASK 0x02000000L 963 #define XPB_RTR_DEST_MAP0__APRTR_SIZE_MASK 0x7C000000L 964 //XPB_RTR_DEST_MAP1 965 #define XPB_RTR_DEST_MAP1__NMR__SHIFT 0x0 966 #define XPB_RTR_DEST_MAP1__DEST_OFFSET__SHIFT 0x1 967 #define XPB_RTR_DEST_MAP1__DEST_SEL__SHIFT 0x14 968 #define XPB_RTR_DEST_MAP1__DEST_SEL_RPB__SHIFT 0x18 969 #define XPB_RTR_DEST_MAP1__SIDE_OK__SHIFT 0x19 970 #define XPB_RTR_DEST_MAP1__APRTR_SIZE__SHIFT 0x1a 971 #define XPB_RTR_DEST_MAP1__NMR_MASK 0x00000001L 972 #define XPB_RTR_DEST_MAP1__DEST_OFFSET_MASK 0x000FFFFEL 973 #define XPB_RTR_DEST_MAP1__DEST_SEL_MASK 0x00F00000L 974 #define XPB_RTR_DEST_MAP1__DEST_SEL_RPB_MASK 0x01000000L 975 #define XPB_RTR_DEST_MAP1__SIDE_OK_MASK 0x02000000L 976 #define XPB_RTR_DEST_MAP1__APRTR_SIZE_MASK 0x7C000000L 977 //XPB_RTR_DEST_MAP2 978 #define XPB_RTR_DEST_MAP2__NMR__SHIFT 0x0 979 #define XPB_RTR_DEST_MAP2__DEST_OFFSET__SHIFT 0x1 980 #define XPB_RTR_DEST_MAP2__DEST_SEL__SHIFT 0x14 981 #define XPB_RTR_DEST_MAP2__DEST_SEL_RPB__SHIFT 0x18 982 #define XPB_RTR_DEST_MAP2__SIDE_OK__SHIFT 0x19 983 #define XPB_RTR_DEST_MAP2__APRTR_SIZE__SHIFT 0x1a 984 #define XPB_RTR_DEST_MAP2__NMR_MASK 0x00000001L 985 #define XPB_RTR_DEST_MAP2__DEST_OFFSET_MASK 0x000FFFFEL 986 #define XPB_RTR_DEST_MAP2__DEST_SEL_MASK 0x00F00000L 987 #define XPB_RTR_DEST_MAP2__DEST_SEL_RPB_MASK 0x01000000L 988 #define XPB_RTR_DEST_MAP2__SIDE_OK_MASK 0x02000000L 989 #define XPB_RTR_DEST_MAP2__APRTR_SIZE_MASK 0x7C000000L 990 //XPB_RTR_DEST_MAP3 991 #define XPB_RTR_DEST_MAP3__NMR__SHIFT 0x0 992 #define XPB_RTR_DEST_MAP3__DEST_OFFSET__SHIFT 0x1 993 #define XPB_RTR_DEST_MAP3__DEST_SEL__SHIFT 0x14 994 #define XPB_RTR_DEST_MAP3__DEST_SEL_RPB__SHIFT 0x18 995 #define XPB_RTR_DEST_MAP3__SIDE_OK__SHIFT 0x19 996 #define XPB_RTR_DEST_MAP3__APRTR_SIZE__SHIFT 0x1a 997 #define XPB_RTR_DEST_MAP3__NMR_MASK 0x00000001L 998 #define XPB_RTR_DEST_MAP3__DEST_OFFSET_MASK 0x000FFFFEL 999 #define XPB_RTR_DEST_MAP3__DEST_SEL_MASK 0x00F00000L 1000 #define XPB_RTR_DEST_MAP3__DEST_SEL_RPB_MASK 0x01000000L 1001 #define XPB_RTR_DEST_MAP3__SIDE_OK_MASK 0x02000000L 1002 #define XPB_RTR_DEST_MAP3__APRTR_SIZE_MASK 0x7C000000L 1003 //XPB_RTR_DEST_MAP4 1004 #define XPB_RTR_DEST_MAP4__NMR__SHIFT 0x0 1005 #define XPB_RTR_DEST_MAP4__DEST_OFFSET__SHIFT 0x1 1006 #define XPB_RTR_DEST_MAP4__DEST_SEL__SHIFT 0x14 1007 #define XPB_RTR_DEST_MAP4__DEST_SEL_RPB__SHIFT 0x18 1008 #define XPB_RTR_DEST_MAP4__SIDE_OK__SHIFT 0x19 1009 #define XPB_RTR_DEST_MAP4__APRTR_SIZE__SHIFT 0x1a 1010 #define XPB_RTR_DEST_MAP4__NMR_MASK 0x00000001L 1011 #define XPB_RTR_DEST_MAP4__DEST_OFFSET_MASK 0x000FFFFEL 1012 #define XPB_RTR_DEST_MAP4__DEST_SEL_MASK 0x00F00000L 1013 #define XPB_RTR_DEST_MAP4__DEST_SEL_RPB_MASK 0x01000000L 1014 #define XPB_RTR_DEST_MAP4__SIDE_OK_MASK 0x02000000L 1015 #define XPB_RTR_DEST_MAP4__APRTR_SIZE_MASK 0x7C000000L 1016 //XPB_RTR_DEST_MAP5 1017 #define XPB_RTR_DEST_MAP5__NMR__SHIFT 0x0 1018 #define XPB_RTR_DEST_MAP5__DEST_OFFSET__SHIFT 0x1 1019 #define XPB_RTR_DEST_MAP5__DEST_SEL__SHIFT 0x14 1020 #define XPB_RTR_DEST_MAP5__DEST_SEL_RPB__SHIFT 0x18 1021 #define XPB_RTR_DEST_MAP5__SIDE_OK__SHIFT 0x19 1022 #define XPB_RTR_DEST_MAP5__APRTR_SIZE__SHIFT 0x1a 1023 #define XPB_RTR_DEST_MAP5__NMR_MASK 0x00000001L 1024 #define XPB_RTR_DEST_MAP5__DEST_OFFSET_MASK 0x000FFFFEL 1025 #define XPB_RTR_DEST_MAP5__DEST_SEL_MASK 0x00F00000L 1026 #define XPB_RTR_DEST_MAP5__DEST_SEL_RPB_MASK 0x01000000L 1027 #define XPB_RTR_DEST_MAP5__SIDE_OK_MASK 0x02000000L 1028 #define XPB_RTR_DEST_MAP5__APRTR_SIZE_MASK 0x7C000000L 1029 //XPB_RTR_DEST_MAP6 1030 #define XPB_RTR_DEST_MAP6__NMR__SHIFT 0x0 1031 #define XPB_RTR_DEST_MAP6__DEST_OFFSET__SHIFT 0x1 1032 #define XPB_RTR_DEST_MAP6__DEST_SEL__SHIFT 0x14 1033 #define XPB_RTR_DEST_MAP6__DEST_SEL_RPB__SHIFT 0x18 1034 #define XPB_RTR_DEST_MAP6__SIDE_OK__SHIFT 0x19 1035 #define XPB_RTR_DEST_MAP6__APRTR_SIZE__SHIFT 0x1a 1036 #define XPB_RTR_DEST_MAP6__NMR_MASK 0x00000001L 1037 #define XPB_RTR_DEST_MAP6__DEST_OFFSET_MASK 0x000FFFFEL 1038 #define XPB_RTR_DEST_MAP6__DEST_SEL_MASK 0x00F00000L 1039 #define XPB_RTR_DEST_MAP6__DEST_SEL_RPB_MASK 0x01000000L 1040 #define XPB_RTR_DEST_MAP6__SIDE_OK_MASK 0x02000000L 1041 #define XPB_RTR_DEST_MAP6__APRTR_SIZE_MASK 0x7C000000L 1042 //XPB_RTR_DEST_MAP7 1043 #define XPB_RTR_DEST_MAP7__NMR__SHIFT 0x0 1044 #define XPB_RTR_DEST_MAP7__DEST_OFFSET__SHIFT 0x1 1045 #define XPB_RTR_DEST_MAP7__DEST_SEL__SHIFT 0x14 1046 #define XPB_RTR_DEST_MAP7__DEST_SEL_RPB__SHIFT 0x18 1047 #define XPB_RTR_DEST_MAP7__SIDE_OK__SHIFT 0x19 1048 #define XPB_RTR_DEST_MAP7__APRTR_SIZE__SHIFT 0x1a 1049 #define XPB_RTR_DEST_MAP7__NMR_MASK 0x00000001L 1050 #define XPB_RTR_DEST_MAP7__DEST_OFFSET_MASK 0x000FFFFEL 1051 #define XPB_RTR_DEST_MAP7__DEST_SEL_MASK 0x00F00000L 1052 #define XPB_RTR_DEST_MAP7__DEST_SEL_RPB_MASK 0x01000000L 1053 #define XPB_RTR_DEST_MAP7__SIDE_OK_MASK 0x02000000L 1054 #define XPB_RTR_DEST_MAP7__APRTR_SIZE_MASK 0x7C000000L 1055 //XPB_RTR_DEST_MAP8 1056 #define XPB_RTR_DEST_MAP8__NMR__SHIFT 0x0 1057 #define XPB_RTR_DEST_MAP8__DEST_OFFSET__SHIFT 0x1 1058 #define XPB_RTR_DEST_MAP8__DEST_SEL__SHIFT 0x14 1059 #define XPB_RTR_DEST_MAP8__DEST_SEL_RPB__SHIFT 0x18 1060 #define XPB_RTR_DEST_MAP8__SIDE_OK__SHIFT 0x19 1061 #define XPB_RTR_DEST_MAP8__APRTR_SIZE__SHIFT 0x1a 1062 #define XPB_RTR_DEST_MAP8__NMR_MASK 0x00000001L 1063 #define XPB_RTR_DEST_MAP8__DEST_OFFSET_MASK 0x000FFFFEL 1064 #define XPB_RTR_DEST_MAP8__DEST_SEL_MASK 0x00F00000L 1065 #define XPB_RTR_DEST_MAP8__DEST_SEL_RPB_MASK 0x01000000L 1066 #define XPB_RTR_DEST_MAP8__SIDE_OK_MASK 0x02000000L 1067 #define XPB_RTR_DEST_MAP8__APRTR_SIZE_MASK 0x7C000000L 1068 //XPB_RTR_DEST_MAP9 1069 #define XPB_RTR_DEST_MAP9__NMR__SHIFT 0x0 1070 #define XPB_RTR_DEST_MAP9__DEST_OFFSET__SHIFT 0x1 1071 #define XPB_RTR_DEST_MAP9__DEST_SEL__SHIFT 0x14 1072 #define XPB_RTR_DEST_MAP9__DEST_SEL_RPB__SHIFT 0x18 1073 #define XPB_RTR_DEST_MAP9__SIDE_OK__SHIFT 0x19 1074 #define XPB_RTR_DEST_MAP9__APRTR_SIZE__SHIFT 0x1a 1075 #define XPB_RTR_DEST_MAP9__NMR_MASK 0x00000001L 1076 #define XPB_RTR_DEST_MAP9__DEST_OFFSET_MASK 0x000FFFFEL 1077 #define XPB_RTR_DEST_MAP9__DEST_SEL_MASK 0x00F00000L 1078 #define XPB_RTR_DEST_MAP9__DEST_SEL_RPB_MASK 0x01000000L 1079 #define XPB_RTR_DEST_MAP9__SIDE_OK_MASK 0x02000000L 1080 #define XPB_RTR_DEST_MAP9__APRTR_SIZE_MASK 0x7C000000L 1081 //XPB_RTR_DEST_MAP10 1082 #define XPB_RTR_DEST_MAP10__NMR__SHIFT 0x0 1083 #define XPB_RTR_DEST_MAP10__DEST_OFFSET__SHIFT 0x1 1084 #define XPB_RTR_DEST_MAP10__DEST_SEL__SHIFT 0x14 1085 #define XPB_RTR_DEST_MAP10__DEST_SEL_RPB__SHIFT 0x18 1086 #define XPB_RTR_DEST_MAP10__SIDE_OK__SHIFT 0x19 1087 #define XPB_RTR_DEST_MAP10__APRTR_SIZE__SHIFT 0x1a 1088 #define XPB_RTR_DEST_MAP10__NMR_MASK 0x00000001L 1089 #define XPB_RTR_DEST_MAP10__DEST_OFFSET_MASK 0x000FFFFEL 1090 #define XPB_RTR_DEST_MAP10__DEST_SEL_MASK 0x00F00000L 1091 #define XPB_RTR_DEST_MAP10__DEST_SEL_RPB_MASK 0x01000000L 1092 #define XPB_RTR_DEST_MAP10__SIDE_OK_MASK 0x02000000L 1093 #define XPB_RTR_DEST_MAP10__APRTR_SIZE_MASK 0x7C000000L 1094 //XPB_RTR_DEST_MAP11 1095 #define XPB_RTR_DEST_MAP11__NMR__SHIFT 0x0 1096 #define XPB_RTR_DEST_MAP11__DEST_OFFSET__SHIFT 0x1 1097 #define XPB_RTR_DEST_MAP11__DEST_SEL__SHIFT 0x14 1098 #define XPB_RTR_DEST_MAP11__DEST_SEL_RPB__SHIFT 0x18 1099 #define XPB_RTR_DEST_MAP11__SIDE_OK__SHIFT 0x19 1100 #define XPB_RTR_DEST_MAP11__APRTR_SIZE__SHIFT 0x1a 1101 #define XPB_RTR_DEST_MAP11__NMR_MASK 0x00000001L 1102 #define XPB_RTR_DEST_MAP11__DEST_OFFSET_MASK 0x000FFFFEL 1103 #define XPB_RTR_DEST_MAP11__DEST_SEL_MASK 0x00F00000L 1104 #define XPB_RTR_DEST_MAP11__DEST_SEL_RPB_MASK 0x01000000L 1105 #define XPB_RTR_DEST_MAP11__SIDE_OK_MASK 0x02000000L 1106 #define XPB_RTR_DEST_MAP11__APRTR_SIZE_MASK 0x7C000000L 1107 //XPB_RTR_DEST_MAP12 1108 #define XPB_RTR_DEST_MAP12__NMR__SHIFT 0x0 1109 #define XPB_RTR_DEST_MAP12__DEST_OFFSET__SHIFT 0x1 1110 #define XPB_RTR_DEST_MAP12__DEST_SEL__SHIFT 0x14 1111 #define XPB_RTR_DEST_MAP12__DEST_SEL_RPB__SHIFT 0x18 1112 #define XPB_RTR_DEST_MAP12__SIDE_OK__SHIFT 0x19 1113 #define XPB_RTR_DEST_MAP12__APRTR_SIZE__SHIFT 0x1a 1114 #define XPB_RTR_DEST_MAP12__NMR_MASK 0x00000001L 1115 #define XPB_RTR_DEST_MAP12__DEST_OFFSET_MASK 0x000FFFFEL 1116 #define XPB_RTR_DEST_MAP12__DEST_SEL_MASK 0x00F00000L 1117 #define XPB_RTR_DEST_MAP12__DEST_SEL_RPB_MASK 0x01000000L 1118 #define XPB_RTR_DEST_MAP12__SIDE_OK_MASK 0x02000000L 1119 #define XPB_RTR_DEST_MAP12__APRTR_SIZE_MASK 0x7C000000L 1120 //XPB_RTR_DEST_MAP13 1121 #define XPB_RTR_DEST_MAP13__NMR__SHIFT 0x0 1122 #define XPB_RTR_DEST_MAP13__DEST_OFFSET__SHIFT 0x1 1123 #define XPB_RTR_DEST_MAP13__DEST_SEL__SHIFT 0x14 1124 #define XPB_RTR_DEST_MAP13__DEST_SEL_RPB__SHIFT 0x18 1125 #define XPB_RTR_DEST_MAP13__SIDE_OK__SHIFT 0x19 1126 #define XPB_RTR_DEST_MAP13__APRTR_SIZE__SHIFT 0x1a 1127 #define XPB_RTR_DEST_MAP13__NMR_MASK 0x00000001L 1128 #define XPB_RTR_DEST_MAP13__DEST_OFFSET_MASK 0x000FFFFEL 1129 #define XPB_RTR_DEST_MAP13__DEST_SEL_MASK 0x00F00000L 1130 #define XPB_RTR_DEST_MAP13__DEST_SEL_RPB_MASK 0x01000000L 1131 #define XPB_RTR_DEST_MAP13__SIDE_OK_MASK 0x02000000L 1132 #define XPB_RTR_DEST_MAP13__APRTR_SIZE_MASK 0x7C000000L 1133 //XPB_CLG_CFG0 1134 #define XPB_CLG_CFG0__WCB_NUM__SHIFT 0x0 1135 #define XPB_CLG_CFG0__LB_TYPE__SHIFT 0x4 1136 #define XPB_CLG_CFG0__P2P_BAR__SHIFT 0x7 1137 #define XPB_CLG_CFG0__HOST_FLUSH__SHIFT 0xa 1138 #define XPB_CLG_CFG0__SIDE_FLUSH__SHIFT 0xe 1139 #define XPB_CLG_CFG0__WCB_NUM_MASK 0x0000000FL 1140 #define XPB_CLG_CFG0__LB_TYPE_MASK 0x00000070L 1141 #define XPB_CLG_CFG0__P2P_BAR_MASK 0x00000380L 1142 #define XPB_CLG_CFG0__HOST_FLUSH_MASK 0x00003C00L 1143 #define XPB_CLG_CFG0__SIDE_FLUSH_MASK 0x0003C000L 1144 //XPB_CLG_CFG1 1145 #define XPB_CLG_CFG1__WCB_NUM__SHIFT 0x0 1146 #define XPB_CLG_CFG1__LB_TYPE__SHIFT 0x4 1147 #define XPB_CLG_CFG1__P2P_BAR__SHIFT 0x7 1148 #define XPB_CLG_CFG1__HOST_FLUSH__SHIFT 0xa 1149 #define XPB_CLG_CFG1__SIDE_FLUSH__SHIFT 0xe 1150 #define XPB_CLG_CFG1__WCB_NUM_MASK 0x0000000FL 1151 #define XPB_CLG_CFG1__LB_TYPE_MASK 0x00000070L 1152 #define XPB_CLG_CFG1__P2P_BAR_MASK 0x00000380L 1153 #define XPB_CLG_CFG1__HOST_FLUSH_MASK 0x00003C00L 1154 #define XPB_CLG_CFG1__SIDE_FLUSH_MASK 0x0003C000L 1155 //XPB_CLG_CFG2 1156 #define XPB_CLG_CFG2__WCB_NUM__SHIFT 0x0 1157 #define XPB_CLG_CFG2__LB_TYPE__SHIFT 0x4 1158 #define XPB_CLG_CFG2__P2P_BAR__SHIFT 0x7 1159 #define XPB_CLG_CFG2__HOST_FLUSH__SHIFT 0xa 1160 #define XPB_CLG_CFG2__SIDE_FLUSH__SHIFT 0xe 1161 #define XPB_CLG_CFG2__WCB_NUM_MASK 0x0000000FL 1162 #define XPB_CLG_CFG2__LB_TYPE_MASK 0x00000070L 1163 #define XPB_CLG_CFG2__P2P_BAR_MASK 0x00000380L 1164 #define XPB_CLG_CFG2__HOST_FLUSH_MASK 0x00003C00L 1165 #define XPB_CLG_CFG2__SIDE_FLUSH_MASK 0x0003C000L 1166 //XPB_CLG_CFG3 1167 #define XPB_CLG_CFG3__WCB_NUM__SHIFT 0x0 1168 #define XPB_CLG_CFG3__LB_TYPE__SHIFT 0x4 1169 #define XPB_CLG_CFG3__P2P_BAR__SHIFT 0x7 1170 #define XPB_CLG_CFG3__HOST_FLUSH__SHIFT 0xa 1171 #define XPB_CLG_CFG3__SIDE_FLUSH__SHIFT 0xe 1172 #define XPB_CLG_CFG3__WCB_NUM_MASK 0x0000000FL 1173 #define XPB_CLG_CFG3__LB_TYPE_MASK 0x00000070L 1174 #define XPB_CLG_CFG3__P2P_BAR_MASK 0x00000380L 1175 #define XPB_CLG_CFG3__HOST_FLUSH_MASK 0x00003C00L 1176 #define XPB_CLG_CFG3__SIDE_FLUSH_MASK 0x0003C000L 1177 //XPB_CLG_CFG4 1178 #define XPB_CLG_CFG4__WCB_NUM__SHIFT 0x0 1179 #define XPB_CLG_CFG4__LB_TYPE__SHIFT 0x4 1180 #define XPB_CLG_CFG4__P2P_BAR__SHIFT 0x7 1181 #define XPB_CLG_CFG4__HOST_FLUSH__SHIFT 0xa 1182 #define XPB_CLG_CFG4__SIDE_FLUSH__SHIFT 0xe 1183 #define XPB_CLG_CFG4__WCB_NUM_MASK 0x0000000FL 1184 #define XPB_CLG_CFG4__LB_TYPE_MASK 0x00000070L 1185 #define XPB_CLG_CFG4__P2P_BAR_MASK 0x00000380L 1186 #define XPB_CLG_CFG4__HOST_FLUSH_MASK 0x00003C00L 1187 #define XPB_CLG_CFG4__SIDE_FLUSH_MASK 0x0003C000L 1188 //XPB_CLG_CFG5 1189 #define XPB_CLG_CFG5__WCB_NUM__SHIFT 0x0 1190 #define XPB_CLG_CFG5__LB_TYPE__SHIFT 0x4 1191 #define XPB_CLG_CFG5__P2P_BAR__SHIFT 0x7 1192 #define XPB_CLG_CFG5__HOST_FLUSH__SHIFT 0xa 1193 #define XPB_CLG_CFG5__SIDE_FLUSH__SHIFT 0xe 1194 #define XPB_CLG_CFG5__WCB_NUM_MASK 0x0000000FL 1195 #define XPB_CLG_CFG5__LB_TYPE_MASK 0x00000070L 1196 #define XPB_CLG_CFG5__P2P_BAR_MASK 0x00000380L 1197 #define XPB_CLG_CFG5__HOST_FLUSH_MASK 0x00003C00L 1198 #define XPB_CLG_CFG5__SIDE_FLUSH_MASK 0x0003C000L 1199 //XPB_CLG_CFG6 1200 #define XPB_CLG_CFG6__WCB_NUM__SHIFT 0x0 1201 #define XPB_CLG_CFG6__LB_TYPE__SHIFT 0x4 1202 #define XPB_CLG_CFG6__P2P_BAR__SHIFT 0x7 1203 #define XPB_CLG_CFG6__HOST_FLUSH__SHIFT 0xa 1204 #define XPB_CLG_CFG6__SIDE_FLUSH__SHIFT 0xe 1205 #define XPB_CLG_CFG6__WCB_NUM_MASK 0x0000000FL 1206 #define XPB_CLG_CFG6__LB_TYPE_MASK 0x00000070L 1207 #define XPB_CLG_CFG6__P2P_BAR_MASK 0x00000380L 1208 #define XPB_CLG_CFG6__HOST_FLUSH_MASK 0x00003C00L 1209 #define XPB_CLG_CFG6__SIDE_FLUSH_MASK 0x0003C000L 1210 //XPB_CLG_CFG7 1211 #define XPB_CLG_CFG7__WCB_NUM__SHIFT 0x0 1212 #define XPB_CLG_CFG7__LB_TYPE__SHIFT 0x4 1213 #define XPB_CLG_CFG7__P2P_BAR__SHIFT 0x7 1214 #define XPB_CLG_CFG7__HOST_FLUSH__SHIFT 0xa 1215 #define XPB_CLG_CFG7__SIDE_FLUSH__SHIFT 0xe 1216 #define XPB_CLG_CFG7__WCB_NUM_MASK 0x0000000FL 1217 #define XPB_CLG_CFG7__LB_TYPE_MASK 0x00000070L 1218 #define XPB_CLG_CFG7__P2P_BAR_MASK 0x00000380L 1219 #define XPB_CLG_CFG7__HOST_FLUSH_MASK 0x00003C00L 1220 #define XPB_CLG_CFG7__SIDE_FLUSH_MASK 0x0003C000L 1221 //XPB_CLG_EXTRA 1222 #define XPB_CLG_EXTRA__CMP0_HIGH__SHIFT 0x0 1223 #define XPB_CLG_EXTRA__CMP0_LOW__SHIFT 0x6 1224 #define XPB_CLG_EXTRA__VLD0__SHIFT 0xb 1225 #define XPB_CLG_EXTRA__CLG0_NUM__SHIFT 0xc 1226 #define XPB_CLG_EXTRA__CMP1_HIGH__SHIFT 0xf 1227 #define XPB_CLG_EXTRA__CMP1_LOW__SHIFT 0x15 1228 #define XPB_CLG_EXTRA__VLD1__SHIFT 0x1a 1229 #define XPB_CLG_EXTRA__CLG1_NUM__SHIFT 0x1b 1230 #define XPB_CLG_EXTRA__CMP0_HIGH_MASK 0x0000003FL 1231 #define XPB_CLG_EXTRA__CMP0_LOW_MASK 0x000007C0L 1232 #define XPB_CLG_EXTRA__VLD0_MASK 0x00000800L 1233 #define XPB_CLG_EXTRA__CLG0_NUM_MASK 0x00007000L 1234 #define XPB_CLG_EXTRA__CMP1_HIGH_MASK 0x001F8000L 1235 #define XPB_CLG_EXTRA__CMP1_LOW_MASK 0x03E00000L 1236 #define XPB_CLG_EXTRA__VLD1_MASK 0x04000000L 1237 #define XPB_CLG_EXTRA__CLG1_NUM_MASK 0x38000000L 1238 //XPB_CLG_EXTRA_MSK 1239 #define XPB_CLG_EXTRA_MSK__MSK0_HIGH__SHIFT 0x0 1240 #define XPB_CLG_EXTRA_MSK__MSK0_LOW__SHIFT 0x6 1241 #define XPB_CLG_EXTRA_MSK__MSK1_HIGH__SHIFT 0xb 1242 #define XPB_CLG_EXTRA_MSK__MSK1_LOW__SHIFT 0x11 1243 #define XPB_CLG_EXTRA_MSK__MSK0_HIGH_MASK 0x0000003FL 1244 #define XPB_CLG_EXTRA_MSK__MSK0_LOW_MASK 0x000007C0L 1245 #define XPB_CLG_EXTRA_MSK__MSK1_HIGH_MASK 0x0001F800L 1246 #define XPB_CLG_EXTRA_MSK__MSK1_LOW_MASK 0x003E0000L 1247 //XPB_LB_ADDR 1248 #define XPB_LB_ADDR__CMP0__SHIFT 0x0 1249 #define XPB_LB_ADDR__MASK0__SHIFT 0xa 1250 #define XPB_LB_ADDR__CMP1__SHIFT 0x14 1251 #define XPB_LB_ADDR__MASK1__SHIFT 0x1a 1252 #define XPB_LB_ADDR__CMP0_MASK 0x000003FFL 1253 #define XPB_LB_ADDR__MASK0_MASK 0x000FFC00L 1254 #define XPB_LB_ADDR__CMP1_MASK 0x03F00000L 1255 #define XPB_LB_ADDR__MASK1_MASK 0xFC000000L 1256 //XPB_WCB_STS 1257 #define XPB_WCB_STS__PBUF_VLD__SHIFT 0x0 1258 #define XPB_WCB_STS__WCB_HST_DATA_BUF_CNT__SHIFT 0x10 1259 #define XPB_WCB_STS__WCB_SID_DATA_BUF_CNT__SHIFT 0x17 1260 #define XPB_WCB_STS__PBUF_VLD_MASK 0x0000FFFFL 1261 #define XPB_WCB_STS__WCB_HST_DATA_BUF_CNT_MASK 0x007F0000L 1262 #define XPB_WCB_STS__WCB_SID_DATA_BUF_CNT_MASK 0x3F800000L 1263 //XPB_HST_CFG 1264 #define XPB_HST_CFG__BAR_UP_WR_CMD__SHIFT 0x0 1265 #define XPB_HST_CFG__BAR_UP_WR_CMD_MASK 0x00000001L 1266 //XPB_P2P_BAR_CFG 1267 #define XPB_P2P_BAR_CFG__ADDR_SIZE__SHIFT 0x0 1268 #define XPB_P2P_BAR_CFG__SEND_BAR__SHIFT 0x4 1269 #define XPB_P2P_BAR_CFG__SNOOP__SHIFT 0x6 1270 #define XPB_P2P_BAR_CFG__SEND_DIS__SHIFT 0x7 1271 #define XPB_P2P_BAR_CFG__COMPRESS_DIS__SHIFT 0x8 1272 #define XPB_P2P_BAR_CFG__UPDATE_DIS__SHIFT 0x9 1273 #define XPB_P2P_BAR_CFG__REGBAR_FROM_SYSBAR__SHIFT 0xa 1274 #define XPB_P2P_BAR_CFG__RD_EN__SHIFT 0xb 1275 #define XPB_P2P_BAR_CFG__ATC_TRANSLATED__SHIFT 0xc 1276 #define XPB_P2P_BAR_CFG__ADDR_SIZE_MASK 0x0000000FL 1277 #define XPB_P2P_BAR_CFG__SEND_BAR_MASK 0x00000030L 1278 #define XPB_P2P_BAR_CFG__SNOOP_MASK 0x00000040L 1279 #define XPB_P2P_BAR_CFG__SEND_DIS_MASK 0x00000080L 1280 #define XPB_P2P_BAR_CFG__COMPRESS_DIS_MASK 0x00000100L 1281 #define XPB_P2P_BAR_CFG__UPDATE_DIS_MASK 0x00000200L 1282 #define XPB_P2P_BAR_CFG__REGBAR_FROM_SYSBAR_MASK 0x00000400L 1283 #define XPB_P2P_BAR_CFG__RD_EN_MASK 0x00000800L 1284 #define XPB_P2P_BAR_CFG__ATC_TRANSLATED_MASK 0x00001000L 1285 //XPB_P2P_BAR0 1286 #define XPB_P2P_BAR0__HOST_FLUSH__SHIFT 0x0 1287 #define XPB_P2P_BAR0__REG_SYS_BAR__SHIFT 0x4 1288 #define XPB_P2P_BAR0__MEM_SYS_BAR__SHIFT 0x8 1289 #define XPB_P2P_BAR0__VALID__SHIFT 0xc 1290 #define XPB_P2P_BAR0__SEND_DIS__SHIFT 0xd 1291 #define XPB_P2P_BAR0__COMPRESS_DIS__SHIFT 0xe 1292 #define XPB_P2P_BAR0__RESERVED__SHIFT 0xf 1293 #define XPB_P2P_BAR0__ADDRESS__SHIFT 0x10 1294 #define XPB_P2P_BAR0__HOST_FLUSH_MASK 0x0000000FL 1295 #define XPB_P2P_BAR0__REG_SYS_BAR_MASK 0x000000F0L 1296 #define XPB_P2P_BAR0__MEM_SYS_BAR_MASK 0x00000F00L 1297 #define XPB_P2P_BAR0__VALID_MASK 0x00001000L 1298 #define XPB_P2P_BAR0__SEND_DIS_MASK 0x00002000L 1299 #define XPB_P2P_BAR0__COMPRESS_DIS_MASK 0x00004000L 1300 #define XPB_P2P_BAR0__RESERVED_MASK 0x00008000L 1301 #define XPB_P2P_BAR0__ADDRESS_MASK 0xFFFF0000L 1302 //XPB_P2P_BAR1 1303 #define XPB_P2P_BAR1__HOST_FLUSH__SHIFT 0x0 1304 #define XPB_P2P_BAR1__REG_SYS_BAR__SHIFT 0x4 1305 #define XPB_P2P_BAR1__MEM_SYS_BAR__SHIFT 0x8 1306 #define XPB_P2P_BAR1__VALID__SHIFT 0xc 1307 #define XPB_P2P_BAR1__SEND_DIS__SHIFT 0xd 1308 #define XPB_P2P_BAR1__COMPRESS_DIS__SHIFT 0xe 1309 #define XPB_P2P_BAR1__RESERVED__SHIFT 0xf 1310 #define XPB_P2P_BAR1__ADDRESS__SHIFT 0x10 1311 #define XPB_P2P_BAR1__HOST_FLUSH_MASK 0x0000000FL 1312 #define XPB_P2P_BAR1__REG_SYS_BAR_MASK 0x000000F0L 1313 #define XPB_P2P_BAR1__MEM_SYS_BAR_MASK 0x00000F00L 1314 #define XPB_P2P_BAR1__VALID_MASK 0x00001000L 1315 #define XPB_P2P_BAR1__SEND_DIS_MASK 0x00002000L 1316 #define XPB_P2P_BAR1__COMPRESS_DIS_MASK 0x00004000L 1317 #define XPB_P2P_BAR1__RESERVED_MASK 0x00008000L 1318 #define XPB_P2P_BAR1__ADDRESS_MASK 0xFFFF0000L 1319 //XPB_P2P_BAR2 1320 #define XPB_P2P_BAR2__HOST_FLUSH__SHIFT 0x0 1321 #define XPB_P2P_BAR2__REG_SYS_BAR__SHIFT 0x4 1322 #define XPB_P2P_BAR2__MEM_SYS_BAR__SHIFT 0x8 1323 #define XPB_P2P_BAR2__VALID__SHIFT 0xc 1324 #define XPB_P2P_BAR2__SEND_DIS__SHIFT 0xd 1325 #define XPB_P2P_BAR2__COMPRESS_DIS__SHIFT 0xe 1326 #define XPB_P2P_BAR2__RESERVED__SHIFT 0xf 1327 #define XPB_P2P_BAR2__ADDRESS__SHIFT 0x10 1328 #define XPB_P2P_BAR2__HOST_FLUSH_MASK 0x0000000FL 1329 #define XPB_P2P_BAR2__REG_SYS_BAR_MASK 0x000000F0L 1330 #define XPB_P2P_BAR2__MEM_SYS_BAR_MASK 0x00000F00L 1331 #define XPB_P2P_BAR2__VALID_MASK 0x00001000L 1332 #define XPB_P2P_BAR2__SEND_DIS_MASK 0x00002000L 1333 #define XPB_P2P_BAR2__COMPRESS_DIS_MASK 0x00004000L 1334 #define XPB_P2P_BAR2__RESERVED_MASK 0x00008000L 1335 #define XPB_P2P_BAR2__ADDRESS_MASK 0xFFFF0000L 1336 //XPB_P2P_BAR3 1337 #define XPB_P2P_BAR3__HOST_FLUSH__SHIFT 0x0 1338 #define XPB_P2P_BAR3__REG_SYS_BAR__SHIFT 0x4 1339 #define XPB_P2P_BAR3__MEM_SYS_BAR__SHIFT 0x8 1340 #define XPB_P2P_BAR3__VALID__SHIFT 0xc 1341 #define XPB_P2P_BAR3__SEND_DIS__SHIFT 0xd 1342 #define XPB_P2P_BAR3__COMPRESS_DIS__SHIFT 0xe 1343 #define XPB_P2P_BAR3__RESERVED__SHIFT 0xf 1344 #define XPB_P2P_BAR3__ADDRESS__SHIFT 0x10 1345 #define XPB_P2P_BAR3__HOST_FLUSH_MASK 0x0000000FL 1346 #define XPB_P2P_BAR3__REG_SYS_BAR_MASK 0x000000F0L 1347 #define XPB_P2P_BAR3__MEM_SYS_BAR_MASK 0x00000F00L 1348 #define XPB_P2P_BAR3__VALID_MASK 0x00001000L 1349 #define XPB_P2P_BAR3__SEND_DIS_MASK 0x00002000L 1350 #define XPB_P2P_BAR3__COMPRESS_DIS_MASK 0x00004000L 1351 #define XPB_P2P_BAR3__RESERVED_MASK 0x00008000L 1352 #define XPB_P2P_BAR3__ADDRESS_MASK 0xFFFF0000L 1353 //XPB_P2P_BAR4 1354 #define XPB_P2P_BAR4__HOST_FLUSH__SHIFT 0x0 1355 #define XPB_P2P_BAR4__REG_SYS_BAR__SHIFT 0x4 1356 #define XPB_P2P_BAR4__MEM_SYS_BAR__SHIFT 0x8 1357 #define XPB_P2P_BAR4__VALID__SHIFT 0xc 1358 #define XPB_P2P_BAR4__SEND_DIS__SHIFT 0xd 1359 #define XPB_P2P_BAR4__COMPRESS_DIS__SHIFT 0xe 1360 #define XPB_P2P_BAR4__RESERVED__SHIFT 0xf 1361 #define XPB_P2P_BAR4__ADDRESS__SHIFT 0x10 1362 #define XPB_P2P_BAR4__HOST_FLUSH_MASK 0x0000000FL 1363 #define XPB_P2P_BAR4__REG_SYS_BAR_MASK 0x000000F0L 1364 #define XPB_P2P_BAR4__MEM_SYS_BAR_MASK 0x00000F00L 1365 #define XPB_P2P_BAR4__VALID_MASK 0x00001000L 1366 #define XPB_P2P_BAR4__SEND_DIS_MASK 0x00002000L 1367 #define XPB_P2P_BAR4__COMPRESS_DIS_MASK 0x00004000L 1368 #define XPB_P2P_BAR4__RESERVED_MASK 0x00008000L 1369 #define XPB_P2P_BAR4__ADDRESS_MASK 0xFFFF0000L 1370 //XPB_P2P_BAR5 1371 #define XPB_P2P_BAR5__HOST_FLUSH__SHIFT 0x0 1372 #define XPB_P2P_BAR5__REG_SYS_BAR__SHIFT 0x4 1373 #define XPB_P2P_BAR5__MEM_SYS_BAR__SHIFT 0x8 1374 #define XPB_P2P_BAR5__VALID__SHIFT 0xc 1375 #define XPB_P2P_BAR5__SEND_DIS__SHIFT 0xd 1376 #define XPB_P2P_BAR5__COMPRESS_DIS__SHIFT 0xe 1377 #define XPB_P2P_BAR5__RESERVED__SHIFT 0xf 1378 #define XPB_P2P_BAR5__ADDRESS__SHIFT 0x10 1379 #define XPB_P2P_BAR5__HOST_FLUSH_MASK 0x0000000FL 1380 #define XPB_P2P_BAR5__REG_SYS_BAR_MASK 0x000000F0L 1381 #define XPB_P2P_BAR5__MEM_SYS_BAR_MASK 0x00000F00L 1382 #define XPB_P2P_BAR5__VALID_MASK 0x00001000L 1383 #define XPB_P2P_BAR5__SEND_DIS_MASK 0x00002000L 1384 #define XPB_P2P_BAR5__COMPRESS_DIS_MASK 0x00004000L 1385 #define XPB_P2P_BAR5__RESERVED_MASK 0x00008000L 1386 #define XPB_P2P_BAR5__ADDRESS_MASK 0xFFFF0000L 1387 //XPB_P2P_BAR6 1388 #define XPB_P2P_BAR6__HOST_FLUSH__SHIFT 0x0 1389 #define XPB_P2P_BAR6__REG_SYS_BAR__SHIFT 0x4 1390 #define XPB_P2P_BAR6__MEM_SYS_BAR__SHIFT 0x8 1391 #define XPB_P2P_BAR6__VALID__SHIFT 0xc 1392 #define XPB_P2P_BAR6__SEND_DIS__SHIFT 0xd 1393 #define XPB_P2P_BAR6__COMPRESS_DIS__SHIFT 0xe 1394 #define XPB_P2P_BAR6__RESERVED__SHIFT 0xf 1395 #define XPB_P2P_BAR6__ADDRESS__SHIFT 0x10 1396 #define XPB_P2P_BAR6__HOST_FLUSH_MASK 0x0000000FL 1397 #define XPB_P2P_BAR6__REG_SYS_BAR_MASK 0x000000F0L 1398 #define XPB_P2P_BAR6__MEM_SYS_BAR_MASK 0x00000F00L 1399 #define XPB_P2P_BAR6__VALID_MASK 0x00001000L 1400 #define XPB_P2P_BAR6__SEND_DIS_MASK 0x00002000L 1401 #define XPB_P2P_BAR6__COMPRESS_DIS_MASK 0x00004000L 1402 #define XPB_P2P_BAR6__RESERVED_MASK 0x00008000L 1403 #define XPB_P2P_BAR6__ADDRESS_MASK 0xFFFF0000L 1404 //XPB_P2P_BAR7 1405 #define XPB_P2P_BAR7__HOST_FLUSH__SHIFT 0x0 1406 #define XPB_P2P_BAR7__REG_SYS_BAR__SHIFT 0x4 1407 #define XPB_P2P_BAR7__MEM_SYS_BAR__SHIFT 0x8 1408 #define XPB_P2P_BAR7__VALID__SHIFT 0xc 1409 #define XPB_P2P_BAR7__SEND_DIS__SHIFT 0xd 1410 #define XPB_P2P_BAR7__COMPRESS_DIS__SHIFT 0xe 1411 #define XPB_P2P_BAR7__RESERVED__SHIFT 0xf 1412 #define XPB_P2P_BAR7__ADDRESS__SHIFT 0x10 1413 #define XPB_P2P_BAR7__HOST_FLUSH_MASK 0x0000000FL 1414 #define XPB_P2P_BAR7__REG_SYS_BAR_MASK 0x000000F0L 1415 #define XPB_P2P_BAR7__MEM_SYS_BAR_MASK 0x00000F00L 1416 #define XPB_P2P_BAR7__VALID_MASK 0x00001000L 1417 #define XPB_P2P_BAR7__SEND_DIS_MASK 0x00002000L 1418 #define XPB_P2P_BAR7__COMPRESS_DIS_MASK 0x00004000L 1419 #define XPB_P2P_BAR7__RESERVED_MASK 0x00008000L 1420 #define XPB_P2P_BAR7__ADDRESS_MASK 0xFFFF0000L 1421 //XPB_P2P_BAR_SETUP 1422 #define XPB_P2P_BAR_SETUP__SEL__SHIFT 0x0 1423 #define XPB_P2P_BAR_SETUP__REG_SYS_BAR__SHIFT 0x8 1424 #define XPB_P2P_BAR_SETUP__VALID__SHIFT 0xc 1425 #define XPB_P2P_BAR_SETUP__SEND_DIS__SHIFT 0xd 1426 #define XPB_P2P_BAR_SETUP__COMPRESS_DIS__SHIFT 0xe 1427 #define XPB_P2P_BAR_SETUP__RESERVED__SHIFT 0xf 1428 #define XPB_P2P_BAR_SETUP__ADDRESS__SHIFT 0x10 1429 #define XPB_P2P_BAR_SETUP__SEL_MASK 0x000000FFL 1430 #define XPB_P2P_BAR_SETUP__REG_SYS_BAR_MASK 0x00000F00L 1431 #define XPB_P2P_BAR_SETUP__VALID_MASK 0x00001000L 1432 #define XPB_P2P_BAR_SETUP__SEND_DIS_MASK 0x00002000L 1433 #define XPB_P2P_BAR_SETUP__COMPRESS_DIS_MASK 0x00004000L 1434 #define XPB_P2P_BAR_SETUP__RESERVED_MASK 0x00008000L 1435 #define XPB_P2P_BAR_SETUP__ADDRESS_MASK 0xFFFF0000L 1436 //XPB_P2P_BAR_DELTA_ABOVE 1437 #define XPB_P2P_BAR_DELTA_ABOVE__EN__SHIFT 0x0 1438 #define XPB_P2P_BAR_DELTA_ABOVE__DELTA__SHIFT 0x8 1439 #define XPB_P2P_BAR_DELTA_ABOVE__EN_MASK 0x000000FFL 1440 #define XPB_P2P_BAR_DELTA_ABOVE__DELTA_MASK 0x0FFFFF00L 1441 //XPB_P2P_BAR_DELTA_BELOW 1442 #define XPB_P2P_BAR_DELTA_BELOW__EN__SHIFT 0x0 1443 #define XPB_P2P_BAR_DELTA_BELOW__DELTA__SHIFT 0x8 1444 #define XPB_P2P_BAR_DELTA_BELOW__EN_MASK 0x000000FFL 1445 #define XPB_P2P_BAR_DELTA_BELOW__DELTA_MASK 0x0FFFFF00L 1446 //XPB_PEER_SYS_BAR0 1447 #define XPB_PEER_SYS_BAR0__VALID__SHIFT 0x0 1448 #define XPB_PEER_SYS_BAR0__ADDR__SHIFT 0x1 1449 #define XPB_PEER_SYS_BAR0__VALID_MASK 0x00000001L 1450 #define XPB_PEER_SYS_BAR0__ADDR_MASK 0xFFFFFFFEL 1451 //XPB_PEER_SYS_BAR1 1452 #define XPB_PEER_SYS_BAR1__VALID__SHIFT 0x0 1453 #define XPB_PEER_SYS_BAR1__ADDR__SHIFT 0x1 1454 #define XPB_PEER_SYS_BAR1__VALID_MASK 0x00000001L 1455 #define XPB_PEER_SYS_BAR1__ADDR_MASK 0xFFFFFFFEL 1456 //XPB_PEER_SYS_BAR2 1457 #define XPB_PEER_SYS_BAR2__VALID__SHIFT 0x0 1458 #define XPB_PEER_SYS_BAR2__ADDR__SHIFT 0x1 1459 #define XPB_PEER_SYS_BAR2__VALID_MASK 0x00000001L 1460 #define XPB_PEER_SYS_BAR2__ADDR_MASK 0xFFFFFFFEL 1461 //XPB_PEER_SYS_BAR3 1462 #define XPB_PEER_SYS_BAR3__VALID__SHIFT 0x0 1463 #define XPB_PEER_SYS_BAR3__ADDR__SHIFT 0x1 1464 #define XPB_PEER_SYS_BAR3__VALID_MASK 0x00000001L 1465 #define XPB_PEER_SYS_BAR3__ADDR_MASK 0xFFFFFFFEL 1466 //XPB_PEER_SYS_BAR4 1467 #define XPB_PEER_SYS_BAR4__VALID__SHIFT 0x0 1468 #define XPB_PEER_SYS_BAR4__ADDR__SHIFT 0x1 1469 #define XPB_PEER_SYS_BAR4__VALID_MASK 0x00000001L 1470 #define XPB_PEER_SYS_BAR4__ADDR_MASK 0xFFFFFFFEL 1471 //XPB_PEER_SYS_BAR5 1472 #define XPB_PEER_SYS_BAR5__VALID__SHIFT 0x0 1473 #define XPB_PEER_SYS_BAR5__ADDR__SHIFT 0x1 1474 #define XPB_PEER_SYS_BAR5__VALID_MASK 0x00000001L 1475 #define XPB_PEER_SYS_BAR5__ADDR_MASK 0xFFFFFFFEL 1476 //XPB_PEER_SYS_BAR6 1477 #define XPB_PEER_SYS_BAR6__VALID__SHIFT 0x0 1478 #define XPB_PEER_SYS_BAR6__ADDR__SHIFT 0x1 1479 #define XPB_PEER_SYS_BAR6__VALID_MASK 0x00000001L 1480 #define XPB_PEER_SYS_BAR6__ADDR_MASK 0xFFFFFFFEL 1481 //XPB_PEER_SYS_BAR7 1482 #define XPB_PEER_SYS_BAR7__VALID__SHIFT 0x0 1483 #define XPB_PEER_SYS_BAR7__ADDR__SHIFT 0x1 1484 #define XPB_PEER_SYS_BAR7__VALID_MASK 0x00000001L 1485 #define XPB_PEER_SYS_BAR7__ADDR_MASK 0xFFFFFFFEL 1486 //XPB_PEER_SYS_BAR8 1487 #define XPB_PEER_SYS_BAR8__VALID__SHIFT 0x0 1488 #define XPB_PEER_SYS_BAR8__ADDR__SHIFT 0x1 1489 #define XPB_PEER_SYS_BAR8__VALID_MASK 0x00000001L 1490 #define XPB_PEER_SYS_BAR8__ADDR_MASK 0xFFFFFFFEL 1491 //XPB_PEER_SYS_BAR9 1492 #define XPB_PEER_SYS_BAR9__VALID__SHIFT 0x0 1493 #define XPB_PEER_SYS_BAR9__ADDR__SHIFT 0x1 1494 #define XPB_PEER_SYS_BAR9__VALID_MASK 0x00000001L 1495 #define XPB_PEER_SYS_BAR9__ADDR_MASK 0xFFFFFFFEL 1496 //XPB_PEER_SYS_BAR10 1497 #define XPB_PEER_SYS_BAR10__VALID__SHIFT 0x0 1498 #define XPB_PEER_SYS_BAR10__ADDR__SHIFT 0x1 1499 #define XPB_PEER_SYS_BAR10__VALID_MASK 0x00000001L 1500 #define XPB_PEER_SYS_BAR10__ADDR_MASK 0xFFFFFFFEL 1501 //XPB_PEER_SYS_BAR11 1502 #define XPB_PEER_SYS_BAR11__VALID__SHIFT 0x0 1503 #define XPB_PEER_SYS_BAR11__ADDR__SHIFT 0x1 1504 #define XPB_PEER_SYS_BAR11__VALID_MASK 0x00000001L 1505 #define XPB_PEER_SYS_BAR11__ADDR_MASK 0xFFFFFFFEL 1506 //XPB_PEER_SYS_BAR12 1507 #define XPB_PEER_SYS_BAR12__VALID__SHIFT 0x0 1508 #define XPB_PEER_SYS_BAR12__ADDR__SHIFT 0x1 1509 #define XPB_PEER_SYS_BAR12__VALID_MASK 0x00000001L 1510 #define XPB_PEER_SYS_BAR12__ADDR_MASK 0xFFFFFFFEL 1511 //XPB_PEER_SYS_BAR13 1512 #define XPB_PEER_SYS_BAR13__VALID__SHIFT 0x0 1513 #define XPB_PEER_SYS_BAR13__ADDR__SHIFT 0x1 1514 #define XPB_PEER_SYS_BAR13__VALID_MASK 0x00000001L 1515 #define XPB_PEER_SYS_BAR13__ADDR_MASK 0xFFFFFFFEL 1516 //XPB_CLK_GAT 1517 #define XPB_CLK_GAT__ONDLY__SHIFT 0x0 1518 #define XPB_CLK_GAT__OFFDLY__SHIFT 0x6 1519 #define XPB_CLK_GAT__RDYDLY__SHIFT 0xc 1520 #define XPB_CLK_GAT__ENABLE__SHIFT 0x12 1521 #define XPB_CLK_GAT__MEM_LS_ENABLE__SHIFT 0x13 1522 #define XPB_CLK_GAT__ONDLY_MASK 0x0000003FL 1523 #define XPB_CLK_GAT__OFFDLY_MASK 0x00000FC0L 1524 #define XPB_CLK_GAT__RDYDLY_MASK 0x0003F000L 1525 #define XPB_CLK_GAT__ENABLE_MASK 0x00040000L 1526 #define XPB_CLK_GAT__MEM_LS_ENABLE_MASK 0x00080000L 1527 //XPB_INTF_CFG 1528 #define XPB_INTF_CFG__RPB_WRREQ_CRD__SHIFT 0x0 1529 #define XPB_INTF_CFG__MC_WRRET_ASK__SHIFT 0x8 1530 #define XPB_INTF_CFG__XSP_REQ_CRD__SHIFT 0x10 1531 #define XPB_INTF_CFG__P2P_WR_CHAIN_BREAK__SHIFT 0x17 1532 #define XPB_INTF_CFG__XSP_SNOOP_SEL__SHIFT 0x1b 1533 #define XPB_INTF_CFG__XSP_SNOOP_VAL__SHIFT 0x1d 1534 #define XPB_INTF_CFG__XSP_ORDERING_SEL__SHIFT 0x1e 1535 #define XPB_INTF_CFG__XSP_ORDERING_VAL__SHIFT 0x1f 1536 #define XPB_INTF_CFG__RPB_WRREQ_CRD_MASK 0x000000FFL 1537 #define XPB_INTF_CFG__MC_WRRET_ASK_MASK 0x0000FF00L 1538 #define XPB_INTF_CFG__XSP_REQ_CRD_MASK 0x007F0000L 1539 #define XPB_INTF_CFG__P2P_WR_CHAIN_BREAK_MASK 0x00800000L 1540 #define XPB_INTF_CFG__XSP_SNOOP_SEL_MASK 0x18000000L 1541 #define XPB_INTF_CFG__XSP_SNOOP_VAL_MASK 0x20000000L 1542 #define XPB_INTF_CFG__XSP_ORDERING_SEL_MASK 0x40000000L 1543 #define XPB_INTF_CFG__XSP_ORDERING_VAL_MASK 0x80000000L 1544 //XPB_INTF_STS 1545 #define XPB_INTF_STS__RPB_WRREQ_CRD__SHIFT 0x0 1546 #define XPB_INTF_STS__XSP_REQ_CRD__SHIFT 0x8 1547 #define XPB_INTF_STS__HOP_DATA_BUF_FULL__SHIFT 0xf 1548 #define XPB_INTF_STS__HOP_ATTR_BUF_FULL__SHIFT 0x10 1549 #define XPB_INTF_STS__CNS_BUF_FULL__SHIFT 0x11 1550 #define XPB_INTF_STS__CNS_BUF_BUSY__SHIFT 0x12 1551 #define XPB_INTF_STS__RPB_RDREQ_CRD__SHIFT 0x13 1552 #define XPB_INTF_STS__RPB_WRREQ_CRD_MASK 0x000000FFL 1553 #define XPB_INTF_STS__XSP_REQ_CRD_MASK 0x00007F00L 1554 #define XPB_INTF_STS__HOP_DATA_BUF_FULL_MASK 0x00008000L 1555 #define XPB_INTF_STS__HOP_ATTR_BUF_FULL_MASK 0x00010000L 1556 #define XPB_INTF_STS__CNS_BUF_FULL_MASK 0x00020000L 1557 #define XPB_INTF_STS__CNS_BUF_BUSY_MASK 0x00040000L 1558 #define XPB_INTF_STS__RPB_RDREQ_CRD_MASK 0x07F80000L 1559 //XPB_PIPE_STS 1560 #define XPB_PIPE_STS__WCB_ANY_PBUF__SHIFT 0x0 1561 #define XPB_PIPE_STS__WCB_HST_DATA_BUF_CNT__SHIFT 0x1 1562 #define XPB_PIPE_STS__WCB_SID_DATA_BUF_CNT__SHIFT 0x8 1563 #define XPB_PIPE_STS__WCB_HST_RD_PTR_BUF_FULL__SHIFT 0xf 1564 #define XPB_PIPE_STS__WCB_SID_RD_PTR_BUF_FULL__SHIFT 0x10 1565 #define XPB_PIPE_STS__WCB_HST_REQ_FIFO_FULL__SHIFT 0x11 1566 #define XPB_PIPE_STS__WCB_SID_REQ_FIFO_FULL__SHIFT 0x12 1567 #define XPB_PIPE_STS__WCB_HST_REQ_OBUF_FULL__SHIFT 0x13 1568 #define XPB_PIPE_STS__WCB_SID_REQ_OBUF_FULL__SHIFT 0x14 1569 #define XPB_PIPE_STS__WCB_HST_DATA_OBUF_FULL__SHIFT 0x15 1570 #define XPB_PIPE_STS__WCB_SID_DATA_OBUF_FULL__SHIFT 0x16 1571 #define XPB_PIPE_STS__RET_BUF_FULL__SHIFT 0x17 1572 #define XPB_PIPE_STS__XPB_CLK_BUSY_BITS__SHIFT 0x18 1573 #define XPB_PIPE_STS__WCB_ANY_PBUF_MASK 0x00000001L 1574 #define XPB_PIPE_STS__WCB_HST_DATA_BUF_CNT_MASK 0x000000FEL 1575 #define XPB_PIPE_STS__WCB_SID_DATA_BUF_CNT_MASK 0x00007F00L 1576 #define XPB_PIPE_STS__WCB_HST_RD_PTR_BUF_FULL_MASK 0x00008000L 1577 #define XPB_PIPE_STS__WCB_SID_RD_PTR_BUF_FULL_MASK 0x00010000L 1578 #define XPB_PIPE_STS__WCB_HST_REQ_FIFO_FULL_MASK 0x00020000L 1579 #define XPB_PIPE_STS__WCB_SID_REQ_FIFO_FULL_MASK 0x00040000L 1580 #define XPB_PIPE_STS__WCB_HST_REQ_OBUF_FULL_MASK 0x00080000L 1581 #define XPB_PIPE_STS__WCB_SID_REQ_OBUF_FULL_MASK 0x00100000L 1582 #define XPB_PIPE_STS__WCB_HST_DATA_OBUF_FULL_MASK 0x00200000L 1583 #define XPB_PIPE_STS__WCB_SID_DATA_OBUF_FULL_MASK 0x00400000L 1584 #define XPB_PIPE_STS__RET_BUF_FULL_MASK 0x00800000L 1585 #define XPB_PIPE_STS__XPB_CLK_BUSY_BITS_MASK 0xFF000000L 1586 //XPB_SUB_CTRL 1587 #define XPB_SUB_CTRL__WRREQ_BYPASS_XPB__SHIFT 0x0 1588 #define XPB_SUB_CTRL__STALL_CNS_RTR_REQ__SHIFT 0x1 1589 #define XPB_SUB_CTRL__STALL_RTR_RPB_WRREQ__SHIFT 0x2 1590 #define XPB_SUB_CTRL__STALL_RTR_MAP_REQ__SHIFT 0x3 1591 #define XPB_SUB_CTRL__STALL_MAP_WCB_REQ__SHIFT 0x4 1592 #define XPB_SUB_CTRL__STALL_WCB_SID_REQ__SHIFT 0x5 1593 #define XPB_SUB_CTRL__STALL_MC_XSP_REQ_SEND__SHIFT 0x6 1594 #define XPB_SUB_CTRL__STALL_WCB_HST_REQ__SHIFT 0x7 1595 #define XPB_SUB_CTRL__STALL_HST_HOP_REQ__SHIFT 0x8 1596 #define XPB_SUB_CTRL__STALL_XPB_RPB_REQ_ATTR__SHIFT 0x9 1597 #define XPB_SUB_CTRL__RESET_CNS__SHIFT 0xa 1598 #define XPB_SUB_CTRL__RESET_RTR__SHIFT 0xb 1599 #define XPB_SUB_CTRL__RESET_RET__SHIFT 0xc 1600 #define XPB_SUB_CTRL__RESET_MAP__SHIFT 0xd 1601 #define XPB_SUB_CTRL__RESET_WCB__SHIFT 0xe 1602 #define XPB_SUB_CTRL__RESET_HST__SHIFT 0xf 1603 #define XPB_SUB_CTRL__RESET_HOP__SHIFT 0x10 1604 #define XPB_SUB_CTRL__RESET_SID__SHIFT 0x11 1605 #define XPB_SUB_CTRL__RESET_SRB__SHIFT 0x12 1606 #define XPB_SUB_CTRL__RESET_CGR__SHIFT 0x13 1607 #define XPB_SUB_CTRL__WRREQ_BYPASS_XPB_MASK 0x00000001L 1608 #define XPB_SUB_CTRL__STALL_CNS_RTR_REQ_MASK 0x00000002L 1609 #define XPB_SUB_CTRL__STALL_RTR_RPB_WRREQ_MASK 0x00000004L 1610 #define XPB_SUB_CTRL__STALL_RTR_MAP_REQ_MASK 0x00000008L 1611 #define XPB_SUB_CTRL__STALL_MAP_WCB_REQ_MASK 0x00000010L 1612 #define XPB_SUB_CTRL__STALL_WCB_SID_REQ_MASK 0x00000020L 1613 #define XPB_SUB_CTRL__STALL_MC_XSP_REQ_SEND_MASK 0x00000040L 1614 #define XPB_SUB_CTRL__STALL_WCB_HST_REQ_MASK 0x00000080L 1615 #define XPB_SUB_CTRL__STALL_HST_HOP_REQ_MASK 0x00000100L 1616 #define XPB_SUB_CTRL__STALL_XPB_RPB_REQ_ATTR_MASK 0x00000200L 1617 #define XPB_SUB_CTRL__RESET_CNS_MASK 0x00000400L 1618 #define XPB_SUB_CTRL__RESET_RTR_MASK 0x00000800L 1619 #define XPB_SUB_CTRL__RESET_RET_MASK 0x00001000L 1620 #define XPB_SUB_CTRL__RESET_MAP_MASK 0x00002000L 1621 #define XPB_SUB_CTRL__RESET_WCB_MASK 0x00004000L 1622 #define XPB_SUB_CTRL__RESET_HST_MASK 0x00008000L 1623 #define XPB_SUB_CTRL__RESET_HOP_MASK 0x00010000L 1624 #define XPB_SUB_CTRL__RESET_SID_MASK 0x00020000L 1625 #define XPB_SUB_CTRL__RESET_SRB_MASK 0x00040000L 1626 #define XPB_SUB_CTRL__RESET_CGR_MASK 0x00080000L 1627 //XPB_MAP_INVERT_FLUSH_NUM_LSB 1628 #define XPB_MAP_INVERT_FLUSH_NUM_LSB__ALTER_FLUSH_NUM__SHIFT 0x0 1629 #define XPB_MAP_INVERT_FLUSH_NUM_LSB__ALTER_FLUSH_NUM_MASK 0x0000FFFFL 1630 //XPB_PERF_KNOBS 1631 #define XPB_PERF_KNOBS__CNS_FIFO_DEPTH__SHIFT 0x0 1632 #define XPB_PERF_KNOBS__WCB_HST_FIFO_DEPTH__SHIFT 0x6 1633 #define XPB_PERF_KNOBS__WCB_SID_FIFO_DEPTH__SHIFT 0xc 1634 #define XPB_PERF_KNOBS__CNS_FIFO_DEPTH_MASK 0x0000003FL 1635 #define XPB_PERF_KNOBS__WCB_HST_FIFO_DEPTH_MASK 0x00000FC0L 1636 #define XPB_PERF_KNOBS__WCB_SID_FIFO_DEPTH_MASK 0x0003F000L 1637 //XPB_STICKY 1638 #define XPB_STICKY__BITS__SHIFT 0x0 1639 #define XPB_STICKY__BITS_MASK 0xFFFFFFFFL 1640 //XPB_STICKY_W1C 1641 #define XPB_STICKY_W1C__BITS__SHIFT 0x0 1642 #define XPB_STICKY_W1C__BITS_MASK 0xFFFFFFFFL 1643 //XPB_MISC_CFG 1644 #define XPB_MISC_CFG__FIELDNAME0__SHIFT 0x0 1645 #define XPB_MISC_CFG__FIELDNAME1__SHIFT 0x8 1646 #define XPB_MISC_CFG__FIELDNAME2__SHIFT 0x10 1647 #define XPB_MISC_CFG__FIELDNAME3__SHIFT 0x18 1648 #define XPB_MISC_CFG__TRIGGERNAME__SHIFT 0x1f 1649 #define XPB_MISC_CFG__FIELDNAME0_MASK 0x000000FFL 1650 #define XPB_MISC_CFG__FIELDNAME1_MASK 0x0000FF00L 1651 #define XPB_MISC_CFG__FIELDNAME2_MASK 0x00FF0000L 1652 #define XPB_MISC_CFG__FIELDNAME3_MASK 0x7F000000L 1653 #define XPB_MISC_CFG__TRIGGERNAME_MASK 0x80000000L 1654 //XPB_INTF_CFG2 1655 #define XPB_INTF_CFG2__RPB_RDREQ_CRD__SHIFT 0x0 1656 #define XPB_INTF_CFG2__RPB_RDREQ_CRD_MASK 0x000000FFL 1657 //XPB_CLG_EXTRA_RD 1658 #define XPB_CLG_EXTRA_RD__CMP0_HIGH__SHIFT 0x0 1659 #define XPB_CLG_EXTRA_RD__CMP0_LOW__SHIFT 0x6 1660 #define XPB_CLG_EXTRA_RD__VLD0__SHIFT 0xb 1661 #define XPB_CLG_EXTRA_RD__CLG0_NUM__SHIFT 0xc 1662 #define XPB_CLG_EXTRA_RD__CMP1_HIGH__SHIFT 0xf 1663 #define XPB_CLG_EXTRA_RD__CMP1_LOW__SHIFT 0x15 1664 #define XPB_CLG_EXTRA_RD__VLD1__SHIFT 0x1a 1665 #define XPB_CLG_EXTRA_RD__CLG1_NUM__SHIFT 0x1b 1666 #define XPB_CLG_EXTRA_RD__CMP0_HIGH_MASK 0x0000003FL 1667 #define XPB_CLG_EXTRA_RD__CMP0_LOW_MASK 0x000007C0L 1668 #define XPB_CLG_EXTRA_RD__VLD0_MASK 0x00000800L 1669 #define XPB_CLG_EXTRA_RD__CLG0_NUM_MASK 0x00007000L 1670 #define XPB_CLG_EXTRA_RD__CMP1_HIGH_MASK 0x001F8000L 1671 #define XPB_CLG_EXTRA_RD__CMP1_LOW_MASK 0x03E00000L 1672 #define XPB_CLG_EXTRA_RD__VLD1_MASK 0x04000000L 1673 #define XPB_CLG_EXTRA_RD__CLG1_NUM_MASK 0x38000000L 1674 //XPB_CLG_EXTRA_MSK_RD 1675 #define XPB_CLG_EXTRA_MSK_RD__MSK0_HIGH__SHIFT 0x0 1676 #define XPB_CLG_EXTRA_MSK_RD__MSK0_LOW__SHIFT 0x6 1677 #define XPB_CLG_EXTRA_MSK_RD__MSK1_HIGH__SHIFT 0xb 1678 #define XPB_CLG_EXTRA_MSK_RD__MSK1_LOW__SHIFT 0x11 1679 #define XPB_CLG_EXTRA_MSK_RD__MSK0_HIGH_MASK 0x0000003FL 1680 #define XPB_CLG_EXTRA_MSK_RD__MSK0_LOW_MASK 0x000007C0L 1681 #define XPB_CLG_EXTRA_MSK_RD__MSK1_HIGH_MASK 0x0001F800L 1682 #define XPB_CLG_EXTRA_MSK_RD__MSK1_LOW_MASK 0x003E0000L 1683 //XPB_CLG_GFX_MATCH 1684 #define XPB_CLG_GFX_MATCH__FARBIRC0_ID__SHIFT 0x0 1685 #define XPB_CLG_GFX_MATCH__FARBIRC1_ID__SHIFT 0x6 1686 #define XPB_CLG_GFX_MATCH__FARBIRC2_ID__SHIFT 0xc 1687 #define XPB_CLG_GFX_MATCH__FARBIRC3_ID__SHIFT 0x12 1688 #define XPB_CLG_GFX_MATCH__FARBIRC0_VLD__SHIFT 0x18 1689 #define XPB_CLG_GFX_MATCH__FARBIRC1_VLD__SHIFT 0x19 1690 #define XPB_CLG_GFX_MATCH__FARBIRC2_VLD__SHIFT 0x1a 1691 #define XPB_CLG_GFX_MATCH__FARBIRC3_VLD__SHIFT 0x1b 1692 #define XPB_CLG_GFX_MATCH__FARBIRC0_ID_MASK 0x0000003FL 1693 #define XPB_CLG_GFX_MATCH__FARBIRC1_ID_MASK 0x00000FC0L 1694 #define XPB_CLG_GFX_MATCH__FARBIRC2_ID_MASK 0x0003F000L 1695 #define XPB_CLG_GFX_MATCH__FARBIRC3_ID_MASK 0x00FC0000L 1696 #define XPB_CLG_GFX_MATCH__FARBIRC0_VLD_MASK 0x01000000L 1697 #define XPB_CLG_GFX_MATCH__FARBIRC1_VLD_MASK 0x02000000L 1698 #define XPB_CLG_GFX_MATCH__FARBIRC2_VLD_MASK 0x04000000L 1699 #define XPB_CLG_GFX_MATCH__FARBIRC3_VLD_MASK 0x08000000L 1700 //XPB_CLG_GFX_MATCH_MSK 1701 #define XPB_CLG_GFX_MATCH_MSK__FARBIRC0_ID_MSK__SHIFT 0x0 1702 #define XPB_CLG_GFX_MATCH_MSK__FARBIRC1_ID_MSK__SHIFT 0x6 1703 #define XPB_CLG_GFX_MATCH_MSK__FARBIRC2_ID_MSK__SHIFT 0xc 1704 #define XPB_CLG_GFX_MATCH_MSK__FARBIRC3_ID_MSK__SHIFT 0x12 1705 #define XPB_CLG_GFX_MATCH_MSK__FARBIRC0_ID_MSK_MASK 0x0000003FL 1706 #define XPB_CLG_GFX_MATCH_MSK__FARBIRC1_ID_MSK_MASK 0x00000FC0L 1707 #define XPB_CLG_GFX_MATCH_MSK__FARBIRC2_ID_MSK_MASK 0x0003F000L 1708 #define XPB_CLG_GFX_MATCH_MSK__FARBIRC3_ID_MSK_MASK 0x00FC0000L 1709 //XPB_CLG_MM_MATCH 1710 #define XPB_CLG_MM_MATCH__FARBIRC0_ID__SHIFT 0x0 1711 #define XPB_CLG_MM_MATCH__FARBIRC1_ID__SHIFT 0x6 1712 #define XPB_CLG_MM_MATCH__FARBIRC0_VLD__SHIFT 0xc 1713 #define XPB_CLG_MM_MATCH__FARBIRC1_VLD__SHIFT 0xd 1714 #define XPB_CLG_MM_MATCH__FARBIRC0_ID_MASK 0x0000003FL 1715 #define XPB_CLG_MM_MATCH__FARBIRC1_ID_MASK 0x00000FC0L 1716 #define XPB_CLG_MM_MATCH__FARBIRC0_VLD_MASK 0x00001000L 1717 #define XPB_CLG_MM_MATCH__FARBIRC1_VLD_MASK 0x00002000L 1718 //XPB_CLG_MM_MATCH_MSK 1719 #define XPB_CLG_MM_MATCH_MSK__FARBIRC0_ID_MSK__SHIFT 0x0 1720 #define XPB_CLG_MM_MATCH_MSK__FARBIRC1_ID_MSK__SHIFT 0x6 1721 #define XPB_CLG_MM_MATCH_MSK__FARBIRC0_ID_MSK_MASK 0x0000003FL 1722 #define XPB_CLG_MM_MATCH_MSK__FARBIRC1_ID_MSK_MASK 0x00000FC0L 1723 //XPB_CLG_GUS_MATCH 1724 #define XPB_CLG_GUS_MATCH__FARBIRC0_ID__SHIFT 0x0 1725 #define XPB_CLG_GUS_MATCH__FARBIRC0_VLD__SHIFT 0x6 1726 #define XPB_CLG_GUS_MATCH__FARBIRC0_ID_MASK 0x0000003FL 1727 #define XPB_CLG_GUS_MATCH__FARBIRC0_VLD_MASK 0x00000040L 1728 //XPB_CLG_GUS_MATCH_MSK 1729 #define XPB_CLG_GUS_MATCH_MSK__FARBIRC0_ID_MSK__SHIFT 0x0 1730 #define XPB_CLG_GUS_MATCH_MSK__FARBIRC0_ID_MSK_MASK 0x0000003FL 1731 //XPB_CLG_GFX_UNITID_MAPPING0 1732 #define XPB_CLG_GFX_UNITID_MAPPING0__UNITID_LOW__SHIFT 0x0 1733 #define XPB_CLG_GFX_UNITID_MAPPING0__UNITID_VLD__SHIFT 0x5 1734 #define XPB_CLG_GFX_UNITID_MAPPING0__DEST_CLG_NUM__SHIFT 0x6 1735 #define XPB_CLG_GFX_UNITID_MAPPING0__UNITID_LOW_MASK 0x0000001FL 1736 #define XPB_CLG_GFX_UNITID_MAPPING0__UNITID_VLD_MASK 0x00000020L 1737 #define XPB_CLG_GFX_UNITID_MAPPING0__DEST_CLG_NUM_MASK 0x000001C0L 1738 //XPB_CLG_GFX_UNITID_MAPPING1 1739 #define XPB_CLG_GFX_UNITID_MAPPING1__UNITID_LOW__SHIFT 0x0 1740 #define XPB_CLG_GFX_UNITID_MAPPING1__UNITID_VLD__SHIFT 0x5 1741 #define XPB_CLG_GFX_UNITID_MAPPING1__DEST_CLG_NUM__SHIFT 0x6 1742 #define XPB_CLG_GFX_UNITID_MAPPING1__UNITID_LOW_MASK 0x0000001FL 1743 #define XPB_CLG_GFX_UNITID_MAPPING1__UNITID_VLD_MASK 0x00000020L 1744 #define XPB_CLG_GFX_UNITID_MAPPING1__DEST_CLG_NUM_MASK 0x000001C0L 1745 //XPB_CLG_GFX_UNITID_MAPPING2 1746 #define XPB_CLG_GFX_UNITID_MAPPING2__UNITID_LOW__SHIFT 0x0 1747 #define XPB_CLG_GFX_UNITID_MAPPING2__UNITID_VLD__SHIFT 0x5 1748 #define XPB_CLG_GFX_UNITID_MAPPING2__DEST_CLG_NUM__SHIFT 0x6 1749 #define XPB_CLG_GFX_UNITID_MAPPING2__UNITID_LOW_MASK 0x0000001FL 1750 #define XPB_CLG_GFX_UNITID_MAPPING2__UNITID_VLD_MASK 0x00000020L 1751 #define XPB_CLG_GFX_UNITID_MAPPING2__DEST_CLG_NUM_MASK 0x000001C0L 1752 //XPB_CLG_GFX_UNITID_MAPPING3 1753 #define XPB_CLG_GFX_UNITID_MAPPING3__UNITID_LOW__SHIFT 0x0 1754 #define XPB_CLG_GFX_UNITID_MAPPING3__UNITID_VLD__SHIFT 0x5 1755 #define XPB_CLG_GFX_UNITID_MAPPING3__DEST_CLG_NUM__SHIFT 0x6 1756 #define XPB_CLG_GFX_UNITID_MAPPING3__UNITID_LOW_MASK 0x0000001FL 1757 #define XPB_CLG_GFX_UNITID_MAPPING3__UNITID_VLD_MASK 0x00000020L 1758 #define XPB_CLG_GFX_UNITID_MAPPING3__DEST_CLG_NUM_MASK 0x000001C0L 1759 //XPB_CLG_GFX_UNITID_MAPPING4 1760 #define XPB_CLG_GFX_UNITID_MAPPING4__UNITID_LOW__SHIFT 0x0 1761 #define XPB_CLG_GFX_UNITID_MAPPING4__UNITID_VLD__SHIFT 0x5 1762 #define XPB_CLG_GFX_UNITID_MAPPING4__DEST_CLG_NUM__SHIFT 0x6 1763 #define XPB_CLG_GFX_UNITID_MAPPING4__UNITID_LOW_MASK 0x0000001FL 1764 #define XPB_CLG_GFX_UNITID_MAPPING4__UNITID_VLD_MASK 0x00000020L 1765 #define XPB_CLG_GFX_UNITID_MAPPING4__DEST_CLG_NUM_MASK 0x000001C0L 1766 //XPB_CLG_GFX_UNITID_MAPPING5 1767 #define XPB_CLG_GFX_UNITID_MAPPING5__UNITID_LOW__SHIFT 0x0 1768 #define XPB_CLG_GFX_UNITID_MAPPING5__UNITID_VLD__SHIFT 0x5 1769 #define XPB_CLG_GFX_UNITID_MAPPING5__DEST_CLG_NUM__SHIFT 0x6 1770 #define XPB_CLG_GFX_UNITID_MAPPING5__UNITID_LOW_MASK 0x0000001FL 1771 #define XPB_CLG_GFX_UNITID_MAPPING5__UNITID_VLD_MASK 0x00000020L 1772 #define XPB_CLG_GFX_UNITID_MAPPING5__DEST_CLG_NUM_MASK 0x000001C0L 1773 //XPB_CLG_GFX_UNITID_MAPPING6 1774 #define XPB_CLG_GFX_UNITID_MAPPING6__UNITID_LOW__SHIFT 0x0 1775 #define XPB_CLG_GFX_UNITID_MAPPING6__UNITID_VLD__SHIFT 0x5 1776 #define XPB_CLG_GFX_UNITID_MAPPING6__DEST_CLG_NUM__SHIFT 0x6 1777 #define XPB_CLG_GFX_UNITID_MAPPING6__UNITID_LOW_MASK 0x0000001FL 1778 #define XPB_CLG_GFX_UNITID_MAPPING6__UNITID_VLD_MASK 0x00000020L 1779 #define XPB_CLG_GFX_UNITID_MAPPING6__DEST_CLG_NUM_MASK 0x000001C0L 1780 //XPB_CLG_GFX_UNITID_MAPPING7 1781 #define XPB_CLG_GFX_UNITID_MAPPING7__UNITID_LOW__SHIFT 0x0 1782 #define XPB_CLG_GFX_UNITID_MAPPING7__UNITID_VLD__SHIFT 0x5 1783 #define XPB_CLG_GFX_UNITID_MAPPING7__DEST_CLG_NUM__SHIFT 0x6 1784 #define XPB_CLG_GFX_UNITID_MAPPING7__UNITID_LOW_MASK 0x0000001FL 1785 #define XPB_CLG_GFX_UNITID_MAPPING7__UNITID_VLD_MASK 0x00000020L 1786 #define XPB_CLG_GFX_UNITID_MAPPING7__DEST_CLG_NUM_MASK 0x000001C0L 1787 //XPB_CLG_MM_UNITID_MAPPING0 1788 #define XPB_CLG_MM_UNITID_MAPPING0__UNITID_LOW__SHIFT 0x0 1789 #define XPB_CLG_MM_UNITID_MAPPING0__UNITID_VLD__SHIFT 0x5 1790 #define XPB_CLG_MM_UNITID_MAPPING0__DEST_CLG_NUM__SHIFT 0x6 1791 #define XPB_CLG_MM_UNITID_MAPPING0__UNITID_LOW_MASK 0x0000001FL 1792 #define XPB_CLG_MM_UNITID_MAPPING0__UNITID_VLD_MASK 0x00000020L 1793 #define XPB_CLG_MM_UNITID_MAPPING0__DEST_CLG_NUM_MASK 0x000001C0L 1794 //XPB_CLG_MM_UNITID_MAPPING1 1795 #define XPB_CLG_MM_UNITID_MAPPING1__UNITID_LOW__SHIFT 0x0 1796 #define XPB_CLG_MM_UNITID_MAPPING1__UNITID_VLD__SHIFT 0x5 1797 #define XPB_CLG_MM_UNITID_MAPPING1__DEST_CLG_NUM__SHIFT 0x6 1798 #define XPB_CLG_MM_UNITID_MAPPING1__UNITID_LOW_MASK 0x0000001FL 1799 #define XPB_CLG_MM_UNITID_MAPPING1__UNITID_VLD_MASK 0x00000020L 1800 #define XPB_CLG_MM_UNITID_MAPPING1__DEST_CLG_NUM_MASK 0x000001C0L 1801 //XPB_CLG_MM_UNITID_MAPPING2 1802 #define XPB_CLG_MM_UNITID_MAPPING2__UNITID_LOW__SHIFT 0x0 1803 #define XPB_CLG_MM_UNITID_MAPPING2__UNITID_VLD__SHIFT 0x5 1804 #define XPB_CLG_MM_UNITID_MAPPING2__DEST_CLG_NUM__SHIFT 0x6 1805 #define XPB_CLG_MM_UNITID_MAPPING2__UNITID_LOW_MASK 0x0000001FL 1806 #define XPB_CLG_MM_UNITID_MAPPING2__UNITID_VLD_MASK 0x00000020L 1807 #define XPB_CLG_MM_UNITID_MAPPING2__DEST_CLG_NUM_MASK 0x000001C0L 1808 //XPB_CLG_MM_UNITID_MAPPING3 1809 #define XPB_CLG_MM_UNITID_MAPPING3__UNITID_LOW__SHIFT 0x0 1810 #define XPB_CLG_MM_UNITID_MAPPING3__UNITID_VLD__SHIFT 0x5 1811 #define XPB_CLG_MM_UNITID_MAPPING3__DEST_CLG_NUM__SHIFT 0x6 1812 #define XPB_CLG_MM_UNITID_MAPPING3__UNITID_LOW_MASK 0x0000001FL 1813 #define XPB_CLG_MM_UNITID_MAPPING3__UNITID_VLD_MASK 0x00000020L 1814 #define XPB_CLG_MM_UNITID_MAPPING3__DEST_CLG_NUM_MASK 0x000001C0L 1815 //XPB_CLG_GUS_UNITID_MAPPING0 1816 #define XPB_CLG_GUS_UNITID_MAPPING0__UNITID_LOW__SHIFT 0x0 1817 #define XPB_CLG_GUS_UNITID_MAPPING0__UNITID_VLD__SHIFT 0x5 1818 #define XPB_CLG_GUS_UNITID_MAPPING0__DEST_CLG_NUM__SHIFT 0x6 1819 #define XPB_CLG_GUS_UNITID_MAPPING0__UNITID_LOW_MASK 0x0000001FL 1820 #define XPB_CLG_GUS_UNITID_MAPPING0__UNITID_VLD_MASK 0x00000020L 1821 #define XPB_CLG_GUS_UNITID_MAPPING0__DEST_CLG_NUM_MASK 0x000001C0L 1822 //XPB_CLG_GUS_UNITID_MAPPING1 1823 #define XPB_CLG_GUS_UNITID_MAPPING1__UNITID_LOW__SHIFT 0x0 1824 #define XPB_CLG_GUS_UNITID_MAPPING1__UNITID_VLD__SHIFT 0x5 1825 #define XPB_CLG_GUS_UNITID_MAPPING1__DEST_CLG_NUM__SHIFT 0x6 1826 #define XPB_CLG_GUS_UNITID_MAPPING1__UNITID_LOW_MASK 0x0000001FL 1827 #define XPB_CLG_GUS_UNITID_MAPPING1__UNITID_VLD_MASK 0x00000020L 1828 #define XPB_CLG_GUS_UNITID_MAPPING1__DEST_CLG_NUM_MASK 0x000001C0L 1829 //XPB_CLG_GUS_UNITID_MAPPING2 1830 #define XPB_CLG_GUS_UNITID_MAPPING2__UNITID_LOW__SHIFT 0x0 1831 #define XPB_CLG_GUS_UNITID_MAPPING2__UNITID_VLD__SHIFT 0x5 1832 #define XPB_CLG_GUS_UNITID_MAPPING2__DEST_CLG_NUM__SHIFT 0x6 1833 #define XPB_CLG_GUS_UNITID_MAPPING2__UNITID_LOW_MASK 0x0000001FL 1834 #define XPB_CLG_GUS_UNITID_MAPPING2__UNITID_VLD_MASK 0x00000020L 1835 #define XPB_CLG_GUS_UNITID_MAPPING2__DEST_CLG_NUM_MASK 0x000001C0L 1836 //XPB_CLG_GUS_UNITID_MAPPING3 1837 #define XPB_CLG_GUS_UNITID_MAPPING3__UNITID_LOW__SHIFT 0x0 1838 #define XPB_CLG_GUS_UNITID_MAPPING3__UNITID_VLD__SHIFT 0x5 1839 #define XPB_CLG_GUS_UNITID_MAPPING3__DEST_CLG_NUM__SHIFT 0x6 1840 #define XPB_CLG_GUS_UNITID_MAPPING3__UNITID_LOW_MASK 0x0000001FL 1841 #define XPB_CLG_GUS_UNITID_MAPPING3__UNITID_VLD_MASK 0x00000020L 1842 #define XPB_CLG_GUS_UNITID_MAPPING3__DEST_CLG_NUM_MASK 0x000001C0L 1843 //XPB_CLG_GUS_UNITID_MAPPING4 1844 #define XPB_CLG_GUS_UNITID_MAPPING4__UNITID_LOW__SHIFT 0x0 1845 #define XPB_CLG_GUS_UNITID_MAPPING4__UNITID_VLD__SHIFT 0x5 1846 #define XPB_CLG_GUS_UNITID_MAPPING4__DEST_CLG_NUM__SHIFT 0x6 1847 #define XPB_CLG_GUS_UNITID_MAPPING4__UNITID_LOW_MASK 0x0000001FL 1848 #define XPB_CLG_GUS_UNITID_MAPPING4__UNITID_VLD_MASK 0x00000020L 1849 #define XPB_CLG_GUS_UNITID_MAPPING4__DEST_CLG_NUM_MASK 0x000001C0L 1850 //XPB_CLG_GUS_UNITID_MAPPING5 1851 #define XPB_CLG_GUS_UNITID_MAPPING5__UNITID_LOW__SHIFT 0x0 1852 #define XPB_CLG_GUS_UNITID_MAPPING5__UNITID_VLD__SHIFT 0x5 1853 #define XPB_CLG_GUS_UNITID_MAPPING5__DEST_CLG_NUM__SHIFT 0x6 1854 #define XPB_CLG_GUS_UNITID_MAPPING5__UNITID_LOW_MASK 0x0000001FL 1855 #define XPB_CLG_GUS_UNITID_MAPPING5__UNITID_VLD_MASK 0x00000020L 1856 #define XPB_CLG_GUS_UNITID_MAPPING5__DEST_CLG_NUM_MASK 0x000001C0L 1857 //XPB_CLG_GUS_UNITID_MAPPING6 1858 #define XPB_CLG_GUS_UNITID_MAPPING6__UNITID_LOW__SHIFT 0x0 1859 #define XPB_CLG_GUS_UNITID_MAPPING6__UNITID_VLD__SHIFT 0x5 1860 #define XPB_CLG_GUS_UNITID_MAPPING6__DEST_CLG_NUM__SHIFT 0x6 1861 #define XPB_CLG_GUS_UNITID_MAPPING6__UNITID_LOW_MASK 0x0000001FL 1862 #define XPB_CLG_GUS_UNITID_MAPPING6__UNITID_VLD_MASK 0x00000020L 1863 #define XPB_CLG_GUS_UNITID_MAPPING6__DEST_CLG_NUM_MASK 0x000001C0L 1864 //XPB_CLG_GUS_UNITID_MAPPING7 1865 #define XPB_CLG_GUS_UNITID_MAPPING7__UNITID_LOW__SHIFT 0x0 1866 #define XPB_CLG_GUS_UNITID_MAPPING7__UNITID_VLD__SHIFT 0x5 1867 #define XPB_CLG_GUS_UNITID_MAPPING7__DEST_CLG_NUM__SHIFT 0x6 1868 #define XPB_CLG_GUS_UNITID_MAPPING7__UNITID_LOW_MASK 0x0000001FL 1869 #define XPB_CLG_GUS_UNITID_MAPPING7__UNITID_VLD_MASK 0x00000020L 1870 #define XPB_CLG_GUS_UNITID_MAPPING7__DEST_CLG_NUM_MASK 0x000001C0L 1871 1872 1873 // addressBlock: athub_rpbdec 1874 //RPB_PASSPW_CONF 1875 #define RPB_PASSPW_CONF__XPB_PASSPW_OVERRIDE__SHIFT 0x0 1876 #define RPB_PASSPW_CONF__XPB_RSPPASSPW_OVERRIDE__SHIFT 0x1 1877 #define RPB_PASSPW_CONF__ATC_MM_TR_PASSPW_OVERRIDE__SHIFT 0x2 1878 #define RPB_PASSPW_CONF__ATC_MM_TR_PASSPW_OVERRIDE_EN__SHIFT 0x3 1879 #define RPB_PASSPW_CONF__ATC_MM_RSPPASSPW_OVERRIDE__SHIFT 0x4 1880 #define RPB_PASSPW_CONF__ATC_MM_RSPPASSPW_OVERRIDE_EN__SHIFT 0x5 1881 #define RPB_PASSPW_CONF__ATC_GFX_TR_PASSPW_OVERRIDE__SHIFT 0x6 1882 #define RPB_PASSPW_CONF__ATC_GFX_TR_PASSPW_OVERRIDE_EN__SHIFT 0x7 1883 #define RPB_PASSPW_CONF__ATC_GFX_RSPPASSPW_OVERRIDE__SHIFT 0x8 1884 #define RPB_PASSPW_CONF__ATC_GFX_RSPPASSPW_OVERRIDE_EN__SHIFT 0x9 1885 #define RPB_PASSPW_CONF__ATC_PAGE_PASSPW_OVERRIDE__SHIFT 0xa 1886 #define RPB_PASSPW_CONF__ATC_PAGE_PASSPW_OVERRIDE_EN__SHIFT 0xb 1887 #define RPB_PASSPW_CONF__ATC_PAGE_RSPPASSPW_OVERRIDE__SHIFT 0xc 1888 #define RPB_PASSPW_CONF__ATC_PAGE_RSPPASSPW_OVERRIDE_EN__SHIFT 0xd 1889 #define RPB_PASSPW_CONF__WR_PASSPW_OVERRIDE__SHIFT 0xe 1890 #define RPB_PASSPW_CONF__WR_RSPPASSPW_OVERRIDE__SHIFT 0xf 1891 #define RPB_PASSPW_CONF__RD_PASSPW_OVERRIDE__SHIFT 0x10 1892 #define RPB_PASSPW_CONF__RD_RSPPASSPW_OVERRIDE__SHIFT 0x11 1893 #define RPB_PASSPW_CONF__ATOMIC_PASSPW_OVERRIDE__SHIFT 0x12 1894 #define RPB_PASSPW_CONF__ATOMIC_RSPPASSPW_OVERRIDE__SHIFT 0x13 1895 #define RPB_PASSPW_CONF__WRRSP_PASSPW_OVERRIDE__SHIFT 0x14 1896 #define RPB_PASSPW_CONF__WRRSP_PASSPW_OVERRIDE_EN__SHIFT 0x15 1897 #define RPB_PASSPW_CONF__RDRSP_PASSPW_OVERRIDE__SHIFT 0x16 1898 #define RPB_PASSPW_CONF__RDRSP_PASSPW_OVERRIDE_EN__SHIFT 0x17 1899 #define RPB_PASSPW_CONF__XPB_PASSPW_OVERRIDE_MASK 0x00000001L 1900 #define RPB_PASSPW_CONF__XPB_RSPPASSPW_OVERRIDE_MASK 0x00000002L 1901 #define RPB_PASSPW_CONF__ATC_MM_TR_PASSPW_OVERRIDE_MASK 0x00000004L 1902 #define RPB_PASSPW_CONF__ATC_MM_TR_PASSPW_OVERRIDE_EN_MASK 0x00000008L 1903 #define RPB_PASSPW_CONF__ATC_MM_RSPPASSPW_OVERRIDE_MASK 0x00000010L 1904 #define RPB_PASSPW_CONF__ATC_MM_RSPPASSPW_OVERRIDE_EN_MASK 0x00000020L 1905 #define RPB_PASSPW_CONF__ATC_GFX_TR_PASSPW_OVERRIDE_MASK 0x00000040L 1906 #define RPB_PASSPW_CONF__ATC_GFX_TR_PASSPW_OVERRIDE_EN_MASK 0x00000080L 1907 #define RPB_PASSPW_CONF__ATC_GFX_RSPPASSPW_OVERRIDE_MASK 0x00000100L 1908 #define RPB_PASSPW_CONF__ATC_GFX_RSPPASSPW_OVERRIDE_EN_MASK 0x00000200L 1909 #define RPB_PASSPW_CONF__ATC_PAGE_PASSPW_OVERRIDE_MASK 0x00000400L 1910 #define RPB_PASSPW_CONF__ATC_PAGE_PASSPW_OVERRIDE_EN_MASK 0x00000800L 1911 #define RPB_PASSPW_CONF__ATC_PAGE_RSPPASSPW_OVERRIDE_MASK 0x00001000L 1912 #define RPB_PASSPW_CONF__ATC_PAGE_RSPPASSPW_OVERRIDE_EN_MASK 0x00002000L 1913 #define RPB_PASSPW_CONF__WR_PASSPW_OVERRIDE_MASK 0x00004000L 1914 #define RPB_PASSPW_CONF__WR_RSPPASSPW_OVERRIDE_MASK 0x00008000L 1915 #define RPB_PASSPW_CONF__RD_PASSPW_OVERRIDE_MASK 0x00010000L 1916 #define RPB_PASSPW_CONF__RD_RSPPASSPW_OVERRIDE_MASK 0x00020000L 1917 #define RPB_PASSPW_CONF__ATOMIC_PASSPW_OVERRIDE_MASK 0x00040000L 1918 #define RPB_PASSPW_CONF__ATOMIC_RSPPASSPW_OVERRIDE_MASK 0x00080000L 1919 #define RPB_PASSPW_CONF__WRRSP_PASSPW_OVERRIDE_MASK 0x00100000L 1920 #define RPB_PASSPW_CONF__WRRSP_PASSPW_OVERRIDE_EN_MASK 0x00200000L 1921 #define RPB_PASSPW_CONF__RDRSP_PASSPW_OVERRIDE_MASK 0x00400000L 1922 #define RPB_PASSPW_CONF__RDRSP_PASSPW_OVERRIDE_EN_MASK 0x00800000L 1923 //RPB_BLOCKLEVEL_CONF 1924 #define RPB_BLOCKLEVEL_CONF__XPB_BLOCKLEVEL_OVERRIDE__SHIFT 0x0 1925 #define RPB_BLOCKLEVEL_CONF__XPB_BLOCKLEVEL_OVERRIDE_EN__SHIFT 0x2 1926 #define RPB_BLOCKLEVEL_CONF__ATC_MM_TR_BLOCKLEVEL__SHIFT 0x3 1927 #define RPB_BLOCKLEVEL_CONF__ATC_GFX_TR_BLOCKLEVEL__SHIFT 0x5 1928 #define RPB_BLOCKLEVEL_CONF__ATC_PAGE_BLOCKLEVEL__SHIFT 0x7 1929 #define RPB_BLOCKLEVEL_CONF__ATC_INV_BLOCKLEVEL__SHIFT 0x9 1930 #define RPB_BLOCKLEVEL_CONF__IO_WR_BLOCKLEVEL_OVERRIDE__SHIFT 0xb 1931 #define RPB_BLOCKLEVEL_CONF__IO_WR_BLOCKLEVEL_OVERRIDE_EN__SHIFT 0xd 1932 #define RPB_BLOCKLEVEL_CONF__IO_RD_BLOCKLEVEL_OVERRIDE__SHIFT 0xe 1933 #define RPB_BLOCKLEVEL_CONF__IO_RD_BLOCKLEVEL_OVERRIDE_EN__SHIFT 0x10 1934 #define RPB_BLOCKLEVEL_CONF__ATOMIC_BLOCKLEVEL_OVERRIDE__SHIFT 0x11 1935 #define RPB_BLOCKLEVEL_CONF__ATOMIC_BLOCKLEVEL_OVERRIDE_EN__SHIFT 0x13 1936 #define RPB_BLOCKLEVEL_CONF__XPB_BLOCKLEVEL_OVERRIDE_MASK 0x00000003L 1937 #define RPB_BLOCKLEVEL_CONF__XPB_BLOCKLEVEL_OVERRIDE_EN_MASK 0x00000004L 1938 #define RPB_BLOCKLEVEL_CONF__ATC_MM_TR_BLOCKLEVEL_MASK 0x00000018L 1939 #define RPB_BLOCKLEVEL_CONF__ATC_GFX_TR_BLOCKLEVEL_MASK 0x00000060L 1940 #define RPB_BLOCKLEVEL_CONF__ATC_PAGE_BLOCKLEVEL_MASK 0x00000180L 1941 #define RPB_BLOCKLEVEL_CONF__ATC_INV_BLOCKLEVEL_MASK 0x00000600L 1942 #define RPB_BLOCKLEVEL_CONF__IO_WR_BLOCKLEVEL_OVERRIDE_MASK 0x00001800L 1943 #define RPB_BLOCKLEVEL_CONF__IO_WR_BLOCKLEVEL_OVERRIDE_EN_MASK 0x00002000L 1944 #define RPB_BLOCKLEVEL_CONF__IO_RD_BLOCKLEVEL_OVERRIDE_MASK 0x0000C000L 1945 #define RPB_BLOCKLEVEL_CONF__IO_RD_BLOCKLEVEL_OVERRIDE_EN_MASK 0x00010000L 1946 #define RPB_BLOCKLEVEL_CONF__ATOMIC_BLOCKLEVEL_OVERRIDE_MASK 0x00060000L 1947 #define RPB_BLOCKLEVEL_CONF__ATOMIC_BLOCKLEVEL_OVERRIDE_EN_MASK 0x00080000L 1948 //RPB_TAG_CONF 1949 #define RPB_TAG_CONF__RPB_IO_RD__SHIFT 0x0 1950 #define RPB_TAG_CONF__RPB_IO_WR__SHIFT 0xa 1951 #define RPB_TAG_CONF__RPB_IO_RD_MASK 0x000003FFL 1952 #define RPB_TAG_CONF__RPB_IO_WR_MASK 0x000FFC00L 1953 //RPB_EFF_CNTL 1954 #define RPB_EFF_CNTL__WR_LAZY_TIMER__SHIFT 0x0 1955 #define RPB_EFF_CNTL__RD_LAZY_TIMER__SHIFT 0x8 1956 #define RPB_EFF_CNTL__WR_LAZY_TIMER_MASK 0x000000FFL 1957 #define RPB_EFF_CNTL__RD_LAZY_TIMER_MASK 0x0000FF00L 1958 //RPB_ARB_CNTL 1959 #define RPB_ARB_CNTL__RD_SWITCH_NUM__SHIFT 0x0 1960 #define RPB_ARB_CNTL__WR_SWITCH_NUM__SHIFT 0x8 1961 #define RPB_ARB_CNTL__ATC_TR_SWITCH_NUM__SHIFT 0x10 1962 #define RPB_ARB_CNTL__ARB_MODE__SHIFT 0x18 1963 #define RPB_ARB_CNTL__SWITCH_NUM_MODE__SHIFT 0x19 1964 #define RPB_ARB_CNTL__RPB_VC0_CRD__SHIFT 0x1a 1965 #define RPB_ARB_CNTL__DISABLE_FED__SHIFT 0x1f 1966 #define RPB_ARB_CNTL__RD_SWITCH_NUM_MASK 0x000000FFL 1967 #define RPB_ARB_CNTL__WR_SWITCH_NUM_MASK 0x0000FF00L 1968 #define RPB_ARB_CNTL__ATC_TR_SWITCH_NUM_MASK 0x00FF0000L 1969 #define RPB_ARB_CNTL__ARB_MODE_MASK 0x01000000L 1970 #define RPB_ARB_CNTL__SWITCH_NUM_MODE_MASK 0x02000000L 1971 #define RPB_ARB_CNTL__RPB_VC0_CRD_MASK 0x7C000000L 1972 #define RPB_ARB_CNTL__DISABLE_FED_MASK 0x80000000L 1973 //RPB_ARB_CNTL2 1974 #define RPB_ARB_CNTL2__P2P_SWITCH_NUM__SHIFT 0x0 1975 #define RPB_ARB_CNTL2__ATOMIC_SWITCH_NUM__SHIFT 0x8 1976 #define RPB_ARB_CNTL2__ATC_PAGE_SWITCH_NUM__SHIFT 0x10 1977 #define RPB_ARB_CNTL2__RPB_VC1_CRD__SHIFT 0x18 1978 #define RPB_ARB_CNTL2__P2P_SWITCH_NUM_MASK 0x000000FFL 1979 #define RPB_ARB_CNTL2__ATOMIC_SWITCH_NUM_MASK 0x0000FF00L 1980 #define RPB_ARB_CNTL2__ATC_PAGE_SWITCH_NUM_MASK 0x00FF0000L 1981 #define RPB_ARB_CNTL2__RPB_VC1_CRD_MASK 0x1F000000L 1982 //RPB_BIF_CNTL 1983 #define RPB_BIF_CNTL__VC0_SWITCH_NUM__SHIFT 0x0 1984 #define RPB_BIF_CNTL__VC1_SWITCH_NUM__SHIFT 0x8 1985 #define RPB_BIF_CNTL__VC2_SWITCH_NUM__SHIFT 0x10 1986 #define RPB_BIF_CNTL__NBIF_DMA_ORIGCLKCTL_EN__SHIFT 0x18 1987 #define RPB_BIF_CNTL__TR_QOS_VC__SHIFT 0x19 1988 #define RPB_BIF_CNTL__RESERVED__SHIFT 0x1c 1989 #define RPB_BIF_CNTL__VC0_SWITCH_NUM_MASK 0x000000FFL 1990 #define RPB_BIF_CNTL__VC1_SWITCH_NUM_MASK 0x0000FF00L 1991 #define RPB_BIF_CNTL__VC2_SWITCH_NUM_MASK 0x00FF0000L 1992 #define RPB_BIF_CNTL__NBIF_DMA_ORIGCLKCTL_EN_MASK 0x01000000L 1993 #define RPB_BIF_CNTL__TR_QOS_VC_MASK 0x0E000000L 1994 #define RPB_BIF_CNTL__RESERVED_MASK 0xF0000000L 1995 //RPB_BIF_CNTL2 1996 #define RPB_BIF_CNTL2__ARB_MODE__SHIFT 0x0 1997 #define RPB_BIF_CNTL2__DRAIN_VC_NUM__SHIFT 0x1 1998 #define RPB_BIF_CNTL2__SWITCH_ENABLE__SHIFT 0x3 1999 #define RPB_BIF_CNTL2__SWITCH_THRESHOLD__SHIFT 0x4 2000 #define RPB_BIF_CNTL2__PAGE_PRI_EN__SHIFT 0xc 2001 #define RPB_BIF_CNTL2__MM_TR_PRI_EN__SHIFT 0xd 2002 #define RPB_BIF_CNTL2__GFX_TR_PRI_EN__SHIFT 0xe 2003 #define RPB_BIF_CNTL2__VC0_CHAINED_OVERRIDE__SHIFT 0xf 2004 #define RPB_BIF_CNTL2__PARITY_CHECK_EN__SHIFT 0x10 2005 #define RPB_BIF_CNTL2__NBIF_HST_COMPCLKCTL_EN__SHIFT 0x11 2006 #define RPB_BIF_CNTL2__RESERVED__SHIFT 0x12 2007 #define RPB_BIF_CNTL2__ARB_MODE_MASK 0x00000001L 2008 #define RPB_BIF_CNTL2__DRAIN_VC_NUM_MASK 0x00000006L 2009 #define RPB_BIF_CNTL2__SWITCH_ENABLE_MASK 0x00000008L 2010 #define RPB_BIF_CNTL2__SWITCH_THRESHOLD_MASK 0x00000FF0L 2011 #define RPB_BIF_CNTL2__PAGE_PRI_EN_MASK 0x00001000L 2012 #define RPB_BIF_CNTL2__MM_TR_PRI_EN_MASK 0x00002000L 2013 #define RPB_BIF_CNTL2__GFX_TR_PRI_EN_MASK 0x00004000L 2014 #define RPB_BIF_CNTL2__VC0_CHAINED_OVERRIDE_MASK 0x00008000L 2015 #define RPB_BIF_CNTL2__PARITY_CHECK_EN_MASK 0x00010000L 2016 #define RPB_BIF_CNTL2__NBIF_HST_COMPCLKCTL_EN_MASK 0x00020000L 2017 #define RPB_BIF_CNTL2__RESERVED_MASK 0xFFFC0000L 2018 //RPB_WR_SWITCH_CNTL 2019 #define RPB_WR_SWITCH_CNTL__QUEUE0_SWITCH_NUM__SHIFT 0x0 2020 #define RPB_WR_SWITCH_CNTL__QUEUE1_SWITCH_NUM__SHIFT 0x7 2021 #define RPB_WR_SWITCH_CNTL__QUEUE2_SWITCH_NUM__SHIFT 0xe 2022 #define RPB_WR_SWITCH_CNTL__QUEUE3_SWITCH_NUM__SHIFT 0x15 2023 #define RPB_WR_SWITCH_CNTL__SWITCH_NUM_MODE__SHIFT 0x1c 2024 #define RPB_WR_SWITCH_CNTL__WORKLOAD_ADJUST_EN__SHIFT 0x1d 2025 #define RPB_WR_SWITCH_CNTL__WEIGHT_ADJUST_STEP__SHIFT 0x1e 2026 #define RPB_WR_SWITCH_CNTL__QUEUE0_SWITCH_NUM_MASK 0x0000007FL 2027 #define RPB_WR_SWITCH_CNTL__QUEUE1_SWITCH_NUM_MASK 0x00003F80L 2028 #define RPB_WR_SWITCH_CNTL__QUEUE2_SWITCH_NUM_MASK 0x001FC000L 2029 #define RPB_WR_SWITCH_CNTL__QUEUE3_SWITCH_NUM_MASK 0x0FE00000L 2030 #define RPB_WR_SWITCH_CNTL__SWITCH_NUM_MODE_MASK 0x10000000L 2031 #define RPB_WR_SWITCH_CNTL__WORKLOAD_ADJUST_EN_MASK 0x20000000L 2032 #define RPB_WR_SWITCH_CNTL__WEIGHT_ADJUST_STEP_MASK 0xC0000000L 2033 //RPB_RD_SWITCH_CNTL 2034 #define RPB_RD_SWITCH_CNTL__QUEUE0_SWITCH_NUM__SHIFT 0x0 2035 #define RPB_RD_SWITCH_CNTL__QUEUE1_SWITCH_NUM__SHIFT 0x7 2036 #define RPB_RD_SWITCH_CNTL__QUEUE2_SWITCH_NUM__SHIFT 0xe 2037 #define RPB_RD_SWITCH_CNTL__QUEUE3_SWITCH_NUM__SHIFT 0x15 2038 #define RPB_RD_SWITCH_CNTL__SWITCH_NUM_MODE__SHIFT 0x1c 2039 #define RPB_RD_SWITCH_CNTL__WORKLOAD_ADJUST_EN__SHIFT 0x1d 2040 #define RPB_RD_SWITCH_CNTL__WEIGHT_ADJUST_STEP__SHIFT 0x1e 2041 #define RPB_RD_SWITCH_CNTL__QUEUE0_SWITCH_NUM_MASK 0x0000007FL 2042 #define RPB_RD_SWITCH_CNTL__QUEUE1_SWITCH_NUM_MASK 0x00003F80L 2043 #define RPB_RD_SWITCH_CNTL__QUEUE2_SWITCH_NUM_MASK 0x001FC000L 2044 #define RPB_RD_SWITCH_CNTL__QUEUE3_SWITCH_NUM_MASK 0x0FE00000L 2045 #define RPB_RD_SWITCH_CNTL__SWITCH_NUM_MODE_MASK 0x10000000L 2046 #define RPB_RD_SWITCH_CNTL__WORKLOAD_ADJUST_EN_MASK 0x20000000L 2047 #define RPB_RD_SWITCH_CNTL__WEIGHT_ADJUST_STEP_MASK 0xC0000000L 2048 //RPB_SWITCH_CNTL2 2049 #define RPB_SWITCH_CNTL2__RD_QUEUE4_SWITCH_NUM__SHIFT 0x0 2050 #define RPB_SWITCH_CNTL2__RD_QUEUE5_SWITCH_NUM__SHIFT 0x7 2051 #define RPB_SWITCH_CNTL2__WR_QUEUE4_SWITCH_NUM__SHIFT 0xe 2052 #define RPB_SWITCH_CNTL2__WR_QUEUE5_SWITCH_NUM__SHIFT 0x15 2053 #define RPB_SWITCH_CNTL2__RD_QUEUE4_SWITCH_NUM_MASK 0x0000007FL 2054 #define RPB_SWITCH_CNTL2__RD_QUEUE5_SWITCH_NUM_MASK 0x00003F80L 2055 #define RPB_SWITCH_CNTL2__WR_QUEUE4_SWITCH_NUM_MASK 0x001FC000L 2056 #define RPB_SWITCH_CNTL2__WR_QUEUE5_SWITCH_NUM_MASK 0x0FE00000L 2057 //RPB_CID_QUEUE_WR 2058 #define RPB_CID_QUEUE_WR__CLIENT_ID_LOW__SHIFT 0x0 2059 #define RPB_CID_QUEUE_WR__CLIENT_ID_HIGH__SHIFT 0x5 2060 #define RPB_CID_QUEUE_WR__UPDATE_MODE__SHIFT 0xb 2061 #define RPB_CID_QUEUE_WR__WRITE_QUEUE__SHIFT 0xc 2062 #define RPB_CID_QUEUE_WR__READ_QUEUE__SHIFT 0xf 2063 #define RPB_CID_QUEUE_WR__UPDATE__SHIFT 0x12 2064 #define RPB_CID_QUEUE_WR__CLIENT_ID_LOW_MASK 0x0000001FL 2065 #define RPB_CID_QUEUE_WR__CLIENT_ID_HIGH_MASK 0x000007E0L 2066 #define RPB_CID_QUEUE_WR__UPDATE_MODE_MASK 0x00000800L 2067 #define RPB_CID_QUEUE_WR__WRITE_QUEUE_MASK 0x00007000L 2068 #define RPB_CID_QUEUE_WR__READ_QUEUE_MASK 0x00038000L 2069 #define RPB_CID_QUEUE_WR__UPDATE_MASK 0x00040000L 2070 //RPB_EA_QUEUE_WR 2071 #define RPB_EA_QUEUE_WR__EA_NUMBER__SHIFT 0x0 2072 #define RPB_EA_QUEUE_WR__WRITE_QUEUE__SHIFT 0x5 2073 #define RPB_EA_QUEUE_WR__READ_QUEUE__SHIFT 0x8 2074 #define RPB_EA_QUEUE_WR__UPDATE__SHIFT 0xb 2075 #define RPB_EA_QUEUE_WR__EA_NUMBER_MASK 0x0000001FL 2076 #define RPB_EA_QUEUE_WR__WRITE_QUEUE_MASK 0x000000E0L 2077 #define RPB_EA_QUEUE_WR__READ_QUEUE_MASK 0x00000700L 2078 #define RPB_EA_QUEUE_WR__UPDATE_MASK 0x00000800L 2079 //RPB_CID_QUEUE_RD 2080 #define RPB_CID_QUEUE_RD__CLIENT_ID_LOW__SHIFT 0x0 2081 #define RPB_CID_QUEUE_RD__CLIENT_ID_HIGH__SHIFT 0x5 2082 #define RPB_CID_QUEUE_RD__WRITE_QUEUE__SHIFT 0xb 2083 #define RPB_CID_QUEUE_RD__READ_QUEUE__SHIFT 0xe 2084 #define RPB_CID_QUEUE_RD__CLIENT_ID_LOW_MASK 0x0000001FL 2085 #define RPB_CID_QUEUE_RD__CLIENT_ID_HIGH_MASK 0x000007E0L 2086 #define RPB_CID_QUEUE_RD__WRITE_QUEUE_MASK 0x00003800L 2087 #define RPB_CID_QUEUE_RD__READ_QUEUE_MASK 0x0001C000L 2088 //RPB_CID_QUEUE_EX 2089 #define RPB_CID_QUEUE_EX__START__SHIFT 0x0 2090 #define RPB_CID_QUEUE_EX__OFFSET__SHIFT 0x1 2091 #define RPB_CID_QUEUE_EX__START_MASK 0x00000001L 2092 #define RPB_CID_QUEUE_EX__OFFSET_MASK 0x000001FEL 2093 //RPB_CID_QUEUE_EX_DATA 2094 #define RPB_CID_QUEUE_EX_DATA__WRITE_ENTRIES__SHIFT 0x0 2095 #define RPB_CID_QUEUE_EX_DATA__READ_ENTRIES__SHIFT 0x10 2096 #define RPB_CID_QUEUE_EX_DATA__WRITE_ENTRIES_MASK 0x0000FFFFL 2097 #define RPB_CID_QUEUE_EX_DATA__READ_ENTRIES_MASK 0xFFFF0000L 2098 //RPB_DEINTRLV_COMBINE_CNTL 2099 #define RPB_DEINTRLV_COMBINE_CNTL__WC_CHAINED_FLUSH_TIMER__SHIFT 0x0 2100 #define RPB_DEINTRLV_COMBINE_CNTL__WC_CHAINED_BREAK_EN__SHIFT 0x4 2101 #define RPB_DEINTRLV_COMBINE_CNTL__WC_HANDLE_CHECK_DISABLE__SHIFT 0x5 2102 #define RPB_DEINTRLV_COMBINE_CNTL__XPB_WRREQ_CRD__SHIFT 0x6 2103 #define RPB_DEINTRLV_COMBINE_CNTL__RESERVED__SHIFT 0xe 2104 #define RPB_DEINTRLV_COMBINE_CNTL__WC_CHAINED_FLUSH_TIMER_MASK 0x0000000FL 2105 #define RPB_DEINTRLV_COMBINE_CNTL__WC_CHAINED_BREAK_EN_MASK 0x00000010L 2106 #define RPB_DEINTRLV_COMBINE_CNTL__WC_HANDLE_CHECK_DISABLE_MASK 0x00000020L 2107 #define RPB_DEINTRLV_COMBINE_CNTL__XPB_WRREQ_CRD_MASK 0x00003FC0L 2108 #define RPB_DEINTRLV_COMBINE_CNTL__RESERVED_MASK 0xFFFFC000L 2109 //RPB_VC_SWITCH_RDWR 2110 #define RPB_VC_SWITCH_RDWR__MODE__SHIFT 0x0 2111 #define RPB_VC_SWITCH_RDWR__NUM_RD__SHIFT 0x2 2112 #define RPB_VC_SWITCH_RDWR__NUM_WR__SHIFT 0xa 2113 #define RPB_VC_SWITCH_RDWR__XPB_RDREQ_CRD__SHIFT 0x12 2114 #define RPB_VC_SWITCH_RDWR__RESERVED__SHIFT 0x1a 2115 #define RPB_VC_SWITCH_RDWR__MODE_MASK 0x00000003L 2116 #define RPB_VC_SWITCH_RDWR__NUM_RD_MASK 0x000003FCL 2117 #define RPB_VC_SWITCH_RDWR__NUM_WR_MASK 0x0003FC00L 2118 #define RPB_VC_SWITCH_RDWR__XPB_RDREQ_CRD_MASK 0x03FC0000L 2119 #define RPB_VC_SWITCH_RDWR__RESERVED_MASK 0xFC000000L 2120 //RPB_PERF_COUNTER_CNTL 2121 #define RPB_PERF_COUNTER_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 2122 #define RPB_PERF_COUNTER_CNTL__CLEAR_SELECTED_PERF_COUNTER__SHIFT 0x2 2123 #define RPB_PERF_COUNTER_CNTL__CLEAR_ALL_PERF_COUNTERS__SHIFT 0x3 2124 #define RPB_PERF_COUNTER_CNTL__STOP_ON_COUNTER_SATURATION__SHIFT 0x4 2125 #define RPB_PERF_COUNTER_CNTL__ENABLE_PERF_COUNTERS__SHIFT 0x5 2126 #define RPB_PERF_COUNTER_CNTL__PERF_COUNTER_ASSIGN_0__SHIFT 0x9 2127 #define RPB_PERF_COUNTER_CNTL__PERF_COUNTER_ASSIGN_1__SHIFT 0xe 2128 #define RPB_PERF_COUNTER_CNTL__PERF_COUNTER_ASSIGN_2__SHIFT 0x13 2129 #define RPB_PERF_COUNTER_CNTL__PERF_COUNTER_ASSIGN_3__SHIFT 0x18 2130 #define RPB_PERF_COUNTER_CNTL__PERF_COUNTER_SELECT_MASK 0x00000003L 2131 #define RPB_PERF_COUNTER_CNTL__CLEAR_SELECTED_PERF_COUNTER_MASK 0x00000004L 2132 #define RPB_PERF_COUNTER_CNTL__CLEAR_ALL_PERF_COUNTERS_MASK 0x00000008L 2133 #define RPB_PERF_COUNTER_CNTL__STOP_ON_COUNTER_SATURATION_MASK 0x00000010L 2134 #define RPB_PERF_COUNTER_CNTL__ENABLE_PERF_COUNTERS_MASK 0x000001E0L 2135 #define RPB_PERF_COUNTER_CNTL__PERF_COUNTER_ASSIGN_0_MASK 0x00003E00L 2136 #define RPB_PERF_COUNTER_CNTL__PERF_COUNTER_ASSIGN_1_MASK 0x0007C000L 2137 #define RPB_PERF_COUNTER_CNTL__PERF_COUNTER_ASSIGN_2_MASK 0x00F80000L 2138 #define RPB_PERF_COUNTER_CNTL__PERF_COUNTER_ASSIGN_3_MASK 0x1F000000L 2139 //RPB_PERF_COUNTER_STATUS 2140 #define RPB_PERF_COUNTER_STATUS__PERFORMANCE_COUNTER_VALUE__SHIFT 0x0 2141 #define RPB_PERF_COUNTER_STATUS__PERFORMANCE_COUNTER_VALUE_MASK 0xFFFFFFFFL 2142 //RPB_PERFCOUNTER_LO 2143 #define RPB_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 2144 #define RPB_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL 2145 //RPB_PERFCOUNTER_HI 2146 #define RPB_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 2147 #define RPB_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 2148 #define RPB_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL 2149 #define RPB_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L 2150 //RPB_PERFCOUNTER0_CFG 2151 #define RPB_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 2152 #define RPB_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 2153 #define RPB_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 2154 #define RPB_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c 2155 #define RPB_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d 2156 #define RPB_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL 2157 #define RPB_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L 2158 #define RPB_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L 2159 #define RPB_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L 2160 #define RPB_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L 2161 //RPB_PERFCOUNTER1_CFG 2162 #define RPB_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 2163 #define RPB_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 2164 #define RPB_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 2165 #define RPB_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c 2166 #define RPB_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d 2167 #define RPB_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL 2168 #define RPB_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L 2169 #define RPB_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L 2170 #define RPB_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L 2171 #define RPB_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L 2172 //RPB_PERFCOUNTER2_CFG 2173 #define RPB_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0 2174 #define RPB_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8 2175 #define RPB_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18 2176 #define RPB_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c 2177 #define RPB_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d 2178 #define RPB_PERFCOUNTER2_CFG__PERF_SEL_MASK 0x000000FFL 2179 #define RPB_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0x0000FF00L 2180 #define RPB_PERFCOUNTER2_CFG__PERF_MODE_MASK 0x0F000000L 2181 #define RPB_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000L 2182 #define RPB_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000L 2183 //RPB_PERFCOUNTER3_CFG 2184 #define RPB_PERFCOUNTER3_CFG__PERF_SEL__SHIFT 0x0 2185 #define RPB_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT 0x8 2186 #define RPB_PERFCOUNTER3_CFG__PERF_MODE__SHIFT 0x18 2187 #define RPB_PERFCOUNTER3_CFG__ENABLE__SHIFT 0x1c 2188 #define RPB_PERFCOUNTER3_CFG__CLEAR__SHIFT 0x1d 2189 #define RPB_PERFCOUNTER3_CFG__PERF_SEL_MASK 0x000000FFL 2190 #define RPB_PERFCOUNTER3_CFG__PERF_SEL_END_MASK 0x0000FF00L 2191 #define RPB_PERFCOUNTER3_CFG__PERF_MODE_MASK 0x0F000000L 2192 #define RPB_PERFCOUNTER3_CFG__ENABLE_MASK 0x10000000L 2193 #define RPB_PERFCOUNTER3_CFG__CLEAR_MASK 0x20000000L 2194 //RPB_PERFCOUNTER_RSLT_CNTL 2195 #define RPB_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 2196 #define RPB_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 2197 #define RPB_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 2198 #define RPB_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 2199 #define RPB_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 2200 #define RPB_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a 2201 #define RPB_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL 2202 #define RPB_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L 2203 #define RPB_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L 2204 #define RPB_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L 2205 #define RPB_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L 2206 #define RPB_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L 2207 //RPB_RD_QUEUE_CNTL 2208 #define RPB_RD_QUEUE_CNTL__ARB_MODE__SHIFT 0x0 2209 #define RPB_RD_QUEUE_CNTL__Q4_SHARED__SHIFT 0x1 2210 #define RPB_RD_QUEUE_CNTL__Q5_SHARED__SHIFT 0x2 2211 #define RPB_RD_QUEUE_CNTL__Q4_UNITID_EA_MODE__SHIFT 0x3 2212 #define RPB_RD_QUEUE_CNTL__Q5_UNITID_EA_MODE__SHIFT 0x4 2213 #define RPB_RD_QUEUE_CNTL__Q4_PATTERN_LOW__SHIFT 0x5 2214 #define RPB_RD_QUEUE_CNTL__Q4_PATTERN_HIGH__SHIFT 0xa 2215 #define RPB_RD_QUEUE_CNTL__Q5_PATTERN_LOW__SHIFT 0x10 2216 #define RPB_RD_QUEUE_CNTL__Q5_PATTERN_HIGH__SHIFT 0x15 2217 #define RPB_RD_QUEUE_CNTL__ARB_MODE_MASK 0x00000001L 2218 #define RPB_RD_QUEUE_CNTL__Q4_SHARED_MASK 0x00000002L 2219 #define RPB_RD_QUEUE_CNTL__Q5_SHARED_MASK 0x00000004L 2220 #define RPB_RD_QUEUE_CNTL__Q4_UNITID_EA_MODE_MASK 0x00000008L 2221 #define RPB_RD_QUEUE_CNTL__Q5_UNITID_EA_MODE_MASK 0x00000010L 2222 #define RPB_RD_QUEUE_CNTL__Q4_PATTERN_LOW_MASK 0x000003E0L 2223 #define RPB_RD_QUEUE_CNTL__Q4_PATTERN_HIGH_MASK 0x0000FC00L 2224 #define RPB_RD_QUEUE_CNTL__Q5_PATTERN_LOW_MASK 0x001F0000L 2225 #define RPB_RD_QUEUE_CNTL__Q5_PATTERN_HIGH_MASK 0x07E00000L 2226 //RPB_RD_QUEUE_CNTL2 2227 #define RPB_RD_QUEUE_CNTL2__Q4_PATTERN_MASK_LOW__SHIFT 0x0 2228 #define RPB_RD_QUEUE_CNTL2__Q4_PATTERN_MASK_HIGH__SHIFT 0x5 2229 #define RPB_RD_QUEUE_CNTL2__Q5_PATTERN_MASK_LOW__SHIFT 0xb 2230 #define RPB_RD_QUEUE_CNTL2__Q5_PATTERN_MASK_HIGH__SHIFT 0x10 2231 #define RPB_RD_QUEUE_CNTL2__Q4_PATTERN_MASK_LOW_MASK 0x0000001FL 2232 #define RPB_RD_QUEUE_CNTL2__Q4_PATTERN_MASK_HIGH_MASK 0x000007E0L 2233 #define RPB_RD_QUEUE_CNTL2__Q5_PATTERN_MASK_LOW_MASK 0x0000F800L 2234 #define RPB_RD_QUEUE_CNTL2__Q5_PATTERN_MASK_HIGH_MASK 0x003F0000L 2235 //RPB_WR_QUEUE_CNTL 2236 #define RPB_WR_QUEUE_CNTL__ARB_MODE__SHIFT 0x0 2237 #define RPB_WR_QUEUE_CNTL__Q4_SHARED__SHIFT 0x1 2238 #define RPB_WR_QUEUE_CNTL__Q5_SHARED__SHIFT 0x2 2239 #define RPB_WR_QUEUE_CNTL__Q4_UNITID_EA_MODE__SHIFT 0x3 2240 #define RPB_WR_QUEUE_CNTL__Q5_UNITID_EA_MODE__SHIFT 0x4 2241 #define RPB_WR_QUEUE_CNTL__Q4_PATTERN_LOW__SHIFT 0x5 2242 #define RPB_WR_QUEUE_CNTL__Q4_PATTERN_HIGH__SHIFT 0xa 2243 #define RPB_WR_QUEUE_CNTL__Q5_PATTERN_LOW__SHIFT 0x10 2244 #define RPB_WR_QUEUE_CNTL__Q5_PATTERN_HIGH__SHIFT 0x15 2245 #define RPB_WR_QUEUE_CNTL__ARB_MODE_MASK 0x00000001L 2246 #define RPB_WR_QUEUE_CNTL__Q4_SHARED_MASK 0x00000002L 2247 #define RPB_WR_QUEUE_CNTL__Q5_SHARED_MASK 0x00000004L 2248 #define RPB_WR_QUEUE_CNTL__Q4_UNITID_EA_MODE_MASK 0x00000008L 2249 #define RPB_WR_QUEUE_CNTL__Q5_UNITID_EA_MODE_MASK 0x00000010L 2250 #define RPB_WR_QUEUE_CNTL__Q4_PATTERN_LOW_MASK 0x000003E0L 2251 #define RPB_WR_QUEUE_CNTL__Q4_PATTERN_HIGH_MASK 0x0000FC00L 2252 #define RPB_WR_QUEUE_CNTL__Q5_PATTERN_LOW_MASK 0x001F0000L 2253 #define RPB_WR_QUEUE_CNTL__Q5_PATTERN_HIGH_MASK 0x07E00000L 2254 //RPB_WR_QUEUE_CNTL2 2255 #define RPB_WR_QUEUE_CNTL2__Q4_PATTERN_MASK_LOW__SHIFT 0x0 2256 #define RPB_WR_QUEUE_CNTL2__Q4_PATTERN_MASK_HIGH__SHIFT 0x5 2257 #define RPB_WR_QUEUE_CNTL2__Q5_PATTERN_MASK_LOW__SHIFT 0xb 2258 #define RPB_WR_QUEUE_CNTL2__Q5_PATTERN_MASK_HIGH__SHIFT 0x10 2259 #define RPB_WR_QUEUE_CNTL2__Q4_PATTERN_MASK_LOW_MASK 0x0000001FL 2260 #define RPB_WR_QUEUE_CNTL2__Q4_PATTERN_MASK_HIGH_MASK 0x000007E0L 2261 #define RPB_WR_QUEUE_CNTL2__Q5_PATTERN_MASK_LOW_MASK 0x0000F800L 2262 #define RPB_WR_QUEUE_CNTL2__Q5_PATTERN_MASK_HIGH_MASK 0x003F0000L 2263 //RPB_ATS_CNTL 2264 #define RPB_ATS_CNTL__PAGE_MIN_LATENCY_ENABLE__SHIFT 0x0 2265 #define RPB_ATS_CNTL__TR_MIN_LATENCY_ENABLE__SHIFT 0x1 2266 #define RPB_ATS_CNTL__SWITCH_THRESHOLD__SHIFT 0x2 2267 #define RPB_ATS_CNTL__TIME_SLICE__SHIFT 0x7 2268 #define RPB_ATS_CNTL__ATCTR_GFX_SWITCH_NUM__SHIFT 0xf 2269 #define RPB_ATS_CNTL__ATCPAGE_SWITCH_NUM__SHIFT 0x13 2270 #define RPB_ATS_CNTL__WR_AT__SHIFT 0x17 2271 #define RPB_ATS_CNTL__MM_VC_SWITCH__SHIFT 0x19 2272 #define RPB_ATS_CNTL__GC_VC_SWITCH__SHIFT 0x1a 2273 #define RPB_ATS_CNTL__PAGE_MIN_LATENCY_ENABLE_MASK 0x00000001L 2274 #define RPB_ATS_CNTL__TR_MIN_LATENCY_ENABLE_MASK 0x00000002L 2275 #define RPB_ATS_CNTL__SWITCH_THRESHOLD_MASK 0x0000007CL 2276 #define RPB_ATS_CNTL__TIME_SLICE_MASK 0x00007F80L 2277 #define RPB_ATS_CNTL__ATCTR_GFX_SWITCH_NUM_MASK 0x00078000L 2278 #define RPB_ATS_CNTL__ATCPAGE_SWITCH_NUM_MASK 0x00780000L 2279 #define RPB_ATS_CNTL__WR_AT_MASK 0x01800000L 2280 #define RPB_ATS_CNTL__MM_VC_SWITCH_MASK 0x02000000L 2281 #define RPB_ATS_CNTL__GC_VC_SWITCH_MASK 0x04000000L 2282 //RPB_ATS_CNTL2 2283 #define RPB_ATS_CNTL2__INVAL_COM_CMD__SHIFT 0x0 2284 #define RPB_ATS_CNTL2__TRANS_CMD__SHIFT 0x6 2285 #define RPB_ATS_CNTL2__PAGE_REQ_CMD__SHIFT 0xc 2286 #define RPB_ATS_CNTL2__PAGE_ROUTING_CODE__SHIFT 0x12 2287 #define RPB_ATS_CNTL2__INVAL_COM_ROUTING_CODE__SHIFT 0x15 2288 #define RPB_ATS_CNTL2__VENDOR_ID__SHIFT 0x18 2289 #define RPB_ATS_CNTL2__RPB_VC5_CRD__SHIFT 0x1a 2290 #define RPB_ATS_CNTL2__INVAL_COM_CMD_MASK 0x0000003FL 2291 #define RPB_ATS_CNTL2__TRANS_CMD_MASK 0x00000FC0L 2292 #define RPB_ATS_CNTL2__PAGE_REQ_CMD_MASK 0x0003F000L 2293 #define RPB_ATS_CNTL2__PAGE_ROUTING_CODE_MASK 0x001C0000L 2294 #define RPB_ATS_CNTL2__INVAL_COM_ROUTING_CODE_MASK 0x00E00000L 2295 #define RPB_ATS_CNTL2__VENDOR_ID_MASK 0x03000000L 2296 #define RPB_ATS_CNTL2__RPB_VC5_CRD_MASK 0x7C000000L 2297 //RPB_ATS_CNTL3 2298 #define RPB_ATS_CNTL3__RPB_ATS_MM_TR__SHIFT 0x0 2299 #define RPB_ATS_CNTL3__RPB_ATS_GFX_TR__SHIFT 0x9 2300 #define RPB_ATS_CNTL3__RPB_ATS_PR__SHIFT 0x12 2301 #define RPB_ATS_CNTL3__RPB_ATS_MM_TR_MASK 0x000001FFL 2302 #define RPB_ATS_CNTL3__RPB_ATS_GFX_TR_MASK 0x0003FE00L 2303 #define RPB_ATS_CNTL3__RPB_ATS_PR_MASK 0x07FC0000L 2304 //RPB_DF_SDPPORT_CNTL 2305 #define RPB_DF_SDPPORT_CNTL__DF_REQ_CRD__SHIFT 0x0 2306 #define RPB_DF_SDPPORT_CNTL__DF_DATA_CRD__SHIFT 0x6 2307 #define RPB_DF_SDPPORT_CNTL__DF_HALT_THRESHOLD__SHIFT 0xc 2308 #define RPB_DF_SDPPORT_CNTL__DF_RELEASE_CREDIT_MODE__SHIFT 0x10 2309 #define RPB_DF_SDPPORT_CNTL__DF_INSERT_PARITY_ERR__SHIFT 0x11 2310 #define RPB_DF_SDPPORT_CNTL__DF_BUSY_INCLUDE_CONN__SHIFT 0x12 2311 #define RPB_DF_SDPPORT_CNTL__RESERVED__SHIFT 0x13 2312 #define RPB_DF_SDPPORT_CNTL__DF_REQ_CRD_MASK 0x0000003FL 2313 #define RPB_DF_SDPPORT_CNTL__DF_DATA_CRD_MASK 0x00000FC0L 2314 #define RPB_DF_SDPPORT_CNTL__DF_HALT_THRESHOLD_MASK 0x0000F000L 2315 #define RPB_DF_SDPPORT_CNTL__DF_RELEASE_CREDIT_MODE_MASK 0x00010000L 2316 #define RPB_DF_SDPPORT_CNTL__DF_INSERT_PARITY_ERR_MASK 0x00020000L 2317 #define RPB_DF_SDPPORT_CNTL__DF_BUSY_INCLUDE_CONN_MASK 0x00040000L 2318 #define RPB_DF_SDPPORT_CNTL__RESERVED_MASK 0xFFF80000L 2319 //RPB_SDPPORT_CNTL 2320 #define RPB_SDPPORT_CNTL__NBIF_DMA_SELF_ACTIVATE__SHIFT 0x0 2321 #define RPB_SDPPORT_CNTL__NBIF_DMA_CFG_MODE__SHIFT 0x1 2322 #define RPB_SDPPORT_CNTL__NBIF_DMA_ENABLE_REISSUE_CREDIT__SHIFT 0x3 2323 #define RPB_SDPPORT_CNTL__NBIF_DMA_ENABLE_SATURATE_COUNTER__SHIFT 0x4 2324 #define RPB_SDPPORT_CNTL__NBIF_DMA_ENABLE_DISRUPT_FULLDIS__SHIFT 0x5 2325 #define RPB_SDPPORT_CNTL__NBIF_DMA_HALT_THRESHOLD__SHIFT 0x6 2326 #define RPB_SDPPORT_CNTL__NBIF_HST_SELF_ACTIVATE__SHIFT 0xa 2327 #define RPB_SDPPORT_CNTL__NBIF_HST_CFG_MODE__SHIFT 0xb 2328 #define RPB_SDPPORT_CNTL__NBIF_HST_ENABLE_REISSUE_CREDIT__SHIFT 0xd 2329 #define RPB_SDPPORT_CNTL__NBIF_HST_ENABLE_SATURATE_COUNTER__SHIFT 0xe 2330 #define RPB_SDPPORT_CNTL__NBIF_HST_ENABLE_DISRUPT_FULLDIS__SHIFT 0xf 2331 #define RPB_SDPPORT_CNTL__NBIF_HST_HALT_THRESHOLD__SHIFT 0x10 2332 #define RPB_SDPPORT_CNTL__NBIF_HST_PASSIVE_MODE__SHIFT 0x14 2333 #define RPB_SDPPORT_CNTL__NBIF_HST_QUICK_COMACK__SHIFT 0x15 2334 #define RPB_SDPPORT_CNTL__DF_SDPVDCI_RDRSPCKEN__SHIFT 0x16 2335 #define RPB_SDPPORT_CNTL__DF_SDPVDCI_RDRSPCKENRCV__SHIFT 0x17 2336 #define RPB_SDPPORT_CNTL__DF_SDPVDCI_RDRSPDATACKEN__SHIFT 0x18 2337 #define RPB_SDPPORT_CNTL__DF_SDPVDCI_RDRSPDATACKENRCV__SHIFT 0x19 2338 #define RPB_SDPPORT_CNTL__DF_SDPVDCI_WRRSPCKEN__SHIFT 0x1a 2339 #define RPB_SDPPORT_CNTL__DF_SDPVDCI_WRRSPCKENRCV__SHIFT 0x1b 2340 #define RPB_SDPPORT_CNTL__RESERVED__SHIFT 0x1c 2341 #define RPB_SDPPORT_CNTL__NBIF_DMA_SELF_ACTIVATE_MASK 0x00000001L 2342 #define RPB_SDPPORT_CNTL__NBIF_DMA_CFG_MODE_MASK 0x00000006L 2343 #define RPB_SDPPORT_CNTL__NBIF_DMA_ENABLE_REISSUE_CREDIT_MASK 0x00000008L 2344 #define RPB_SDPPORT_CNTL__NBIF_DMA_ENABLE_SATURATE_COUNTER_MASK 0x00000010L 2345 #define RPB_SDPPORT_CNTL__NBIF_DMA_ENABLE_DISRUPT_FULLDIS_MASK 0x00000020L 2346 #define RPB_SDPPORT_CNTL__NBIF_DMA_HALT_THRESHOLD_MASK 0x000003C0L 2347 #define RPB_SDPPORT_CNTL__NBIF_HST_SELF_ACTIVATE_MASK 0x00000400L 2348 #define RPB_SDPPORT_CNTL__NBIF_HST_CFG_MODE_MASK 0x00001800L 2349 #define RPB_SDPPORT_CNTL__NBIF_HST_ENABLE_REISSUE_CREDIT_MASK 0x00002000L 2350 #define RPB_SDPPORT_CNTL__NBIF_HST_ENABLE_SATURATE_COUNTER_MASK 0x00004000L 2351 #define RPB_SDPPORT_CNTL__NBIF_HST_ENABLE_DISRUPT_FULLDIS_MASK 0x00008000L 2352 #define RPB_SDPPORT_CNTL__NBIF_HST_HALT_THRESHOLD_MASK 0x000F0000L 2353 #define RPB_SDPPORT_CNTL__NBIF_HST_PASSIVE_MODE_MASK 0x00100000L 2354 #define RPB_SDPPORT_CNTL__NBIF_HST_QUICK_COMACK_MASK 0x00200000L 2355 #define RPB_SDPPORT_CNTL__DF_SDPVDCI_RDRSPCKEN_MASK 0x00400000L 2356 #define RPB_SDPPORT_CNTL__DF_SDPVDCI_RDRSPCKENRCV_MASK 0x00800000L 2357 #define RPB_SDPPORT_CNTL__DF_SDPVDCI_RDRSPDATACKEN_MASK 0x01000000L 2358 #define RPB_SDPPORT_CNTL__DF_SDPVDCI_RDRSPDATACKENRCV_MASK 0x02000000L 2359 #define RPB_SDPPORT_CNTL__DF_SDPVDCI_WRRSPCKEN_MASK 0x04000000L 2360 #define RPB_SDPPORT_CNTL__DF_SDPVDCI_WRRSPCKENRCV_MASK 0x08000000L 2361 #define RPB_SDPPORT_CNTL__RESERVED_MASK 0xF0000000L 2362 //RPB_NBIF_SDPPORT_CNTL 2363 #define RPB_NBIF_SDPPORT_CNTL__NBIF_DMA_WRRSP_CRD__SHIFT 0x0 2364 #define RPB_NBIF_SDPPORT_CNTL__NBIF_DMA_RDRSP_CRD__SHIFT 0x8 2365 #define RPB_NBIF_SDPPORT_CNTL__NBIF_HST_REQ_CRD__SHIFT 0x10 2366 #define RPB_NBIF_SDPPORT_CNTL__NBIF_HST_DATA_CRD__SHIFT 0x18 2367 #define RPB_NBIF_SDPPORT_CNTL__NBIF_DMA_WRRSP_CRD_MASK 0x000000FFL 2368 #define RPB_NBIF_SDPPORT_CNTL__NBIF_DMA_RDRSP_CRD_MASK 0x0000FF00L 2369 #define RPB_NBIF_SDPPORT_CNTL__NBIF_HST_REQ_CRD_MASK 0x00FF0000L 2370 #define RPB_NBIF_SDPPORT_CNTL__NBIF_HST_DATA_CRD_MASK 0xFF000000L 2371 2372 2373 2374 2375 2376 2377 2378 #endif 2379
