1// SPDX-License-Identifier: GPL-2.0-or-later 2// Copyright 2019 IBM Corp. 3 4#include <dt-bindings/interrupt-controller/arm-gic.h> 5#include <dt-bindings/interrupt-controller/aspeed-scu-ic.h> 6#include <dt-bindings/clock/ast2600-clock.h> 7 8/ { 9 model = "Aspeed BMC"; 10 compatible = "aspeed,ast2600"; 11 #address-cells = <1>; 12 #size-cells = <1>; 13 interrupt-parent = <&gic>; 14 15 aliases { 16 i2c0 = &i2c0; 17 i2c1 = &i2c1; 18 i2c2 = &i2c2; 19 i2c3 = &i2c3; 20 i2c4 = &i2c4; 21 i2c5 = &i2c5; 22 i2c6 = &i2c6; 23 i2c7 = &i2c7; 24 i2c8 = &i2c8; 25 i2c9 = &i2c9; 26 i2c10 = &i2c10; 27 i2c11 = &i2c11; 28 i2c12 = &i2c12; 29 i2c13 = &i2c13; 30 i2c14 = &i2c14; 31 i2c15 = &i2c15; 32 serial0 = &uart1; 33 serial1 = &uart2; 34 serial2 = &uart3; 35 serial3 = &uart4; 36 serial4 = &uart5; 37 serial5 = &vuart1; 38 serial6 = &vuart2; 39 }; 40 41 42 cpus { 43 #address-cells = <1>; 44 #size-cells = <0>; 45 enable-method = "aspeed,ast2600-smp"; 46 47 cpu@f00 { 48 compatible = "arm,cortex-a7"; 49 device_type = "cpu"; 50 reg = <0xf00>; 51 }; 52 53 cpu@f01 { 54 compatible = "arm,cortex-a7"; 55 device_type = "cpu"; 56 reg = <0xf01>; 57 }; 58 }; 59 60 timer { 61 compatible = "arm,armv7-timer"; 62 interrupt-parent = <&gic>; 63 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 64 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 65 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 66 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; 67 clocks = <&syscon ASPEED_CLK_HPLL>; 68 arm,cpu-registers-not-fw-configured; 69 always-on; 70 }; 71 72 edac: sdram@1e6e0000 { 73 compatible = "aspeed,ast2600-sdram-edac", "syscon"; 74 reg = <0x1e6e0000 0x174>; 75 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 76 }; 77 78 ahb { 79 compatible = "simple-bus"; 80 #address-cells = <1>; 81 #size-cells = <1>; 82 device_type = "soc"; 83 ranges; 84 85 gic: interrupt-controller@40461000 { 86 compatible = "arm,cortex-a7-gic"; 87 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; 88 #interrupt-cells = <3>; 89 interrupt-controller; 90 interrupt-parent = <&gic>; 91 reg = <0x40461000 0x1000>, 92 <0x40462000 0x1000>, 93 <0x40464000 0x2000>, 94 <0x40466000 0x2000>; 95 }; 96 97 fmc: spi@1e620000 { 98 reg = < 0x1e620000 0xc4 99 0x20000000 0x10000000 >; 100 #address-cells = <1>; 101 #size-cells = <0>; 102 compatible = "aspeed,ast2600-fmc"; 103 clocks = <&syscon ASPEED_CLK_AHB>; 104 status = "disabled"; 105 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 106 flash@0 { 107 reg = < 0 >; 108 compatible = "jedec,spi-nor"; 109 spi-max-frequency = <50000000>; 110 status = "disabled"; 111 }; 112 flash@1 { 113 reg = < 1 >; 114 compatible = "jedec,spi-nor"; 115 spi-max-frequency = <50000000>; 116 status = "disabled"; 117 }; 118 flash@2 { 119 reg = < 2 >; 120 compatible = "jedec,spi-nor"; 121 spi-max-frequency = <50000000>; 122 status = "disabled"; 123 }; 124 }; 125 126 spi1: spi@1e630000 { 127 reg = < 0x1e630000 0xc4 128 0x30000000 0x10000000 >; 129 #address-cells = <1>; 130 #size-cells = <0>; 131 compatible = "aspeed,ast2600-spi"; 132 clocks = <&syscon ASPEED_CLK_AHB>; 133 status = "disabled"; 134 flash@0 { 135 reg = < 0 >; 136 compatible = "jedec,spi-nor"; 137 spi-max-frequency = <50000000>; 138 status = "disabled"; 139 }; 140 flash@1 { 141 reg = < 1 >; 142 compatible = "jedec,spi-nor"; 143 spi-max-frequency = <50000000>; 144 status = "disabled"; 145 }; 146 }; 147 148 spi2: spi@1e631000 { 149 reg = < 0x1e631000 0xc4 150 0x50000000 0x10000000 >; 151 #address-cells = <1>; 152 #size-cells = <0>; 153 compatible = "aspeed,ast2600-spi"; 154 clocks = <&syscon ASPEED_CLK_AHB>; 155 status = "disabled"; 156 flash@0 { 157 reg = < 0 >; 158 compatible = "jedec,spi-nor"; 159 spi-max-frequency = <50000000>; 160 status = "disabled"; 161 }; 162 flash@1 { 163 reg = < 1 >; 164 compatible = "jedec,spi-nor"; 165 spi-max-frequency = <50000000>; 166 status = "disabled"; 167 }; 168 flash@2 { 169 reg = < 2 >; 170 compatible = "jedec,spi-nor"; 171 spi-max-frequency = <50000000>; 172 status = "disabled"; 173 }; 174 }; 175 176 mdio0: mdio@1e650000 { 177 compatible = "aspeed,ast2600-mdio"; 178 reg = <0x1e650000 0x8>; 179 #address-cells = <1>; 180 #size-cells = <0>; 181 status = "disabled"; 182 pinctrl-names = "default"; 183 pinctrl-0 = <&pinctrl_mdio1_default>; 184 }; 185 186 mdio1: mdio@1e650008 { 187 compatible = "aspeed,ast2600-mdio"; 188 reg = <0x1e650008 0x8>; 189 #address-cells = <1>; 190 #size-cells = <0>; 191 status = "disabled"; 192 pinctrl-names = "default"; 193 pinctrl-0 = <&pinctrl_mdio2_default>; 194 }; 195 196 mdio2: mdio@1e650010 { 197 compatible = "aspeed,ast2600-mdio"; 198 reg = <0x1e650010 0x8>; 199 #address-cells = <1>; 200 #size-cells = <0>; 201 status = "disabled"; 202 pinctrl-names = "default"; 203 pinctrl-0 = <&pinctrl_mdio3_default>; 204 }; 205 206 mdio3: mdio@1e650018 { 207 compatible = "aspeed,ast2600-mdio"; 208 reg = <0x1e650018 0x8>; 209 #address-cells = <1>; 210 #size-cells = <0>; 211 status = "disabled"; 212 pinctrl-names = "default"; 213 pinctrl-0 = <&pinctrl_mdio4_default>; 214 }; 215 216 mac0: ftgmac@1e660000 { 217 compatible = "aspeed,ast2600-mac", "faraday,ftgmac100"; 218 reg = <0x1e660000 0x180>; 219 #address-cells = <1>; 220 #size-cells = <0>; 221 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 222 clocks = <&syscon ASPEED_CLK_GATE_MAC1CLK>; 223 status = "disabled"; 224 }; 225 226 mac1: ftgmac@1e680000 { 227 compatible = "aspeed,ast2600-mac", "faraday,ftgmac100"; 228 reg = <0x1e680000 0x180>; 229 #address-cells = <1>; 230 #size-cells = <0>; 231 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 232 clocks = <&syscon ASPEED_CLK_GATE_MAC2CLK>; 233 status = "disabled"; 234 }; 235 236 mac2: ftgmac@1e670000 { 237 compatible = "aspeed,ast2600-mac", "faraday,ftgmac100"; 238 reg = <0x1e670000 0x180>; 239 #address-cells = <1>; 240 #size-cells = <0>; 241 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 242 clocks = <&syscon ASPEED_CLK_GATE_MAC3CLK>; 243 status = "disabled"; 244 }; 245 246 mac3: ftgmac@1e690000 { 247 compatible = "aspeed,ast2600-mac", "faraday,ftgmac100"; 248 reg = <0x1e690000 0x180>; 249 #address-cells = <1>; 250 #size-cells = <0>; 251 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 252 clocks = <&syscon ASPEED_CLK_GATE_MAC4CLK>; 253 status = "disabled"; 254 }; 255 256 ehci0: usb@1e6a1000 { 257 compatible = "aspeed,ast2600-ehci", "generic-ehci"; 258 reg = <0x1e6a1000 0x100>; 259 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 260 clocks = <&syscon ASPEED_CLK_GATE_USBPORT1CLK>; 261 pinctrl-names = "default"; 262 pinctrl-0 = <&pinctrl_usb2ah_default>; 263 status = "disabled"; 264 }; 265 266 ehci1: usb@1e6a3000 { 267 compatible = "aspeed,ast2600-ehci", "generic-ehci"; 268 reg = <0x1e6a3000 0x100>; 269 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 270 clocks = <&syscon ASPEED_CLK_GATE_USBPORT2CLK>; 271 pinctrl-names = "default"; 272 pinctrl-0 = <&pinctrl_usb2bh_default>; 273 status = "disabled"; 274 }; 275 276 uhci: usb@1e6b0000 { 277 compatible = "aspeed,ast2600-uhci", "generic-uhci"; 278 reg = <0x1e6b0000 0x100>; 279 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 280 #ports = <2>; 281 clocks = <&syscon ASPEED_CLK_GATE_USBUHCICLK>; 282 status = "disabled"; 283 /* 284 * No default pinmux, it will follow EHCI, use an 285 * explicit pinmux override if EHCI is not enabled. 286 */ 287 }; 288 289 vhub: usb-vhub@1e6a0000 { 290 compatible = "aspeed,ast2600-usb-vhub"; 291 reg = <0x1e6a0000 0x350>; 292 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 293 clocks = <&syscon ASPEED_CLK_GATE_USBPORT1CLK>; 294 aspeed,vhub-downstream-ports = <7>; 295 aspeed,vhub-generic-endpoints = <21>; 296 pinctrl-names = "default"; 297 pinctrl-0 = <&pinctrl_usb2ad_default>; 298 status = "disabled"; 299 }; 300 301 apb { 302 compatible = "simple-bus"; 303 #address-cells = <1>; 304 #size-cells = <1>; 305 ranges; 306 307 syscon: syscon@1e6e2000 { 308 compatible = "aspeed,ast2600-scu", "syscon", "simple-mfd"; 309 reg = <0x1e6e2000 0x1000>; 310 ranges = <0 0x1e6e2000 0x1000>; 311 #address-cells = <1>; 312 #size-cells = <1>; 313 #clock-cells = <1>; 314 #reset-cells = <1>; 315 316 pinctrl: pinctrl { 317 compatible = "aspeed,ast2600-pinctrl"; 318 }; 319 320 silicon-id@14 { 321 compatible = "aspeed,ast2600-silicon-id", "aspeed,silicon-id"; 322 reg = <0x14 0x4 0x5b0 0x8>; 323 }; 324 325 smp-memram@180 { 326 compatible = "aspeed,ast2600-smpmem"; 327 reg = <0x180 0x40>; 328 }; 329 330 scu_ic0: interrupt-controller@560 { 331 #interrupt-cells = <1>; 332 compatible = "aspeed,ast2600-scu-ic0"; 333 reg = <0x560 0x4>; 334 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 335 interrupt-controller; 336 }; 337 338 scu_ic1: interrupt-controller@570 { 339 #interrupt-cells = <1>; 340 compatible = "aspeed,ast2600-scu-ic1"; 341 reg = <0x570 0x4>; 342 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 343 interrupt-controller; 344 }; 345 }; 346 347 rng: hwrng@1e6e2524 { 348 compatible = "timeriomem_rng"; 349 reg = <0x1e6e2524 0x4>; 350 period = <1>; 351 quality = <100>; 352 }; 353 354 xdma: xdma@1e6e7000 { 355 compatible = "aspeed,ast2600-xdma"; 356 reg = <0x1e6e7000 0x100>; 357 clocks = <&syscon ASPEED_CLK_GATE_BCLK>; 358 resets = <&syscon ASPEED_RESET_DEV_XDMA>, <&syscon ASPEED_RESET_RC_XDMA>; 359 reset-names = "device", "root-complex"; 360 interrupts-extended = <&gic GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 361 <&scu_ic0 ASPEED_AST2600_SCU_IC0_PCIE_PERST_LO_TO_HI>; 362 aspeed,pcie-device = "bmc"; 363 aspeed,scu = <&syscon>; 364 status = "disabled"; 365 }; 366 367 gpio0: gpio@1e780000 { 368 #gpio-cells = <2>; 369 gpio-controller; 370 compatible = "aspeed,ast2600-gpio"; 371 reg = <0x1e780000 0x400>; 372 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 373 gpio-ranges = <&pinctrl 0 0 208>; 374 ngpios = <208>; 375 clocks = <&syscon ASPEED_CLK_APB2>; 376 interrupt-controller; 377 #interrupt-cells = <2>; 378 }; 379 380 sgpiom0: sgpiom@1e780500 { 381 #gpio-cells = <2>; 382 gpio-controller; 383 compatible = "aspeed,ast2600-sgpiom"; 384 reg = <0x1e780500 0x100>; 385 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 386 clocks = <&syscon ASPEED_CLK_APB2>; 387 interrupt-controller; 388 bus-frequency = <12000000>; 389 pinctrl-names = "default"; 390 pinctrl-0 = <&pinctrl_sgpm1_default>; 391 status = "disabled"; 392 }; 393 394 sgpiom1: sgpiom@1e780600 { 395 #gpio-cells = <2>; 396 gpio-controller; 397 compatible = "aspeed,ast2600-sgpiom"; 398 reg = <0x1e780600 0x100>; 399 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; 400 clocks = <&syscon ASPEED_CLK_APB2>; 401 interrupt-controller; 402 bus-frequency = <12000000>; 403 pinctrl-names = "default"; 404 pinctrl-0 = <&pinctrl_sgpm2_default>; 405 status = "disabled"; 406 }; 407 408 gpio1: gpio@1e780800 { 409 #gpio-cells = <2>; 410 gpio-controller; 411 compatible = "aspeed,ast2600-gpio"; 412 reg = <0x1e780800 0x800>; 413 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 414 gpio-ranges = <&pinctrl 0 208 36>; 415 ngpios = <36>; 416 clocks = <&syscon ASPEED_CLK_APB1>; 417 interrupt-controller; 418 #interrupt-cells = <2>; 419 }; 420 421 rtc: rtc@1e781000 { 422 compatible = "aspeed,ast2600-rtc"; 423 reg = <0x1e781000 0x18>; 424 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 425 status = "disabled"; 426 }; 427 428 timer: timer@1e782000 { 429 compatible = "aspeed,ast2600-timer"; 430 reg = <0x1e782000 0x90>; 431 interrupts-extended = <&gic GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 432 <&gic GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, 433 <&gic GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, 434 <&gic GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, 435 <&gic GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, 436 <&gic GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, 437 <&gic GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, 438 <&gic GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 439 clocks = <&syscon ASPEED_CLK_APB1>; 440 clock-names = "PCLK"; 441 status = "disabled"; 442 }; 443 444 uart1: serial@1e783000 { 445 compatible = "ns16550a"; 446 reg = <0x1e783000 0x20>; 447 reg-shift = <2>; 448 reg-io-width = <4>; 449 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 450 clocks = <&syscon ASPEED_CLK_GATE_UART1CLK>; 451 resets = <&lpc_reset 4>; 452 no-loopback-test; 453 pinctrl-names = "default"; 454 pinctrl-0 = <&pinctrl_txd1_default &pinctrl_rxd1_default>; 455 status = "disabled"; 456 }; 457 458 uart5: serial@1e784000 { 459 compatible = "ns16550a"; 460 reg = <0x1e784000 0x1000>; 461 reg-shift = <2>; 462 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 463 clocks = <&syscon ASPEED_CLK_GATE_UART5CLK>; 464 no-loopback-test; 465 }; 466 467 wdt1: watchdog@1e785000 { 468 compatible = "aspeed,ast2600-wdt"; 469 reg = <0x1e785000 0x40>; 470 }; 471 472 wdt2: watchdog@1e785040 { 473 compatible = "aspeed,ast2600-wdt"; 474 reg = <0x1e785040 0x40>; 475 status = "disabled"; 476 }; 477 478 wdt3: watchdog@1e785080 { 479 compatible = "aspeed,ast2600-wdt"; 480 reg = <0x1e785080 0x40>; 481 status = "disabled"; 482 }; 483 484 wdt4: watchdog@1e7850c0 { 485 compatible = "aspeed,ast2600-wdt"; 486 reg = <0x1e7850C0 0x40>; 487 status = "disabled"; 488 }; 489 490 lpc: lpc@1e789000 { 491 compatible = "aspeed,ast2600-lpc-v2", "simple-mfd", "syscon"; 492 reg = <0x1e789000 0x1000>; 493 reg-io-width = <4>; 494 495 #address-cells = <1>; 496 #size-cells = <1>; 497 ranges = <0x0 0x1e789000 0x1000>; 498 499 kcs1: kcs@24 { 500 compatible = "aspeed,ast2500-kcs-bmc-v2"; 501 reg = <0x24 0x1>, <0x30 0x1>, <0x3c 0x1>; 502 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 503 kcs_chan = <1>; 504 status = "disabled"; 505 }; 506 507 kcs2: kcs@28 { 508 compatible = "aspeed,ast2500-kcs-bmc-v2"; 509 reg = <0x28 0x1>, <0x34 0x1>, <0x40 0x1>; 510 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; 511 status = "disabled"; 512 }; 513 514 kcs3: kcs@2c { 515 compatible = "aspeed,ast2500-kcs-bmc-v2"; 516 reg = <0x2c 0x1>, <0x38 0x1>, <0x44 0x1>; 517 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 518 status = "disabled"; 519 }; 520 521 kcs4: kcs@114 { 522 compatible = "aspeed,ast2500-kcs-bmc-v2"; 523 reg = <0x114 0x1>, <0x118 0x1>, <0x11c 0x1>; 524 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; 525 status = "disabled"; 526 }; 527 528 lpc_ctrl: lpc-ctrl@80 { 529 compatible = "aspeed,ast2600-lpc-ctrl"; 530 reg = <0x80 0x80>; 531 clocks = <&syscon ASPEED_CLK_GATE_LCLK>; 532 status = "disabled"; 533 }; 534 535 lpc_snoop: lpc-snoop@80 { 536 compatible = "aspeed,ast2600-lpc-snoop"; 537 reg = <0x80 0x80>; 538 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; 539 clocks = <&syscon ASPEED_CLK_GATE_LCLK>; 540 status = "disabled"; 541 }; 542 543 lhc: lhc@a0 { 544 compatible = "aspeed,ast2600-lhc"; 545 reg = <0xa0 0x24 0xc8 0x8>; 546 }; 547 548 lpc_reset: reset-controller@98 { 549 compatible = "aspeed,ast2600-lpc-reset"; 550 reg = <0x98 0x4>; 551 #reset-cells = <1>; 552 }; 553 554 ibt: ibt@140 { 555 compatible = "aspeed,ast2600-ibt-bmc"; 556 reg = <0x140 0x18>; 557 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 558 status = "disabled"; 559 }; 560 }; 561 562 sdc: sdc@1e740000 { 563 compatible = "aspeed,ast2600-sd-controller"; 564 reg = <0x1e740000 0x100>; 565 #address-cells = <1>; 566 #size-cells = <1>; 567 ranges = <0 0x1e740000 0x10000>; 568 clocks = <&syscon ASPEED_CLK_GATE_SDCLK>; 569 status = "disabled"; 570 571 sdhci0: sdhci@1e740100 { 572 compatible = "aspeed,ast2600-sdhci", "sdhci"; 573 reg = <0x100 0x100>; 574 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; 575 sdhci,auto-cmd12; 576 clocks = <&syscon ASPEED_CLK_SDIO>; 577 status = "disabled"; 578 }; 579 580 sdhci1: sdhci@1e740200 { 581 compatible = "aspeed,ast2600-sdhci", "sdhci"; 582 reg = <0x200 0x100>; 583 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; 584 sdhci,auto-cmd12; 585 clocks = <&syscon ASPEED_CLK_SDIO>; 586 status = "disabled"; 587 }; 588 }; 589 590 emmc_controller: sdc@1e750000 { 591 compatible = "aspeed,ast2600-sd-controller"; 592 reg = <0x1e750000 0x100>; 593 #address-cells = <1>; 594 #size-cells = <1>; 595 ranges = <0 0x1e750000 0x10000>; 596 clocks = <&syscon ASPEED_CLK_GATE_EMMCCLK>; 597 status = "disabled"; 598 599 emmc: sdhci@1e750100 { 600 compatible = "aspeed,ast2600-sdhci"; 601 reg = <0x100 0x100>; 602 sdhci,auto-cmd12; 603 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 604 clocks = <&syscon ASPEED_CLK_EMMC>; 605 pinctrl-names = "default"; 606 pinctrl-0 = <&pinctrl_emmc_default>; 607 }; 608 }; 609 610 vuart1: serial@1e787000 { 611 compatible = "aspeed,ast2500-vuart"; 612 reg = <0x1e787000 0x40>; 613 reg-shift = <2>; 614 interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>; 615 clocks = <&syscon ASPEED_CLK_APB1>; 616 no-loopback-test; 617 status = "disabled"; 618 }; 619 620 vuart2: serial@1e788000 { 621 compatible = "aspeed,ast2500-vuart"; 622 reg = <0x1e788000 0x40>; 623 reg-shift = <2>; 624 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; 625 clocks = <&syscon ASPEED_CLK_APB1>; 626 no-loopback-test; 627 status = "disabled"; 628 }; 629 630 uart2: serial@1e78d000 { 631 compatible = "ns16550a"; 632 reg = <0x1e78d000 0x20>; 633 reg-shift = <2>; 634 reg-io-width = <4>; 635 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; 636 clocks = <&syscon ASPEED_CLK_GATE_UART2CLK>; 637 resets = <&lpc_reset 5>; 638 no-loopback-test; 639 pinctrl-names = "default"; 640 pinctrl-0 = <&pinctrl_txd2_default &pinctrl_rxd2_default>; 641 status = "disabled"; 642 }; 643 644 uart3: serial@1e78e000 { 645 compatible = "ns16550a"; 646 reg = <0x1e78e000 0x20>; 647 reg-shift = <2>; 648 reg-io-width = <4>; 649 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 650 clocks = <&syscon ASPEED_CLK_GATE_UART3CLK>; 651 resets = <&lpc_reset 6>; 652 no-loopback-test; 653 pinctrl-names = "default"; 654 pinctrl-0 = <&pinctrl_txd3_default &pinctrl_rxd3_default>; 655 status = "disabled"; 656 }; 657 658 uart4: serial@1e78f000 { 659 compatible = "ns16550a"; 660 reg = <0x1e78f000 0x20>; 661 reg-shift = <2>; 662 reg-io-width = <4>; 663 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 664 clocks = <&syscon ASPEED_CLK_GATE_UART4CLK>; 665 resets = <&lpc_reset 7>; 666 no-loopback-test; 667 pinctrl-names = "default"; 668 pinctrl-0 = <&pinctrl_txd4_default &pinctrl_rxd4_default>; 669 status = "disabled"; 670 }; 671 672 i2c: bus@1e78a000 { 673 compatible = "simple-bus"; 674 #address-cells = <1>; 675 #size-cells = <1>; 676 ranges = <0 0x1e78a000 0x1000>; 677 }; 678 679 fsim0: fsi@1e79b000 { 680 compatible = "aspeed,ast2600-fsi-master", "fsi-master"; 681 reg = <0x1e79b000 0x94>; 682 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 683 pinctrl-names = "default"; 684 pinctrl-0 = <&pinctrl_fsi1_default>; 685 clocks = <&syscon ASPEED_CLK_GATE_FSICLK>; 686 status = "disabled"; 687 }; 688 689 fsim1: fsi@1e79b100 { 690 compatible = "aspeed,ast2600-fsi-master", "fsi-master"; 691 reg = <0x1e79b100 0x94>; 692 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 693 pinctrl-names = "default"; 694 pinctrl-0 = <&pinctrl_fsi2_default>; 695 clocks = <&syscon ASPEED_CLK_GATE_FSICLK>; 696 status = "disabled"; 697 }; 698 }; 699 }; 700}; 701 702#include "aspeed-g6-pinctrl.dtsi" 703 704&i2c { 705 i2c0: i2c-bus@80 { 706 #address-cells = <1>; 707 #size-cells = <0>; 708 #interrupt-cells = <1>; 709 reg = <0x80 0x80>; 710 compatible = "aspeed,ast2600-i2c-bus"; 711 clocks = <&syscon ASPEED_CLK_APB2>; 712 resets = <&syscon ASPEED_RESET_I2C>; 713 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; 714 bus-frequency = <100000>; 715 pinctrl-names = "default"; 716 pinctrl-0 = <&pinctrl_i2c1_default>; 717 status = "disabled"; 718 }; 719 720 i2c1: i2c-bus@100 { 721 #address-cells = <1>; 722 #size-cells = <0>; 723 #interrupt-cells = <1>; 724 reg = <0x100 0x80>; 725 compatible = "aspeed,ast2600-i2c-bus"; 726 clocks = <&syscon ASPEED_CLK_APB2>; 727 resets = <&syscon ASPEED_RESET_I2C>; 728 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; 729 bus-frequency = <100000>; 730 pinctrl-names = "default"; 731 pinctrl-0 = <&pinctrl_i2c2_default>; 732 status = "disabled"; 733 }; 734 735 i2c2: i2c-bus@180 { 736 #address-cells = <1>; 737 #size-cells = <0>; 738 #interrupt-cells = <1>; 739 reg = <0x180 0x80>; 740 compatible = "aspeed,ast2600-i2c-bus"; 741 clocks = <&syscon ASPEED_CLK_APB2>; 742 resets = <&syscon ASPEED_RESET_I2C>; 743 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 744 bus-frequency = <100000>; 745 pinctrl-names = "default"; 746 pinctrl-0 = <&pinctrl_i2c3_default>; 747 status = "disabled"; 748 }; 749 750 i2c3: i2c-bus@200 { 751 #address-cells = <1>; 752 #size-cells = <0>; 753 #interrupt-cells = <1>; 754 reg = <0x200 0x80>; 755 compatible = "aspeed,ast2600-i2c-bus"; 756 clocks = <&syscon ASPEED_CLK_APB2>; 757 resets = <&syscon ASPEED_RESET_I2C>; 758 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 759 bus-frequency = <100000>; 760 pinctrl-names = "default"; 761 pinctrl-0 = <&pinctrl_i2c4_default>; 762 status = "disabled"; 763 }; 764 765 i2c4: i2c-bus@280 { 766 #address-cells = <1>; 767 #size-cells = <0>; 768 #interrupt-cells = <1>; 769 reg = <0x280 0x80>; 770 compatible = "aspeed,ast2600-i2c-bus"; 771 clocks = <&syscon ASPEED_CLK_APB2>; 772 resets = <&syscon ASPEED_RESET_I2C>; 773 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 774 bus-frequency = <100000>; 775 pinctrl-names = "default"; 776 pinctrl-0 = <&pinctrl_i2c5_default>; 777 status = "disabled"; 778 }; 779 780 i2c5: i2c-bus@300 { 781 #address-cells = <1>; 782 #size-cells = <0>; 783 #interrupt-cells = <1>; 784 reg = <0x300 0x80>; 785 compatible = "aspeed,ast2600-i2c-bus"; 786 clocks = <&syscon ASPEED_CLK_APB2>; 787 resets = <&syscon ASPEED_RESET_I2C>; 788 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 789 bus-frequency = <100000>; 790 pinctrl-names = "default"; 791 pinctrl-0 = <&pinctrl_i2c6_default>; 792 status = "disabled"; 793 }; 794 795 i2c6: i2c-bus@380 { 796 #address-cells = <1>; 797 #size-cells = <0>; 798 #interrupt-cells = <1>; 799 reg = <0x380 0x80>; 800 compatible = "aspeed,ast2600-i2c-bus"; 801 clocks = <&syscon ASPEED_CLK_APB2>; 802 resets = <&syscon ASPEED_RESET_I2C>; 803 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 804 bus-frequency = <100000>; 805 pinctrl-names = "default"; 806 pinctrl-0 = <&pinctrl_i2c7_default>; 807 status = "disabled"; 808 }; 809 810 i2c7: i2c-bus@400 { 811 #address-cells = <1>; 812 #size-cells = <0>; 813 #interrupt-cells = <1>; 814 reg = <0x400 0x80>; 815 compatible = "aspeed,ast2600-i2c-bus"; 816 clocks = <&syscon ASPEED_CLK_APB2>; 817 resets = <&syscon ASPEED_RESET_I2C>; 818 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 819 bus-frequency = <100000>; 820 pinctrl-names = "default"; 821 pinctrl-0 = <&pinctrl_i2c8_default>; 822 status = "disabled"; 823 }; 824 825 i2c8: i2c-bus@480 { 826 #address-cells = <1>; 827 #size-cells = <0>; 828 #interrupt-cells = <1>; 829 reg = <0x480 0x80>; 830 compatible = "aspeed,ast2600-i2c-bus"; 831 clocks = <&syscon ASPEED_CLK_APB2>; 832 resets = <&syscon ASPEED_RESET_I2C>; 833 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 834 bus-frequency = <100000>; 835 pinctrl-names = "default"; 836 pinctrl-0 = <&pinctrl_i2c9_default>; 837 status = "disabled"; 838 }; 839 840 i2c9: i2c-bus@500 { 841 #address-cells = <1>; 842 #size-cells = <0>; 843 #interrupt-cells = <1>; 844 reg = <0x500 0x80>; 845 compatible = "aspeed,ast2600-i2c-bus"; 846 clocks = <&syscon ASPEED_CLK_APB2>; 847 resets = <&syscon ASPEED_RESET_I2C>; 848 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; 849 bus-frequency = <100000>; 850 pinctrl-names = "default"; 851 pinctrl-0 = <&pinctrl_i2c10_default>; 852 status = "disabled"; 853 }; 854 855 i2c10: i2c-bus@580 { 856 #address-cells = <1>; 857 #size-cells = <0>; 858 #interrupt-cells = <1>; 859 reg = <0x580 0x80>; 860 compatible = "aspeed,ast2600-i2c-bus"; 861 clocks = <&syscon ASPEED_CLK_APB2>; 862 resets = <&syscon ASPEED_RESET_I2C>; 863 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; 864 bus-frequency = <100000>; 865 pinctrl-names = "default"; 866 pinctrl-0 = <&pinctrl_i2c11_default>; 867 status = "disabled"; 868 }; 869 870 i2c11: i2c-bus@600 { 871 #address-cells = <1>; 872 #size-cells = <0>; 873 #interrupt-cells = <1>; 874 reg = <0x600 0x80>; 875 compatible = "aspeed,ast2600-i2c-bus"; 876 clocks = <&syscon ASPEED_CLK_APB2>; 877 resets = <&syscon ASPEED_RESET_I2C>; 878 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; 879 bus-frequency = <100000>; 880 pinctrl-names = "default"; 881 pinctrl-0 = <&pinctrl_i2c12_default>; 882 status = "disabled"; 883 }; 884 885 i2c12: i2c-bus@680 { 886 #address-cells = <1>; 887 #size-cells = <0>; 888 #interrupt-cells = <1>; 889 reg = <0x680 0x80>; 890 compatible = "aspeed,ast2600-i2c-bus"; 891 clocks = <&syscon ASPEED_CLK_APB2>; 892 resets = <&syscon ASPEED_RESET_I2C>; 893 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; 894 bus-frequency = <100000>; 895 pinctrl-names = "default"; 896 pinctrl-0 = <&pinctrl_i2c13_default>; 897 status = "disabled"; 898 }; 899 900 i2c13: i2c-bus@700 { 901 #address-cells = <1>; 902 #size-cells = <0>; 903 #interrupt-cells = <1>; 904 reg = <0x700 0x80>; 905 compatible = "aspeed,ast2600-i2c-bus"; 906 clocks = <&syscon ASPEED_CLK_APB2>; 907 resets = <&syscon ASPEED_RESET_I2C>; 908 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; 909 bus-frequency = <100000>; 910 pinctrl-names = "default"; 911 pinctrl-0 = <&pinctrl_i2c14_default>; 912 status = "disabled"; 913 }; 914 915 i2c14: i2c-bus@780 { 916 #address-cells = <1>; 917 #size-cells = <0>; 918 #interrupt-cells = <1>; 919 reg = <0x780 0x80>; 920 compatible = "aspeed,ast2600-i2c-bus"; 921 clocks = <&syscon ASPEED_CLK_APB2>; 922 resets = <&syscon ASPEED_RESET_I2C>; 923 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>; 924 bus-frequency = <100000>; 925 pinctrl-names = "default"; 926 pinctrl-0 = <&pinctrl_i2c15_default>; 927 status = "disabled"; 928 }; 929 930 i2c15: i2c-bus@800 { 931 #address-cells = <1>; 932 #size-cells = <0>; 933 #interrupt-cells = <1>; 934 reg = <0x800 0x80>; 935 compatible = "aspeed,ast2600-i2c-bus"; 936 clocks = <&syscon ASPEED_CLK_APB2>; 937 resets = <&syscon ASPEED_RESET_I2C>; 938 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 939 bus-frequency = <100000>; 940 pinctrl-names = "default"; 941 pinctrl-0 = <&pinctrl_i2c16_default>; 942 status = "disabled"; 943 }; 944}; 945
