1// SPDX-License-Identifier: GPL-2.0+
2#include <dt-bindings/clock/aspeed-clock.h>
3
4/ {
5	model = "Aspeed BMC";
6	compatible = "aspeed,ast2500";
7	#address-cells = <1>;
8	#size-cells = <1>;
9	interrupt-parent = <&vic>;
10
11	aliases {
12		i2c0 = &i2c0;
13		i2c1 = &i2c1;
14		i2c2 = &i2c2;
15		i2c3 = &i2c3;
16		i2c4 = &i2c4;
17		i2c5 = &i2c5;
18		i2c6 = &i2c6;
19		i2c7 = &i2c7;
20		i2c8 = &i2c8;
21		i2c9 = &i2c9;
22		i2c10 = &i2c10;
23		i2c11 = &i2c11;
24		i2c12 = &i2c12;
25		i2c13 = &i2c13;
26		serial0 = &uart1;
27		serial1 = &uart2;
28		serial2 = &uart3;
29		serial3 = &uart4;
30		serial4 = &uart5;
31		serial5 = &vuart;
32	};
33
34	cpus {
35		#address-cells = <1>;
36		#size-cells = <0>;
37
38		cpu@0 {
39			compatible = "arm,arm1176jzf-s";
40			device_type = "cpu";
41			reg = <0>;
42		};
43	};
44
45	memory@80000000 {
46		device_type = "memory";
47		reg = <0x80000000 0>;
48	};
49
50	ahb {
51		compatible = "simple-bus";
52		#address-cells = <1>;
53		#size-cells = <1>;
54		ranges;
55
56		fmc: flash-controller@1e620000 {
57			reg = < 0x1e620000 0xc4
58				0x20000000 0x10000000 >;
59			#address-cells = <1>;
60			#size-cells = <0>;
61			compatible = "aspeed,ast2500-fmc";
62			clocks = <&syscon ASPEED_CLK_AHB>;
63			status = "disabled";
64			interrupts = <19>;
65			flash@0 {
66				reg = < 0 >;
67				compatible = "jedec,spi-nor";
68				status = "disabled";
69			};
70			flash@1 {
71				reg = < 1 >;
72				compatible = "jedec,spi-nor";
73				status = "disabled";
74			};
75			flash@2 {
76				reg = < 2 >;
77				compatible = "jedec,spi-nor";
78				status = "disabled";
79			};
80		};
81
82		spi1: flash-controller@1e630000 {
83			reg = < 0x1e630000 0xc4
84				0x30000000 0x08000000 >;
85			#address-cells = <1>;
86			#size-cells = <0>;
87			compatible = "aspeed,ast2500-spi";
88			clocks = <&syscon ASPEED_CLK_AHB>;
89			status = "disabled";
90			flash@0 {
91				reg = < 0 >;
92				compatible = "jedec,spi-nor";
93				status = "disabled";
94			};
95			flash@1 {
96				reg = < 1 >;
97				compatible = "jedec,spi-nor";
98				status = "disabled";
99			};
100		};
101
102		spi2: flash-controller@1e631000 {
103			reg = < 0x1e631000 0xc4
104				0x38000000 0x08000000 >;
105			#address-cells = <1>;
106			#size-cells = <0>;
107			compatible = "aspeed,ast2500-spi";
108			clocks = <&syscon ASPEED_CLK_AHB>;
109			status = "disabled";
110			flash@0 {
111				reg = < 0 >;
112				compatible = "jedec,spi-nor";
113				status = "disabled";
114			};
115			flash@1 {
116				reg = < 1 >;
117				compatible = "jedec,spi-nor";
118				status = "disabled";
119			};
120		};
121
122		vic: interrupt-controller@1e6c0080 {
123			compatible = "aspeed,ast2400-vic";
124			interrupt-controller;
125			#interrupt-cells = <1>;
126			valid-sources = <0xfefff7ff 0x0807ffff>;
127			reg = <0x1e6c0080 0x80>;
128		};
129
130		cvic: copro-interrupt-controller@1e6c2000 {
131			compatible = "aspeed,ast2500-cvic", "aspeed-cvic";
132			valid-sources = <0xffffffff>;
133			copro-sw-interrupts = <1>;
134			reg = <0x1e6c2000 0x80>;
135		};
136
137		mac0: ethernet@1e660000 {
138			compatible = "aspeed,ast2500-mac", "faraday,ftgmac100";
139			reg = <0x1e660000 0x180>;
140			interrupts = <2>;
141			clocks = <&syscon ASPEED_CLK_GATE_MAC1CLK>;
142			status = "disabled";
143		};
144
145		mac1: ethernet@1e680000 {
146			compatible = "aspeed,ast2500-mac", "faraday,ftgmac100";
147			reg = <0x1e680000 0x180>;
148			interrupts = <3>;
149			clocks = <&syscon ASPEED_CLK_GATE_MAC2CLK>;
150			status = "disabled";
151		};
152
153		ehci0: usb@1e6a1000 {
154			compatible = "aspeed,ast2500-ehci", "generic-ehci";
155			reg = <0x1e6a1000 0x100>;
156			interrupts = <5>;
157			clocks = <&syscon ASPEED_CLK_GATE_USBPORT1CLK>;
158			pinctrl-names = "default";
159			pinctrl-0 = <&pinctrl_usb2ah_default>;
160			status = "disabled";
161		};
162
163		ehci1: usb@1e6a3000 {
164			compatible = "aspeed,ast2500-ehci", "generic-ehci";
165			reg = <0x1e6a3000 0x100>;
166			interrupts = <13>;
167			clocks = <&syscon ASPEED_CLK_GATE_USBPORT2CLK>;
168			pinctrl-names = "default";
169			pinctrl-0 = <&pinctrl_usb2bh_default>;
170			status = "disabled";
171		};
172
173		uhci: usb@1e6b0000 {
174			compatible = "aspeed,ast2500-uhci", "generic-uhci";
175			reg = <0x1e6b0000 0x100>;
176			interrupts = <14>;
177			#ports = <2>;
178			clocks = <&syscon ASPEED_CLK_GATE_USBUHCICLK>;
179			status = "disabled";
180			/*
181			 * No default pinmux, it will follow EHCI, use an explicit pinmux
182			 * override if you don't enable EHCI
183			 */
184		};
185
186		vhub: usb-vhub@1e6a0000 {
187			compatible = "aspeed,ast2500-usb-vhub";
188			reg = <0x1e6a0000 0x300>;
189			interrupts = <5>;
190			clocks = <&syscon ASPEED_CLK_GATE_USBPORT1CLK>;
191			pinctrl-names = "default";
192			pinctrl-0 = <&pinctrl_usb2ad_default>;
193			status = "disabled";
194		};
195
196		apb {
197			compatible = "simple-bus";
198			#address-cells = <1>;
199			#size-cells = <1>;
200			ranges;
201
202			syscon: syscon@1e6e2000 {
203				compatible = "aspeed,ast2500-scu", "syscon", "simple-mfd";
204				reg = <0x1e6e2000 0x1a8>;
205				#address-cells = <1>;
206				#size-cells = <0>;
207				#clock-cells = <1>;
208				#reset-cells = <1>;
209
210				pinctrl: pinctrl {
211					compatible = "aspeed,g5-pinctrl";
212					aspeed,external-nodes = <&gfx &lhc>;
213
214				};
215			};
216
217			rng: hwrng@1e6e2078 {
218				compatible = "timeriomem_rng";
219				reg = <0x1e6e2078 0x4>;
220				period = <1>;
221				quality = <100>;
222			};
223
224			gfx: display@1e6e6000 {
225				compatible = "aspeed,ast2500-gfx", "syscon";
226				reg = <0x1e6e6000 0x1000>;
227				reg-io-width = <4>;
228			};
229
230			adc: adc@1e6e9000 {
231				compatible = "aspeed,ast2500-adc";
232				reg = <0x1e6e9000 0xb0>;
233				clocks = <&syscon ASPEED_CLK_APB>;
234				resets = <&syscon ASPEED_RESET_ADC>;
235				#io-channel-cells = <1>;
236				status = "disabled";
237			};
238
239			sram: sram@1e720000 {
240				compatible = "mmio-sram";
241				reg = <0x1e720000 0x9000>;	// 36K
242			};
243
244			gpio: gpio@1e780000 {
245				#gpio-cells = <2>;
246				gpio-controller;
247				compatible = "aspeed,ast2500-gpio";
248				reg = <0x1e780000 0x1000>;
249				interrupts = <20>;
250				gpio-ranges = <&pinctrl 0 0 220>;
251				clocks = <&syscon ASPEED_CLK_APB>;
252				interrupt-controller;
253			};
254
255			timer: timer@1e782000 {
256				/* This timer is a Faraday FTTMR010 derivative */
257				compatible = "aspeed,ast2400-timer";
258				reg = <0x1e782000 0x90>;
259				interrupts = <16 17 18 35 36 37 38 39>;
260				clocks = <&syscon ASPEED_CLK_APB>;
261				clock-names = "PCLK";
262			};
263
264			uart1: serial@1e783000 {
265				compatible = "ns16550a";
266				reg = <0x1e783000 0x20>;
267				reg-shift = <2>;
268				interrupts = <9>;
269				clocks = <&syscon ASPEED_CLK_GATE_UART1CLK>;
270				resets = <&lpc_reset 4>;
271				no-loopback-test;
272				status = "disabled";
273			};
274
275			uart5: serial@1e784000 {
276				compatible = "ns16550a";
277				reg = <0x1e784000 0x20>;
278				reg-shift = <2>;
279				interrupts = <10>;
280				clocks = <&syscon ASPEED_CLK_GATE_UART5CLK>;
281				no-loopback-test;
282				status = "disabled";
283			};
284
285			wdt1: watchdog@1e785000 {
286				compatible = "aspeed,ast2500-wdt";
287				reg = <0x1e785000 0x20>;
288				clocks = <&syscon ASPEED_CLK_APB>;
289			};
290
291			wdt2: watchdog@1e785020 {
292				compatible = "aspeed,ast2500-wdt";
293				reg = <0x1e785020 0x20>;
294				clocks = <&syscon ASPEED_CLK_APB>;
295			};
296
297			wdt3: watchdog@1e785040 {
298				compatible = "aspeed,ast2500-wdt";
299				reg = <0x1e785040 0x20>;
300				clocks = <&syscon ASPEED_CLK_APB>;
301				status = "disabled";
302			};
303
304			pwm_tacho: pwm-tacho-controller@1e786000 {
305				compatible = "aspeed,ast2500-pwm-tacho";
306				#address-cells = <1>;
307				#size-cells = <0>;
308				reg = <0x1e786000 0x1000>;
309				clocks = <&syscon ASPEED_CLK_24M>;
310				resets = <&syscon ASPEED_RESET_PWM>;
311				status = "disabled";
312			};
313
314			vuart: serial@1e787000 {
315				compatible = "aspeed,ast2500-vuart";
316				reg = <0x1e787000 0x40>;
317				reg-shift = <2>;
318				interrupts = <8>;
319				clocks = <&syscon ASPEED_CLK_APB>;
320				no-loopback-test;
321				status = "disabled";
322			};
323
324			lpc: lpc@1e789000 {
325				compatible = "aspeed,ast2500-lpc", "simple-mfd";
326				reg = <0x1e789000 0x1000>;
327
328				#address-cells = <1>;
329				#size-cells = <1>;
330				ranges = <0x0 0x1e789000 0x1000>;
331
332				lpc_bmc: lpc-bmc@0 {
333					compatible = "aspeed,ast2500-lpc-bmc";
334					reg = <0x0 0x80>;
335				};
336
337				lpc_host: lpc-host@80 {
338					compatible = "aspeed,ast2500-lpc-host", "simple-mfd", "syscon";
339					reg = <0x80 0x1e0>;
340					reg-io-width = <4>;
341
342					#address-cells = <1>;
343					#size-cells = <1>;
344					ranges = <0x0 0x80 0x1e0>;
345
346					lpc_ctrl: lpc-ctrl@0 {
347						compatible = "aspeed,ast2500-lpc-ctrl";
348						reg = <0x0 0x80>;
349						clocks = <&syscon ASPEED_CLK_GATE_LCLK>;
350						status = "disabled";
351					};
352
353					lpc_snoop: lpc-snoop@0 {
354						compatible = "aspeed,ast2500-lpc-snoop";
355						reg = <0x0 0x80>;
356						interrupts = <8>;
357						status = "disabled";
358					};
359
360					lhc: lhc@20 {
361						compatible = "aspeed,ast2500-lhc";
362						reg = <0x20 0x24 0x48 0x8>;
363					};
364
365					lpc_reset: reset-controller@18 {
366						compatible = "aspeed,ast2500-lpc-reset";
367						reg = <0x18 0x4>;
368						#reset-cells = <1>;
369					};
370
371					ibt: ibt@c0 {
372						compatible = "aspeed,ast2500-ibt-bmc";
373						reg = <0xc0 0x18>;
374						interrupts = <8>;
375						status = "disabled";
376					};
377				};
378			};
379
380			uart2: serial@1e78d000 {
381				compatible = "ns16550a";
382				reg = <0x1e78d000 0x20>;
383				reg-shift = <2>;
384				interrupts = <32>;
385				clocks = <&syscon ASPEED_CLK_GATE_UART2CLK>;
386				resets = <&lpc_reset 5>;
387				no-loopback-test;
388				status = "disabled";
389			};
390
391			uart3: serial@1e78e000 {
392				compatible = "ns16550a";
393				reg = <0x1e78e000 0x20>;
394				reg-shift = <2>;
395				interrupts = <33>;
396				clocks = <&syscon ASPEED_CLK_GATE_UART3CLK>;
397				resets = <&lpc_reset 6>;
398				no-loopback-test;
399				status = "disabled";
400			};
401
402			uart4: serial@1e78f000 {
403				compatible = "ns16550a";
404				reg = <0x1e78f000 0x20>;
405				reg-shift = <2>;
406				interrupts = <34>;
407				clocks = <&syscon ASPEED_CLK_GATE_UART4CLK>;
408				resets = <&lpc_reset 7>;
409				no-loopback-test;
410				status = "disabled";
411			};
412
413			i2c: i2c@1e78a000 {
414				compatible = "simple-bus";
415				#address-cells = <1>;
416				#size-cells = <1>;
417				ranges = <0 0x1e78a000 0x1000>;
418			};
419		};
420	};
421};
422
423&i2c {
424	i2c_ic: interrupt-controller@0 {
425		#interrupt-cells = <1>;
426		compatible = "aspeed,ast2500-i2c-ic";
427		reg = <0x0 0x40>;
428		interrupts = <12>;
429		interrupt-controller;
430	};
431
432	i2c0: i2c-bus@40 {
433		#address-cells = <1>;
434		#size-cells = <0>;
435		#interrupt-cells = <1>;
436
437		reg = <0x40 0x40>;
438		compatible = "aspeed,ast2500-i2c-bus";
439		clocks = <&syscon ASPEED_CLK_APB>;
440		resets = <&syscon ASPEED_RESET_I2C>;
441		bus-frequency = <100000>;
442		interrupts = <0>;
443		interrupt-parent = <&i2c_ic>;
444		status = "disabled";
445		/* Does not need pinctrl properties */
446	};
447
448	i2c1: i2c-bus@80 {
449		#address-cells = <1>;
450		#size-cells = <0>;
451		#interrupt-cells = <1>;
452
453		reg = <0x80 0x40>;
454		compatible = "aspeed,ast2500-i2c-bus";
455		clocks = <&syscon ASPEED_CLK_APB>;
456		resets = <&syscon ASPEED_RESET_I2C>;
457		bus-frequency = <100000>;
458		interrupts = <1>;
459		interrupt-parent = <&i2c_ic>;
460		status = "disabled";
461		/* Does not need pinctrl properties */
462	};
463
464	i2c2: i2c-bus@c0 {
465		#address-cells = <1>;
466		#size-cells = <0>;
467		#interrupt-cells = <1>;
468
469		reg = <0xc0 0x40>;
470		compatible = "aspeed,ast2500-i2c-bus";
471		clocks = <&syscon ASPEED_CLK_APB>;
472		resets = <&syscon ASPEED_RESET_I2C>;
473		bus-frequency = <100000>;
474		interrupts = <2>;
475		interrupt-parent = <&i2c_ic>;
476		pinctrl-names = "default";
477		pinctrl-0 = <&pinctrl_i2c3_default>;
478		status = "disabled";
479	};
480
481	i2c3: i2c-bus@100 {
482		#address-cells = <1>;
483		#size-cells = <0>;
484		#interrupt-cells = <1>;
485
486		reg = <0x100 0x40>;
487		compatible = "aspeed,ast2500-i2c-bus";
488		clocks = <&syscon ASPEED_CLK_APB>;
489		resets = <&syscon ASPEED_RESET_I2C>;
490		bus-frequency = <100000>;
491		interrupts = <3>;
492		interrupt-parent = <&i2c_ic>;
493		pinctrl-names = "default";
494		pinctrl-0 = <&pinctrl_i2c4_default>;
495		status = "disabled";
496	};
497
498	i2c4: i2c-bus@140 {
499		#address-cells = <1>;
500		#size-cells = <0>;
501		#interrupt-cells = <1>;
502
503		reg = <0x140 0x40>;
504		compatible = "aspeed,ast2500-i2c-bus";
505		clocks = <&syscon ASPEED_CLK_APB>;
506		resets = <&syscon ASPEED_RESET_I2C>;
507		bus-frequency = <100000>;
508		interrupts = <4>;
509		interrupt-parent = <&i2c_ic>;
510		pinctrl-names = "default";
511		pinctrl-0 = <&pinctrl_i2c5_default>;
512		status = "disabled";
513	};
514
515	i2c5: i2c-bus@180 {
516		#address-cells = <1>;
517		#size-cells = <0>;
518		#interrupt-cells = <1>;
519
520		reg = <0x180 0x40>;
521		compatible = "aspeed,ast2500-i2c-bus";
522		clocks = <&syscon ASPEED_CLK_APB>;
523		resets = <&syscon ASPEED_RESET_I2C>;
524		bus-frequency = <100000>;
525		interrupts = <5>;
526		interrupt-parent = <&i2c_ic>;
527		pinctrl-names = "default";
528		pinctrl-0 = <&pinctrl_i2c6_default>;
529		status = "disabled";
530	};
531
532	i2c6: i2c-bus@1c0 {
533		#address-cells = <1>;
534		#size-cells = <0>;
535		#interrupt-cells = <1>;
536
537		reg = <0x1c0 0x40>;
538		compatible = "aspeed,ast2500-i2c-bus";
539		clocks = <&syscon ASPEED_CLK_APB>;
540		resets = <&syscon ASPEED_RESET_I2C>;
541		bus-frequency = <100000>;
542		interrupts = <6>;
543		interrupt-parent = <&i2c_ic>;
544		pinctrl-names = "default";
545		pinctrl-0 = <&pinctrl_i2c7_default>;
546		status = "disabled";
547	};
548
549	i2c7: i2c-bus@300 {
550		#address-cells = <1>;
551		#size-cells = <0>;
552		#interrupt-cells = <1>;
553
554		reg = <0x300 0x40>;
555		compatible = "aspeed,ast2500-i2c-bus";
556		clocks = <&syscon ASPEED_CLK_APB>;
557		resets = <&syscon ASPEED_RESET_I2C>;
558		bus-frequency = <100000>;
559		interrupts = <7>;
560		interrupt-parent = <&i2c_ic>;
561		pinctrl-names = "default";
562		pinctrl-0 = <&pinctrl_i2c8_default>;
563		status = "disabled";
564	};
565
566	i2c8: i2c-bus@340 {
567		#address-cells = <1>;
568		#size-cells = <0>;
569		#interrupt-cells = <1>;
570
571		reg = <0x340 0x40>;
572		compatible = "aspeed,ast2500-i2c-bus";
573		clocks = <&syscon ASPEED_CLK_APB>;
574		resets = <&syscon ASPEED_RESET_I2C>;
575		bus-frequency = <100000>;
576		interrupts = <8>;
577		interrupt-parent = <&i2c_ic>;
578		pinctrl-names = "default";
579		pinctrl-0 = <&pinctrl_i2c9_default>;
580		status = "disabled";
581	};
582
583	i2c9: i2c-bus@380 {
584		#address-cells = <1>;
585		#size-cells = <0>;
586		#interrupt-cells = <1>;
587
588		reg = <0x380 0x40>;
589		compatible = "aspeed,ast2500-i2c-bus";
590		clocks = <&syscon ASPEED_CLK_APB>;
591		resets = <&syscon ASPEED_RESET_I2C>;
592		bus-frequency = <100000>;
593		interrupts = <9>;
594		interrupt-parent = <&i2c_ic>;
595		pinctrl-names = "default";
596		pinctrl-0 = <&pinctrl_i2c10_default>;
597		status = "disabled";
598	};
599
600	i2c10: i2c-bus@3c0 {
601		#address-cells = <1>;
602		#size-cells = <0>;
603		#interrupt-cells = <1>;
604
605		reg = <0x3c0 0x40>;
606		compatible = "aspeed,ast2500-i2c-bus";
607		clocks = <&syscon ASPEED_CLK_APB>;
608		resets = <&syscon ASPEED_RESET_I2C>;
609		bus-frequency = <100000>;
610		interrupts = <10>;
611		interrupt-parent = <&i2c_ic>;
612		pinctrl-names = "default";
613		pinctrl-0 = <&pinctrl_i2c11_default>;
614		status = "disabled";
615	};
616
617	i2c11: i2c-bus@400 {
618		#address-cells = <1>;
619		#size-cells = <0>;
620		#interrupt-cells = <1>;
621
622		reg = <0x400 0x40>;
623		compatible = "aspeed,ast2500-i2c-bus";
624		clocks = <&syscon ASPEED_CLK_APB>;
625		resets = <&syscon ASPEED_RESET_I2C>;
626		bus-frequency = <100000>;
627		interrupts = <11>;
628		interrupt-parent = <&i2c_ic>;
629		pinctrl-names = "default";
630		pinctrl-0 = <&pinctrl_i2c12_default>;
631		status = "disabled";
632	};
633
634	i2c12: i2c-bus@440 {
635		#address-cells = <1>;
636		#size-cells = <0>;
637		#interrupt-cells = <1>;
638
639		reg = <0x440 0x40>;
640		compatible = "aspeed,ast2500-i2c-bus";
641		clocks = <&syscon ASPEED_CLK_APB>;
642		resets = <&syscon ASPEED_RESET_I2C>;
643		bus-frequency = <100000>;
644		interrupts = <12>;
645		interrupt-parent = <&i2c_ic>;
646		pinctrl-names = "default";
647		pinctrl-0 = <&pinctrl_i2c13_default>;
648		status = "disabled";
649	};
650
651	i2c13: i2c-bus@480 {
652		#address-cells = <1>;
653		#size-cells = <0>;
654		#interrupt-cells = <1>;
655
656		reg = <0x480 0x40>;
657		compatible = "aspeed,ast2500-i2c-bus";
658		clocks = <&syscon ASPEED_CLK_APB>;
659		resets = <&syscon ASPEED_RESET_I2C>;
660		bus-frequency = <100000>;
661		interrupts = <13>;
662		interrupt-parent = <&i2c_ic>;
663		pinctrl-names = "default";
664		pinctrl-0 = <&pinctrl_i2c14_default>;
665		status = "disabled";
666	};
667};
668
669&pinctrl {
670	pinctrl_acpi_default: acpi_default {
671		function = "ACPI";
672		groups = "ACPI";
673	};
674
675	pinctrl_adc0_default: adc0_default {
676		function = "ADC0";
677		groups = "ADC0";
678	};
679
680	pinctrl_adc1_default: adc1_default {
681		function = "ADC1";
682		groups = "ADC1";
683	};
684
685	pinctrl_adc10_default: adc10_default {
686		function = "ADC10";
687		groups = "ADC10";
688	};
689
690	pinctrl_adc11_default: adc11_default {
691		function = "ADC11";
692		groups = "ADC11";
693	};
694
695	pinctrl_adc12_default: adc12_default {
696		function = "ADC12";
697		groups = "ADC12";
698	};
699
700	pinctrl_adc13_default: adc13_default {
701		function = "ADC13";
702		groups = "ADC13";
703	};
704
705	pinctrl_adc14_default: adc14_default {
706		function = "ADC14";
707		groups = "ADC14";
708	};
709
710	pinctrl_adc15_default: adc15_default {
711		function = "ADC15";
712		groups = "ADC15";
713	};
714
715	pinctrl_adc2_default: adc2_default {
716		function = "ADC2";
717		groups = "ADC2";
718	};
719
720	pinctrl_adc3_default: adc3_default {
721		function = "ADC3";
722		groups = "ADC3";
723	};
724
725	pinctrl_adc4_default: adc4_default {
726		function = "ADC4";
727		groups = "ADC4";
728	};
729
730	pinctrl_adc5_default: adc5_default {
731		function = "ADC5";
732		groups = "ADC5";
733	};
734
735	pinctrl_adc6_default: adc6_default {
736		function = "ADC6";
737		groups = "ADC6";
738	};
739
740	pinctrl_adc7_default: adc7_default {
741		function = "ADC7";
742		groups = "ADC7";
743	};
744
745	pinctrl_adc8_default: adc8_default {
746		function = "ADC8";
747		groups = "ADC8";
748	};
749
750	pinctrl_adc9_default: adc9_default {
751		function = "ADC9";
752		groups = "ADC9";
753	};
754
755	pinctrl_bmcint_default: bmcint_default {
756		function = "BMCINT";
757		groups = "BMCINT";
758	};
759
760	pinctrl_ddcclk_default: ddcclk_default {
761		function = "DDCCLK";
762		groups = "DDCCLK";
763	};
764
765	pinctrl_ddcdat_default: ddcdat_default {
766		function = "DDCDAT";
767		groups = "DDCDAT";
768	};
769
770	pinctrl_espi_default: espi_default {
771		function = "ESPI";
772		groups = "ESPI";
773	};
774
775	pinctrl_fwspics1_default: fwspics1_default {
776		function = "FWSPICS1";
777		groups = "FWSPICS1";
778	};
779
780	pinctrl_fwspics2_default: fwspics2_default {
781		function = "FWSPICS2";
782		groups = "FWSPICS2";
783	};
784
785	pinctrl_gpid0_default: gpid0_default {
786		function = "GPID0";
787		groups = "GPID0";
788	};
789
790	pinctrl_gpid2_default: gpid2_default {
791		function = "GPID2";
792		groups = "GPID2";
793	};
794
795	pinctrl_gpid4_default: gpid4_default {
796		function = "GPID4";
797		groups = "GPID4";
798	};
799
800	pinctrl_gpid6_default: gpid6_default {
801		function = "GPID6";
802		groups = "GPID6";
803	};
804
805	pinctrl_gpie0_default: gpie0_default {
806		function = "GPIE0";
807		groups = "GPIE0";
808	};
809
810	pinctrl_gpie2_default: gpie2_default {
811		function = "GPIE2";
812		groups = "GPIE2";
813	};
814
815	pinctrl_gpie4_default: gpie4_default {
816		function = "GPIE4";
817		groups = "GPIE4";
818	};
819
820	pinctrl_gpie6_default: gpie6_default {
821		function = "GPIE6";
822		groups = "GPIE6";
823	};
824
825	pinctrl_i2c10_default: i2c10_default {
826		function = "I2C10";
827		groups = "I2C10";
828	};
829
830	pinctrl_i2c11_default: i2c11_default {
831		function = "I2C11";
832		groups = "I2C11";
833	};
834
835	pinctrl_i2c12_default: i2c12_default {
836		function = "I2C12";
837		groups = "I2C12";
838	};
839
840	pinctrl_i2c13_default: i2c13_default {
841		function = "I2C13";
842		groups = "I2C13";
843	};
844
845	pinctrl_i2c14_default: i2c14_default {
846		function = "I2C14";
847		groups = "I2C14";
848	};
849
850	pinctrl_i2c3_default: i2c3_default {
851		function = "I2C3";
852		groups = "I2C3";
853	};
854
855	pinctrl_i2c4_default: i2c4_default {
856		function = "I2C4";
857		groups = "I2C4";
858	};
859
860	pinctrl_i2c5_default: i2c5_default {
861		function = "I2C5";
862		groups = "I2C5";
863	};
864
865	pinctrl_i2c6_default: i2c6_default {
866		function = "I2C6";
867		groups = "I2C6";
868	};
869
870	pinctrl_i2c7_default: i2c7_default {
871		function = "I2C7";
872		groups = "I2C7";
873	};
874
875	pinctrl_i2c8_default: i2c8_default {
876		function = "I2C8";
877		groups = "I2C8";
878	};
879
880	pinctrl_i2c9_default: i2c9_default {
881		function = "I2C9";
882		groups = "I2C9";
883	};
884
885	pinctrl_lad0_default: lad0_default {
886		function = "LAD0";
887		groups = "LAD0";
888	};
889
890	pinctrl_lad1_default: lad1_default {
891		function = "LAD1";
892		groups = "LAD1";
893	};
894
895	pinctrl_lad2_default: lad2_default {
896		function = "LAD2";
897		groups = "LAD2";
898	};
899
900	pinctrl_lad3_default: lad3_default {
901		function = "LAD3";
902		groups = "LAD3";
903	};
904
905	pinctrl_lclk_default: lclk_default {
906		function = "LCLK";
907		groups = "LCLK";
908	};
909
910	pinctrl_lframe_default: lframe_default {
911		function = "LFRAME";
912		groups = "LFRAME";
913	};
914
915	pinctrl_lpchc_default: lpchc_default {
916		function = "LPCHC";
917		groups = "LPCHC";
918	};
919
920	pinctrl_lpcpd_default: lpcpd_default {
921		function = "LPCPD";
922		groups = "LPCPD";
923	};
924
925	pinctrl_lpcplus_default: lpcplus_default {
926		function = "LPCPLUS";
927		groups = "LPCPLUS";
928	};
929
930	pinctrl_lpcpme_default: lpcpme_default {
931		function = "LPCPME";
932		groups = "LPCPME";
933	};
934
935	pinctrl_lpcrst_default: lpcrst_default {
936		function = "LPCRST";
937		groups = "LPCRST";
938	};
939
940	pinctrl_lpcsmi_default: lpcsmi_default {
941		function = "LPCSMI";
942		groups = "LPCSMI";
943	};
944
945	pinctrl_lsirq_default: lsirq_default {
946		function = "LSIRQ";
947		groups = "LSIRQ";
948	};
949
950	pinctrl_mac1link_default: mac1link_default {
951		function = "MAC1LINK";
952		groups = "MAC1LINK";
953	};
954
955	pinctrl_mac2link_default: mac2link_default {
956		function = "MAC2LINK";
957		groups = "MAC2LINK";
958	};
959
960	pinctrl_mdio1_default: mdio1_default {
961		function = "MDIO1";
962		groups = "MDIO1";
963	};
964
965	pinctrl_mdio2_default: mdio2_default {
966		function = "MDIO2";
967		groups = "MDIO2";
968	};
969
970	pinctrl_ncts1_default: ncts1_default {
971		function = "NCTS1";
972		groups = "NCTS1";
973	};
974
975	pinctrl_ncts2_default: ncts2_default {
976		function = "NCTS2";
977		groups = "NCTS2";
978	};
979
980	pinctrl_ncts3_default: ncts3_default {
981		function = "NCTS3";
982		groups = "NCTS3";
983	};
984
985	pinctrl_ncts4_default: ncts4_default {
986		function = "NCTS4";
987		groups = "NCTS4";
988	};
989
990	pinctrl_ndcd1_default: ndcd1_default {
991		function = "NDCD1";
992		groups = "NDCD1";
993	};
994
995	pinctrl_ndcd2_default: ndcd2_default {
996		function = "NDCD2";
997		groups = "NDCD2";
998	};
999
1000	pinctrl_ndcd3_default: ndcd3_default {
1001		function = "NDCD3";
1002		groups = "NDCD3";
1003	};
1004
1005	pinctrl_ndcd4_default: ndcd4_default {
1006		function = "NDCD4";
1007		groups = "NDCD4";
1008	};
1009
1010	pinctrl_ndsr1_default: ndsr1_default {
1011		function = "NDSR1";
1012		groups = "NDSR1";
1013	};
1014
1015	pinctrl_ndsr2_default: ndsr2_default {
1016		function = "NDSR2";
1017		groups = "NDSR2";
1018	};
1019
1020	pinctrl_ndsr3_default: ndsr3_default {
1021		function = "NDSR3";
1022		groups = "NDSR3";
1023	};
1024
1025	pinctrl_ndsr4_default: ndsr4_default {
1026		function = "NDSR4";
1027		groups = "NDSR4";
1028	};
1029
1030	pinctrl_ndtr1_default: ndtr1_default {
1031		function = "NDTR1";
1032		groups = "NDTR1";
1033	};
1034
1035	pinctrl_ndtr2_default: ndtr2_default {
1036		function = "NDTR2";
1037		groups = "NDTR2";
1038	};
1039
1040	pinctrl_ndtr3_default: ndtr3_default {
1041		function = "NDTR3";
1042		groups = "NDTR3";
1043	};
1044
1045	pinctrl_ndtr4_default: ndtr4_default {
1046		function = "NDTR4";
1047		groups = "NDTR4";
1048	};
1049
1050	pinctrl_nri1_default: nri1_default {
1051		function = "NRI1";
1052		groups = "NRI1";
1053	};
1054
1055	pinctrl_nri2_default: nri2_default {
1056		function = "NRI2";
1057		groups = "NRI2";
1058	};
1059
1060	pinctrl_nri3_default: nri3_default {
1061		function = "NRI3";
1062		groups = "NRI3";
1063	};
1064
1065	pinctrl_nri4_default: nri4_default {
1066		function = "NRI4";
1067		groups = "NRI4";
1068	};
1069
1070	pinctrl_nrts1_default: nrts1_default {
1071		function = "NRTS1";
1072		groups = "NRTS1";
1073	};
1074
1075	pinctrl_nrts2_default: nrts2_default {
1076		function = "NRTS2";
1077		groups = "NRTS2";
1078	};
1079
1080	pinctrl_nrts3_default: nrts3_default {
1081		function = "NRTS3";
1082		groups = "NRTS3";
1083	};
1084
1085	pinctrl_nrts4_default: nrts4_default {
1086		function = "NRTS4";
1087		groups = "NRTS4";
1088	};
1089
1090	pinctrl_oscclk_default: oscclk_default {
1091		function = "OSCCLK";
1092		groups = "OSCCLK";
1093	};
1094
1095	pinctrl_pewake_default: pewake_default {
1096		function = "PEWAKE";
1097		groups = "PEWAKE";
1098	};
1099
1100	pinctrl_pnor_default: pnor_default {
1101		function = "PNOR";
1102		groups = "PNOR";
1103	};
1104
1105	pinctrl_pwm0_default: pwm0_default {
1106		function = "PWM0";
1107		groups = "PWM0";
1108	};
1109
1110	pinctrl_pwm1_default: pwm1_default {
1111		function = "PWM1";
1112		groups = "PWM1";
1113	};
1114
1115	pinctrl_pwm2_default: pwm2_default {
1116		function = "PWM2";
1117		groups = "PWM2";
1118	};
1119
1120	pinctrl_pwm3_default: pwm3_default {
1121		function = "PWM3";
1122		groups = "PWM3";
1123	};
1124
1125	pinctrl_pwm4_default: pwm4_default {
1126		function = "PWM4";
1127		groups = "PWM4";
1128	};
1129
1130	pinctrl_pwm5_default: pwm5_default {
1131		function = "PWM5";
1132		groups = "PWM5";
1133	};
1134
1135	pinctrl_pwm6_default: pwm6_default {
1136		function = "PWM6";
1137		groups = "PWM6";
1138	};
1139
1140	pinctrl_pwm7_default: pwm7_default {
1141		function = "PWM7";
1142		groups = "PWM7";
1143	};
1144
1145	pinctrl_rgmii1_default: rgmii1_default {
1146		function = "RGMII1";
1147		groups = "RGMII1";
1148	};
1149
1150	pinctrl_rgmii2_default: rgmii2_default {
1151		function = "RGMII2";
1152		groups = "RGMII2";
1153	};
1154
1155	pinctrl_rmii1_default: rmii1_default {
1156		function = "RMII1";
1157		groups = "RMII1";
1158	};
1159
1160	pinctrl_rmii2_default: rmii2_default {
1161		function = "RMII2";
1162		groups = "RMII2";
1163	};
1164
1165	pinctrl_rxd1_default: rxd1_default {
1166		function = "RXD1";
1167		groups = "RXD1";
1168	};
1169
1170	pinctrl_rxd2_default: rxd2_default {
1171		function = "RXD2";
1172		groups = "RXD2";
1173	};
1174
1175	pinctrl_rxd3_default: rxd3_default {
1176		function = "RXD3";
1177		groups = "RXD3";
1178	};
1179
1180	pinctrl_rxd4_default: rxd4_default {
1181		function = "RXD4";
1182		groups = "RXD4";
1183	};
1184
1185	pinctrl_salt1_default: salt1_default {
1186		function = "SALT1";
1187		groups = "SALT1";
1188	};
1189
1190	pinctrl_salt10_default: salt10_default {
1191		function = "SALT10";
1192		groups = "SALT10";
1193	};
1194
1195	pinctrl_salt11_default: salt11_default {
1196		function = "SALT11";
1197		groups = "SALT11";
1198	};
1199
1200	pinctrl_salt12_default: salt12_default {
1201		function = "SALT12";
1202		groups = "SALT12";
1203	};
1204
1205	pinctrl_salt13_default: salt13_default {
1206		function = "SALT13";
1207		groups = "SALT13";
1208	};
1209
1210	pinctrl_salt14_default: salt14_default {
1211		function = "SALT14";
1212		groups = "SALT14";
1213	};
1214
1215	pinctrl_salt2_default: salt2_default {
1216		function = "SALT2";
1217		groups = "SALT2";
1218	};
1219
1220	pinctrl_salt3_default: salt3_default {
1221		function = "SALT3";
1222		groups = "SALT3";
1223	};
1224
1225	pinctrl_salt4_default: salt4_default {
1226		function = "SALT4";
1227		groups = "SALT4";
1228	};
1229
1230	pinctrl_salt5_default: salt5_default {
1231		function = "SALT5";
1232		groups = "SALT5";
1233	};
1234
1235	pinctrl_salt6_default: salt6_default {
1236		function = "SALT6";
1237		groups = "SALT6";
1238	};
1239
1240	pinctrl_salt7_default: salt7_default {
1241		function = "SALT7";
1242		groups = "SALT7";
1243	};
1244
1245	pinctrl_salt8_default: salt8_default {
1246		function = "SALT8";
1247		groups = "SALT8";
1248	};
1249
1250	pinctrl_salt9_default: salt9_default {
1251		function = "SALT9";
1252		groups = "SALT9";
1253	};
1254
1255	pinctrl_scl1_default: scl1_default {
1256		function = "SCL1";
1257		groups = "SCL1";
1258	};
1259
1260	pinctrl_scl2_default: scl2_default {
1261		function = "SCL2";
1262		groups = "SCL2";
1263	};
1264
1265	pinctrl_sd1_default: sd1_default {
1266		function = "SD1";
1267		groups = "SD1";
1268	};
1269
1270	pinctrl_sd2_default: sd2_default {
1271		function = "SD2";
1272		groups = "SD2";
1273	};
1274
1275	pinctrl_sda1_default: sda1_default {
1276		function = "SDA1";
1277		groups = "SDA1";
1278	};
1279
1280	pinctrl_sda2_default: sda2_default {
1281		function = "SDA2";
1282		groups = "SDA2";
1283	};
1284
1285	pinctrl_sgps1_default: sgps1_default {
1286		function = "SGPS1";
1287		groups = "SGPS1";
1288	};
1289
1290	pinctrl_sgps2_default: sgps2_default {
1291		function = "SGPS2";
1292		groups = "SGPS2";
1293	};
1294
1295	pinctrl_sioonctrl_default: sioonctrl_default {
1296		function = "SIOONCTRL";
1297		groups = "SIOONCTRL";
1298	};
1299
1300	pinctrl_siopbi_default: siopbi_default {
1301		function = "SIOPBI";
1302		groups = "SIOPBI";
1303	};
1304
1305	pinctrl_siopbo_default: siopbo_default {
1306		function = "SIOPBO";
1307		groups = "SIOPBO";
1308	};
1309
1310	pinctrl_siopwreq_default: siopwreq_default {
1311		function = "SIOPWREQ";
1312		groups = "SIOPWREQ";
1313	};
1314
1315	pinctrl_siopwrgd_default: siopwrgd_default {
1316		function = "SIOPWRGD";
1317		groups = "SIOPWRGD";
1318	};
1319
1320	pinctrl_sios3_default: sios3_default {
1321		function = "SIOS3";
1322		groups = "SIOS3";
1323	};
1324
1325	pinctrl_sios5_default: sios5_default {
1326		function = "SIOS5";
1327		groups = "SIOS5";
1328	};
1329
1330	pinctrl_siosci_default: siosci_default {
1331		function = "SIOSCI";
1332		groups = "SIOSCI";
1333	};
1334
1335	pinctrl_spi1_default: spi1_default {
1336		function = "SPI1";
1337		groups = "SPI1";
1338	};
1339
1340	pinctrl_spi1cs1_default: spi1cs1_default {
1341		function = "SPI1CS1";
1342		groups = "SPI1CS1";
1343	};
1344
1345	pinctrl_spi1debug_default: spi1debug_default {
1346		function = "SPI1DEBUG";
1347		groups = "SPI1DEBUG";
1348	};
1349
1350	pinctrl_spi1passthru_default: spi1passthru_default {
1351		function = "SPI1PASSTHRU";
1352		groups = "SPI1PASSTHRU";
1353	};
1354
1355	pinctrl_spi2ck_default: spi2ck_default {
1356		function = "SPI2CK";
1357		groups = "SPI2CK";
1358	};
1359
1360	pinctrl_spi2cs0_default: spi2cs0_default {
1361		function = "SPI2CS0";
1362		groups = "SPI2CS0";
1363	};
1364
1365	pinctrl_spi2cs1_default: spi2cs1_default {
1366		function = "SPI2CS1";
1367		groups = "SPI2CS1";
1368	};
1369
1370	pinctrl_spi2miso_default: spi2miso_default {
1371		function = "SPI2MISO";
1372		groups = "SPI2MISO";
1373	};
1374
1375	pinctrl_spi2mosi_default: spi2mosi_default {
1376		function = "SPI2MOSI";
1377		groups = "SPI2MOSI";
1378	};
1379
1380	pinctrl_timer3_default: timer3_default {
1381		function = "TIMER3";
1382		groups = "TIMER3";
1383	};
1384
1385	pinctrl_timer4_default: timer4_default {
1386		function = "TIMER4";
1387		groups = "TIMER4";
1388	};
1389
1390	pinctrl_timer5_default: timer5_default {
1391		function = "TIMER5";
1392		groups = "TIMER5";
1393	};
1394
1395	pinctrl_timer6_default: timer6_default {
1396		function = "TIMER6";
1397		groups = "TIMER6";
1398	};
1399
1400	pinctrl_timer7_default: timer7_default {
1401		function = "TIMER7";
1402		groups = "TIMER7";
1403	};
1404
1405	pinctrl_timer8_default: timer8_default {
1406		function = "TIMER8";
1407		groups = "TIMER8";
1408	};
1409
1410	pinctrl_txd1_default: txd1_default {
1411		function = "TXD1";
1412		groups = "TXD1";
1413	};
1414
1415	pinctrl_txd2_default: txd2_default {
1416		function = "TXD2";
1417		groups = "TXD2";
1418	};
1419
1420	pinctrl_txd3_default: txd3_default {
1421		function = "TXD3";
1422		groups = "TXD3";
1423	};
1424
1425	pinctrl_txd4_default: txd4_default {
1426		function = "TXD4";
1427		groups = "TXD4";
1428	};
1429
1430	pinctrl_uart6_default: uart6_default {
1431		function = "UART6";
1432		groups = "UART6";
1433	};
1434
1435	pinctrl_usbcki_default: usbcki_default {
1436		function = "USBCKI";
1437		groups = "USBCKI";
1438	};
1439
1440	pinctrl_usb2ah_default: usb2ah_default {
1441		function = "USB2AH";
1442		groups = "USB2AH";
1443	};
1444
1445	pinctrl_usb2ad_default: usb2ad_default {
1446		function = "USB2AD";
1447		groups = "USB2AD";
1448	};
1449
1450	pinctrl_usb11bhid_default: usb11bhid_default {
1451		function = "USB11BHID";
1452		groups = "USB11BHID";
1453	};
1454
1455	pinctrl_usb2bh_default: usb2bh_default {
1456		function = "USB2BH";
1457		groups = "USB2BH";
1458	};
1459
1460	pinctrl_vgabiosrom_default: vgabiosrom_default {
1461		function = "VGABIOSROM";
1462		groups = "VGABIOSROM";
1463	};
1464
1465	pinctrl_vgahs_default: vgahs_default {
1466		function = "VGAHS";
1467		groups = "VGAHS";
1468	};
1469
1470	pinctrl_vgavs_default: vgavs_default {
1471		function = "VGAVS";
1472		groups = "VGAVS";
1473	};
1474
1475	pinctrl_vpi24_default: vpi24_default {
1476		function = "VPI24";
1477		groups = "VPI24";
1478	};
1479
1480	pinctrl_vpo_default: vpo_default {
1481		function = "VPO";
1482		groups = "VPO";
1483	};
1484
1485	pinctrl_wdtrst1_default: wdtrst1_default {
1486		function = "WDTRST1";
1487		groups = "WDTRST1";
1488	};
1489
1490	pinctrl_wdtrst2_default: wdtrst2_default {
1491		function = "WDTRST2";
1492		groups = "WDTRST2";
1493	};
1494};
1495