1// SPDX-License-Identifier: GPL-2.0+
2#include <dt-bindings/clock/aspeed-clock.h>
3
4/ {
5	model = "Aspeed BMC";
6	compatible = "aspeed,ast2400";
7	#address-cells = <1>;
8	#size-cells = <1>;
9	interrupt-parent = <&vic>;
10
11	aliases {
12		i2c0 = &i2c0;
13		i2c1 = &i2c1;
14		i2c2 = &i2c2;
15		i2c3 = &i2c3;
16		i2c4 = &i2c4;
17		i2c5 = &i2c5;
18		i2c6 = &i2c6;
19		i2c7 = &i2c7;
20		i2c8 = &i2c8;
21		i2c9 = &i2c9;
22		i2c10 = &i2c10;
23		i2c11 = &i2c11;
24		i2c12 = &i2c12;
25		i2c13 = &i2c13;
26		serial0 = &uart1;
27		serial1 = &uart2;
28		serial2 = &uart3;
29		serial3 = &uart4;
30		serial4 = &uart5;
31		serial5 = &vuart;
32	};
33
34	cpus {
35		#address-cells = <1>;
36		#size-cells = <0>;
37
38		cpu@0 {
39			compatible = "arm,arm926ej-s";
40			device_type = "cpu";
41			reg = <0>;
42		};
43	};
44
45	memory@40000000 {
46		device_type = "memory";
47		reg = <0x40000000 0>;
48	};
49
50	ahb {
51		compatible = "simple-bus";
52		#address-cells = <1>;
53		#size-cells = <1>;
54		ranges;
55
56		fmc: spi@1e620000 {
57			reg = < 0x1e620000 0x94
58				0x20000000 0x10000000 >;
59			#address-cells = <1>;
60			#size-cells = <0>;
61			compatible = "aspeed,ast2400-fmc";
62			clocks = <&syscon ASPEED_CLK_AHB>;
63			status = "disabled";
64			interrupts = <19>;
65			flash@0 {
66				reg = < 0 >;
67				compatible = "jedec,spi-nor";
68				spi-max-frequency = <50000000>;
69				status = "disabled";
70			};
71			flash@1 {
72				reg = < 1 >;
73				compatible = "jedec,spi-nor";
74				status = "disabled";
75			};
76			flash@2 {
77				reg = < 2 >;
78				compatible = "jedec,spi-nor";
79				status = "disabled";
80			};
81			flash@3 {
82				reg = < 3 >;
83				compatible = "jedec,spi-nor";
84				status = "disabled";
85			};
86			flash@4 {
87				reg = < 4 >;
88				compatible = "jedec,spi-nor";
89				status = "disabled";
90			};
91		};
92
93		spi: spi@1e630000 {
94			reg = < 0x1e630000 0x18
95				0x30000000 0x10000000 >;
96			#address-cells = <1>;
97			#size-cells = <0>;
98			compatible = "aspeed,ast2400-spi";
99			clocks = <&syscon ASPEED_CLK_AHB>;
100			status = "disabled";
101			flash@0 {
102				reg = < 0 >;
103				compatible = "jedec,spi-nor";
104				spi-max-frequency = <50000000>;
105				status = "disabled";
106			};
107		};
108
109		vic: interrupt-controller@1e6c0080 {
110			compatible = "aspeed,ast2400-vic";
111			interrupt-controller;
112			#interrupt-cells = <1>;
113			valid-sources = <0xffffffff 0x0007ffff>;
114			reg = <0x1e6c0080 0x80>;
115		};
116
117		cvic: copro-interrupt-controller@1e6c2000 {
118			compatible = "aspeed,ast2400-cvic", "aspeed-cvic";
119			valid-sources = <0x7fffffff>;
120			reg = <0x1e6c2000 0x80>;
121		};
122
123		mac0: ethernet@1e660000 {
124			compatible = "aspeed,ast2400-mac", "faraday,ftgmac100";
125			reg = <0x1e660000 0x180>;
126			interrupts = <2>;
127			clocks = <&syscon ASPEED_CLK_GATE_MAC1CLK>;
128			status = "disabled";
129		};
130
131		mac1: ethernet@1e680000 {
132			compatible = "aspeed,ast2400-mac", "faraday,ftgmac100";
133			reg = <0x1e680000 0x180>;
134			interrupts = <3>;
135			clocks = <&syscon ASPEED_CLK_GATE_MAC2CLK>;
136			status = "disabled";
137		};
138
139		ehci0: usb@1e6a1000 {
140			compatible = "aspeed,ast2400-ehci", "generic-ehci";
141			reg = <0x1e6a1000 0x100>;
142			interrupts = <5>;
143			clocks = <&syscon ASPEED_CLK_GATE_USBPORT1CLK>;
144			pinctrl-names = "default";
145			pinctrl-0 = <&pinctrl_usb2h_default>;
146			status = "disabled";
147		};
148
149		uhci: usb@1e6b0000 {
150			compatible = "aspeed,ast2400-uhci", "generic-uhci";
151			reg = <0x1e6b0000 0x100>;
152			interrupts = <14>;
153			#ports = <3>;
154			clocks = <&syscon ASPEED_CLK_GATE_USBUHCICLK>;
155			status = "disabled";
156			/*
157			 * No default pinmux, it will follow EHCI, use an explicit pinmux
158			 * override if you don't enable EHCI
159			 */
160		};
161
162		vhub: usb-vhub@1e6a0000 {
163			compatible = "aspeed,ast2400-usb-vhub";
164			reg = <0x1e6a0000 0x300>;
165			interrupts = <5>;
166			clocks = <&syscon ASPEED_CLK_GATE_USBPORT1CLK>;
167			aspeed,vhub-downstream-ports = <5>;
168			aspeed,vhub-generic-endpoints = <15>;
169			pinctrl-names = "default";
170			pinctrl-0 = <&pinctrl_usb2d_default>;
171			status = "disabled";
172		};
173
174		apb {
175			compatible = "simple-bus";
176			#address-cells = <1>;
177			#size-cells = <1>;
178			ranges;
179
180			syscon: syscon@1e6e2000 {
181				compatible = "aspeed,ast2400-scu", "syscon", "simple-mfd";
182				reg = <0x1e6e2000 0x1a8>;
183				#address-cells = <1>;
184				#size-cells = <1>;
185				ranges = <0 0x1e6e2000 0x1000>;
186				#clock-cells = <1>;
187				#reset-cells = <1>;
188
189				p2a: p2a-control@2c {
190					reg = <0x2c 0x4>;
191					compatible = "aspeed,ast2400-p2a-ctrl";
192					status = "disabled";
193				};
194
195				pinctrl: pinctrl@80 {
196					reg = <0x80 0x18>, <0xa0 0x10>;
197					compatible = "aspeed,ast2400-pinctrl";
198				};
199			};
200
201			rng: hwrng@1e6e2078 {
202				compatible = "timeriomem_rng";
203				reg = <0x1e6e2078 0x4>;
204				period = <1>;
205				quality = <100>;
206			};
207
208			adc: adc@1e6e9000 {
209				compatible = "aspeed,ast2400-adc";
210				reg = <0x1e6e9000 0xb0>;
211				clocks = <&syscon ASPEED_CLK_APB>;
212				resets = <&syscon ASPEED_RESET_ADC>;
213				#io-channel-cells = <1>;
214				status = "disabled";
215			};
216
217			sram: sram@1e720000 {
218				compatible = "mmio-sram";
219				reg = <0x1e720000 0x8000>;	// 32K
220			};
221
222			video: video@1e700000 {
223				compatible = "aspeed,ast2400-video-engine";
224				reg = <0x1e700000 0x1000>;
225				clocks = <&syscon ASPEED_CLK_GATE_VCLK>,
226					 <&syscon ASPEED_CLK_GATE_ECLK>;
227				clock-names = "vclk", "eclk";
228				interrupts = <7>;
229				status = "disabled";
230			};
231
232			sdmmc: sd-controller@1e740000 {
233				compatible = "aspeed,ast2400-sd-controller";
234				reg = <0x1e740000 0x100>;
235				#address-cells = <1>;
236				#size-cells = <1>;
237				ranges = <0 0x1e740000 0x10000>;
238				clocks = <&syscon ASPEED_CLK_GATE_SDCLK>;
239				status = "disabled";
240
241				sdhci0: sdhci@100 {
242					compatible = "aspeed,ast2400-sdhci";
243					reg = <0x100 0x100>;
244					interrupts = <26>;
245					sdhci,auto-cmd12;
246					clocks = <&syscon ASPEED_CLK_SDIO>;
247					status = "disabled";
248				};
249
250				sdhci1: sdhci@200 {
251					compatible = "aspeed,ast2400-sdhci";
252					reg = <0x200 0x100>;
253					interrupts = <26>;
254					sdhci,auto-cmd12;
255					clocks = <&syscon ASPEED_CLK_SDIO>;
256					status = "disabled";
257				};
258			};
259
260			gpio: gpio@1e780000 {
261				#gpio-cells = <2>;
262				gpio-controller;
263				compatible = "aspeed,ast2400-gpio";
264				reg = <0x1e780000 0x1000>;
265				interrupts = <20>;
266				gpio-ranges = <&pinctrl 0 0 220>;
267				clocks = <&syscon ASPEED_CLK_APB>;
268				interrupt-controller;
269				#interrupt-cells = <2>;
270			};
271
272			timer: timer@1e782000 {
273				/* This timer is a Faraday FTTMR010 derivative */
274				compatible = "aspeed,ast2400-timer";
275				reg = <0x1e782000 0x90>;
276				interrupts = <16 17 18 35 36 37 38 39>;
277				clocks = <&syscon ASPEED_CLK_APB>;
278				clock-names = "PCLK";
279			};
280
281			rtc: rtc@1e781000 {
282				compatible = "aspeed,ast2400-rtc";
283				reg = <0x1e781000 0x18>;
284				status = "disabled";
285			};
286
287			uart1: serial@1e783000 {
288				compatible = "ns16550a";
289				reg = <0x1e783000 0x20>;
290				reg-shift = <2>;
291				interrupts = <9>;
292				clocks = <&syscon ASPEED_CLK_GATE_UART1CLK>;
293				resets = <&lpc_reset 4>;
294				no-loopback-test;
295				status = "disabled";
296			};
297
298			uart5: serial@1e784000 {
299				compatible = "ns16550a";
300				reg = <0x1e784000 0x20>;
301				reg-shift = <2>;
302				interrupts = <10>;
303				clocks = <&syscon ASPEED_CLK_GATE_UART5CLK>;
304				no-loopback-test;
305				status = "disabled";
306			};
307
308			wdt1: watchdog@1e785000 {
309				compatible = "aspeed,ast2400-wdt";
310				reg = <0x1e785000 0x1c>;
311				clocks = <&syscon ASPEED_CLK_APB>;
312			};
313
314			wdt2: watchdog@1e785020 {
315				compatible = "aspeed,ast2400-wdt";
316				reg = <0x1e785020 0x1c>;
317				clocks = <&syscon ASPEED_CLK_APB>;
318			};
319
320			pwm_tacho: pwm-tacho-controller@1e786000 {
321				compatible = "aspeed,ast2400-pwm-tacho";
322				#address-cells = <1>;
323				#size-cells = <0>;
324				reg = <0x1e786000 0x1000>;
325				clocks = <&syscon ASPEED_CLK_24M>;
326				resets = <&syscon ASPEED_RESET_PWM>;
327				status = "disabled";
328			};
329
330			vuart: serial@1e787000 {
331				compatible = "aspeed,ast2400-vuart";
332				reg = <0x1e787000 0x40>;
333				reg-shift = <2>;
334				interrupts = <8>;
335				clocks = <&syscon ASPEED_CLK_APB>;
336				no-loopback-test;
337				status = "disabled";
338			};
339
340			lpc: lpc@1e789000 {
341				compatible = "aspeed,ast2400-lpc", "simple-mfd";
342				reg = <0x1e789000 0x1000>;
343
344				#address-cells = <1>;
345				#size-cells = <1>;
346				ranges = <0x0 0x1e789000 0x1000>;
347
348				lpc_bmc: lpc-bmc@0 {
349					compatible = "aspeed,ast2400-lpc-bmc";
350					reg = <0x0 0x80>;
351				};
352
353				lpc_host: lpc-host@80 {
354					compatible = "aspeed,ast2400-lpc-host", "simple-mfd", "syscon";
355					reg = <0x80 0x1e0>;
356					reg-io-width = <4>;
357
358					#address-cells = <1>;
359					#size-cells = <1>;
360					ranges = <0x0 0x80 0x1e0>;
361
362					lpc_ctrl: lpc-ctrl@0 {
363						compatible = "aspeed,ast2400-lpc-ctrl";
364						reg = <0x0 0x10>;
365						clocks = <&syscon ASPEED_CLK_GATE_LCLK>;
366						status = "disabled";
367					};
368
369					lpc_snoop: lpc-snoop@10 {
370						compatible = "aspeed,ast2400-lpc-snoop";
371						reg = <0x10 0x8>;
372						interrupts = <8>;
373						status = "disabled";
374					};
375
376					lhc: lhc@20 {
377						compatible = "aspeed,ast2400-lhc";
378						reg = <0x20 0x24 0x48 0x8>;
379					};
380
381					lpc_reset: reset-controller@18 {
382						compatible = "aspeed,ast2400-lpc-reset";
383						reg = <0x18 0x4>;
384						#reset-cells = <1>;
385					};
386
387					ibt: ibt@c0  {
388						compatible = "aspeed,ast2400-ibt-bmc";
389						reg = <0xc0 0x18>;
390						interrupts = <8>;
391						status = "disabled";
392					};
393				};
394			};
395
396			uart2: serial@1e78d000 {
397				compatible = "ns16550a";
398				reg = <0x1e78d000 0x20>;
399				reg-shift = <2>;
400				interrupts = <32>;
401				clocks = <&syscon ASPEED_CLK_GATE_UART2CLK>;
402				resets = <&lpc_reset 5>;
403				no-loopback-test;
404				status = "disabled";
405			};
406
407			uart3: serial@1e78e000 {
408				compatible = "ns16550a";
409				reg = <0x1e78e000 0x20>;
410				reg-shift = <2>;
411				interrupts = <33>;
412				clocks = <&syscon ASPEED_CLK_GATE_UART3CLK>;
413				resets = <&lpc_reset 6>;
414				no-loopback-test;
415				status = "disabled";
416			};
417
418			uart4: serial@1e78f000 {
419				compatible = "ns16550a";
420				reg = <0x1e78f000 0x20>;
421				reg-shift = <2>;
422				interrupts = <34>;
423				clocks = <&syscon ASPEED_CLK_GATE_UART4CLK>;
424				resets = <&lpc_reset 7>;
425				no-loopback-test;
426				status = "disabled";
427			};
428
429			i2c: bus@1e78a000 {
430				compatible = "simple-bus";
431				#address-cells = <1>;
432				#size-cells = <1>;
433				ranges = <0 0x1e78a000 0x1000>;
434			};
435		};
436	};
437};
438
439&i2c {
440	i2c_ic: interrupt-controller@0 {
441		#interrupt-cells = <1>;
442		compatible = "aspeed,ast2400-i2c-ic";
443		reg = <0x0 0x40>;
444		interrupts = <12>;
445		interrupt-controller;
446	};
447
448	i2c0: i2c-bus@40 {
449		#address-cells = <1>;
450		#size-cells = <0>;
451		#interrupt-cells = <1>;
452
453		reg = <0x40 0x40>;
454		compatible = "aspeed,ast2400-i2c-bus";
455		clocks = <&syscon ASPEED_CLK_APB>;
456		resets = <&syscon ASPEED_RESET_I2C>;
457		bus-frequency = <100000>;
458		interrupts = <0>;
459		interrupt-parent = <&i2c_ic>;
460		status = "disabled";
461		/* Does not need pinctrl properties */
462	};
463
464	i2c1: i2c-bus@80 {
465		#address-cells = <1>;
466		#size-cells = <0>;
467		#interrupt-cells = <1>;
468
469		reg = <0x80 0x40>;
470		compatible = "aspeed,ast2400-i2c-bus";
471		clocks = <&syscon ASPEED_CLK_APB>;
472		resets = <&syscon ASPEED_RESET_I2C>;
473		bus-frequency = <100000>;
474		interrupts = <1>;
475		interrupt-parent = <&i2c_ic>;
476		status = "disabled";
477		/* Does not need pinctrl properties */
478	};
479
480	i2c2: i2c-bus@c0 {
481		#address-cells = <1>;
482		#size-cells = <0>;
483		#interrupt-cells = <1>;
484
485		reg = <0xc0 0x40>;
486		compatible = "aspeed,ast2400-i2c-bus";
487		clocks = <&syscon ASPEED_CLK_APB>;
488		resets = <&syscon ASPEED_RESET_I2C>;
489		bus-frequency = <100000>;
490		interrupts = <2>;
491		interrupt-parent = <&i2c_ic>;
492		pinctrl-names = "default";
493		pinctrl-0 = <&pinctrl_i2c3_default>;
494		status = "disabled";
495	};
496
497	i2c3: i2c-bus@100 {
498		#address-cells = <1>;
499		#size-cells = <0>;
500		#interrupt-cells = <1>;
501
502		reg = <0x100 0x40>;
503		compatible = "aspeed,ast2400-i2c-bus";
504		clocks = <&syscon ASPEED_CLK_APB>;
505		resets = <&syscon ASPEED_RESET_I2C>;
506		bus-frequency = <100000>;
507		interrupts = <3>;
508		interrupt-parent = <&i2c_ic>;
509		pinctrl-names = "default";
510		pinctrl-0 = <&pinctrl_i2c4_default>;
511		status = "disabled";
512	};
513
514	i2c4: i2c-bus@140 {
515		#address-cells = <1>;
516		#size-cells = <0>;
517		#interrupt-cells = <1>;
518
519		reg = <0x140 0x40>;
520		compatible = "aspeed,ast2400-i2c-bus";
521		clocks = <&syscon ASPEED_CLK_APB>;
522		resets = <&syscon ASPEED_RESET_I2C>;
523		bus-frequency = <100000>;
524		interrupts = <4>;
525		interrupt-parent = <&i2c_ic>;
526		pinctrl-names = "default";
527		pinctrl-0 = <&pinctrl_i2c5_default>;
528		status = "disabled";
529	};
530
531	i2c5: i2c-bus@180 {
532		#address-cells = <1>;
533		#size-cells = <0>;
534		#interrupt-cells = <1>;
535
536		reg = <0x180 0x40>;
537		compatible = "aspeed,ast2400-i2c-bus";
538		clocks = <&syscon ASPEED_CLK_APB>;
539		resets = <&syscon ASPEED_RESET_I2C>;
540		bus-frequency = <100000>;
541		interrupts = <5>;
542		interrupt-parent = <&i2c_ic>;
543		pinctrl-names = "default";
544		pinctrl-0 = <&pinctrl_i2c6_default>;
545		status = "disabled";
546	};
547
548	i2c6: i2c-bus@1c0 {
549		#address-cells = <1>;
550		#size-cells = <0>;
551		#interrupt-cells = <1>;
552
553		reg = <0x1c0 0x40>;
554		compatible = "aspeed,ast2400-i2c-bus";
555		clocks = <&syscon ASPEED_CLK_APB>;
556		resets = <&syscon ASPEED_RESET_I2C>;
557		bus-frequency = <100000>;
558		interrupts = <6>;
559		interrupt-parent = <&i2c_ic>;
560		pinctrl-names = "default";
561		pinctrl-0 = <&pinctrl_i2c7_default>;
562		status = "disabled";
563	};
564
565	i2c7: i2c-bus@300 {
566		#address-cells = <1>;
567		#size-cells = <0>;
568		#interrupt-cells = <1>;
569
570		reg = <0x300 0x40>;
571		compatible = "aspeed,ast2400-i2c-bus";
572		clocks = <&syscon ASPEED_CLK_APB>;
573		resets = <&syscon ASPEED_RESET_I2C>;
574		bus-frequency = <100000>;
575		interrupts = <7>;
576		interrupt-parent = <&i2c_ic>;
577		pinctrl-names = "default";
578		pinctrl-0 = <&pinctrl_i2c8_default>;
579		status = "disabled";
580	};
581
582	i2c8: i2c-bus@340 {
583		#address-cells = <1>;
584		#size-cells = <0>;
585		#interrupt-cells = <1>;
586
587		reg = <0x340 0x40>;
588		compatible = "aspeed,ast2400-i2c-bus";
589		clocks = <&syscon ASPEED_CLK_APB>;
590		resets = <&syscon ASPEED_RESET_I2C>;
591		bus-frequency = <100000>;
592		interrupts = <8>;
593		interrupt-parent = <&i2c_ic>;
594		pinctrl-names = "default";
595		pinctrl-0 = <&pinctrl_i2c9_default>;
596		status = "disabled";
597	};
598
599	i2c9: i2c-bus@380 {
600		#address-cells = <1>;
601		#size-cells = <0>;
602		#interrupt-cells = <1>;
603
604		reg = <0x380 0x40>;
605		compatible = "aspeed,ast2400-i2c-bus";
606		clocks = <&syscon ASPEED_CLK_APB>;
607		resets = <&syscon ASPEED_RESET_I2C>;
608		bus-frequency = <100000>;
609		interrupts = <9>;
610		interrupt-parent = <&i2c_ic>;
611		pinctrl-names = "default";
612		pinctrl-0 = <&pinctrl_i2c10_default>;
613		status = "disabled";
614	};
615
616	i2c10: i2c-bus@3c0 {
617		#address-cells = <1>;
618		#size-cells = <0>;
619		#interrupt-cells = <1>;
620
621		reg = <0x3c0 0x40>;
622		compatible = "aspeed,ast2400-i2c-bus";
623		clocks = <&syscon ASPEED_CLK_APB>;
624		resets = <&syscon ASPEED_RESET_I2C>;
625		bus-frequency = <100000>;
626		interrupts = <10>;
627		interrupt-parent = <&i2c_ic>;
628		pinctrl-names = "default";
629		pinctrl-0 = <&pinctrl_i2c11_default>;
630		status = "disabled";
631	};
632
633	i2c11: i2c-bus@400 {
634		#address-cells = <1>;
635		#size-cells = <0>;
636		#interrupt-cells = <1>;
637
638		reg = <0x400 0x40>;
639		compatible = "aspeed,ast2400-i2c-bus";
640		clocks = <&syscon ASPEED_CLK_APB>;
641		resets = <&syscon ASPEED_RESET_I2C>;
642		bus-frequency = <100000>;
643		interrupts = <11>;
644		interrupt-parent = <&i2c_ic>;
645		pinctrl-names = "default";
646		pinctrl-0 = <&pinctrl_i2c12_default>;
647		status = "disabled";
648	};
649
650	i2c12: i2c-bus@440 {
651		#address-cells = <1>;
652		#size-cells = <0>;
653		#interrupt-cells = <1>;
654
655		reg = <0x440 0x40>;
656		compatible = "aspeed,ast2400-i2c-bus";
657		clocks = <&syscon ASPEED_CLK_APB>;
658		resets = <&syscon ASPEED_RESET_I2C>;
659		bus-frequency = <100000>;
660		interrupts = <12>;
661		interrupt-parent = <&i2c_ic>;
662		pinctrl-names = "default";
663		pinctrl-0 = <&pinctrl_i2c13_default>;
664		status = "disabled";
665	};
666
667	i2c13: i2c-bus@480 {
668		#address-cells = <1>;
669		#size-cells = <0>;
670		#interrupt-cells = <1>;
671
672		reg = <0x480 0x40>;
673		compatible = "aspeed,ast2400-i2c-bus";
674		clocks = <&syscon ASPEED_CLK_APB>;
675		resets = <&syscon ASPEED_RESET_I2C>;
676		bus-frequency = <100000>;
677		interrupts = <13>;
678		interrupt-parent = <&i2c_ic>;
679		pinctrl-names = "default";
680		pinctrl-0 = <&pinctrl_i2c14_default>;
681		status = "disabled";
682	};
683};
684
685&pinctrl {
686	pinctrl_acpi_default: acpi_default {
687		function = "ACPI";
688		groups = "ACPI";
689	};
690
691	pinctrl_adc0_default: adc0_default {
692		function = "ADC0";
693		groups = "ADC0";
694	};
695
696	pinctrl_adc1_default: adc1_default {
697		function = "ADC1";
698		groups = "ADC1";
699	};
700
701	pinctrl_adc10_default: adc10_default {
702		function = "ADC10";
703		groups = "ADC10";
704	};
705
706	pinctrl_adc11_default: adc11_default {
707		function = "ADC11";
708		groups = "ADC11";
709	};
710
711	pinctrl_adc12_default: adc12_default {
712		function = "ADC12";
713		groups = "ADC12";
714	};
715
716	pinctrl_adc13_default: adc13_default {
717		function = "ADC13";
718		groups = "ADC13";
719	};
720
721	pinctrl_adc14_default: adc14_default {
722		function = "ADC14";
723		groups = "ADC14";
724	};
725
726	pinctrl_adc15_default: adc15_default {
727		function = "ADC15";
728		groups = "ADC15";
729	};
730
731	pinctrl_adc2_default: adc2_default {
732		function = "ADC2";
733		groups = "ADC2";
734	};
735
736	pinctrl_adc3_default: adc3_default {
737		function = "ADC3";
738		groups = "ADC3";
739	};
740
741	pinctrl_adc4_default: adc4_default {
742		function = "ADC4";
743		groups = "ADC4";
744	};
745
746	pinctrl_adc5_default: adc5_default {
747		function = "ADC5";
748		groups = "ADC5";
749	};
750
751	pinctrl_adc6_default: adc6_default {
752		function = "ADC6";
753		groups = "ADC6";
754	};
755
756	pinctrl_adc7_default: adc7_default {
757		function = "ADC7";
758		groups = "ADC7";
759	};
760
761	pinctrl_adc8_default: adc8_default {
762		function = "ADC8";
763		groups = "ADC8";
764	};
765
766	pinctrl_adc9_default: adc9_default {
767		function = "ADC9";
768		groups = "ADC9";
769	};
770
771	pinctrl_bmcint_default: bmcint_default {
772		function = "BMCINT";
773		groups = "BMCINT";
774	};
775
776	pinctrl_ddcclk_default: ddcclk_default {
777		function = "DDCCLK";
778		groups = "DDCCLK";
779	};
780
781	pinctrl_ddcdat_default: ddcdat_default {
782		function = "DDCDAT";
783		groups = "DDCDAT";
784	};
785
786	pinctrl_extrst_default: extrst_default {
787		function = "EXTRST";
788		groups = "EXTRST";
789	};
790
791	pinctrl_flack_default: flack_default {
792		function = "FLACK";
793		groups = "FLACK";
794	};
795
796	pinctrl_flbusy_default: flbusy_default {
797		function = "FLBUSY";
798		groups = "FLBUSY";
799	};
800
801	pinctrl_flwp_default: flwp_default {
802		function = "FLWP";
803		groups = "FLWP";
804	};
805
806	pinctrl_gpid_default: gpid_default {
807		function = "GPID";
808		groups = "GPID";
809	};
810
811	pinctrl_gpid0_default: gpid0_default {
812		function = "GPID0";
813		groups = "GPID0";
814	};
815
816	pinctrl_gpid2_default: gpid2_default {
817		function = "GPID2";
818		groups = "GPID2";
819	};
820
821	pinctrl_gpid4_default: gpid4_default {
822		function = "GPID4";
823		groups = "GPID4";
824	};
825
826	pinctrl_gpid6_default: gpid6_default {
827		function = "GPID6";
828		groups = "GPID6";
829	};
830
831	pinctrl_gpie0_default: gpie0_default {
832		function = "GPIE0";
833		groups = "GPIE0";
834	};
835
836	pinctrl_gpie2_default: gpie2_default {
837		function = "GPIE2";
838		groups = "GPIE2";
839	};
840
841	pinctrl_gpie4_default: gpie4_default {
842		function = "GPIE4";
843		groups = "GPIE4";
844	};
845
846	pinctrl_gpie6_default: gpie6_default {
847		function = "GPIE6";
848		groups = "GPIE6";
849	};
850
851	pinctrl_i2c10_default: i2c10_default {
852		function = "I2C10";
853		groups = "I2C10";
854	};
855
856	pinctrl_i2c11_default: i2c11_default {
857		function = "I2C11";
858		groups = "I2C11";
859	};
860
861	pinctrl_i2c12_default: i2c12_default {
862		function = "I2C12";
863		groups = "I2C12";
864	};
865
866	pinctrl_i2c13_default: i2c13_default {
867		function = "I2C13";
868		groups = "I2C13";
869	};
870
871	pinctrl_i2c14_default: i2c14_default {
872		function = "I2C14";
873		groups = "I2C14";
874	};
875
876	pinctrl_i2c3_default: i2c3_default {
877		function = "I2C3";
878		groups = "I2C3";
879	};
880
881	pinctrl_i2c4_default: i2c4_default {
882		function = "I2C4";
883		groups = "I2C4";
884	};
885
886	pinctrl_i2c5_default: i2c5_default {
887		function = "I2C5";
888		groups = "I2C5";
889	};
890
891	pinctrl_i2c6_default: i2c6_default {
892		function = "I2C6";
893		groups = "I2C6";
894	};
895
896	pinctrl_i2c7_default: i2c7_default {
897		function = "I2C7";
898		groups = "I2C7";
899	};
900
901	pinctrl_i2c8_default: i2c8_default {
902		function = "I2C8";
903		groups = "I2C8";
904	};
905
906	pinctrl_i2c9_default: i2c9_default {
907		function = "I2C9";
908		groups = "I2C9";
909	};
910
911	pinctrl_lpcpd_default: lpcpd_default {
912		function = "LPCPD";
913		groups = "LPCPD";
914	};
915
916	pinctrl_lpcpme_default: lpcpme_default {
917		function = "LPCPME";
918		groups = "LPCPME";
919	};
920
921	pinctrl_lpcrst_default: lpcrst_default {
922		function = "LPCRST";
923		groups = "LPCRST";
924	};
925
926	pinctrl_lpcsmi_default: lpcsmi_default {
927		function = "LPCSMI";
928		groups = "LPCSMI";
929	};
930
931	pinctrl_mac1link_default: mac1link_default {
932		function = "MAC1LINK";
933		groups = "MAC1LINK";
934	};
935
936	pinctrl_mac2link_default: mac2link_default {
937		function = "MAC2LINK";
938		groups = "MAC2LINK";
939	};
940
941	pinctrl_mdio1_default: mdio1_default {
942		function = "MDIO1";
943		groups = "MDIO1";
944	};
945
946	pinctrl_mdio2_default: mdio2_default {
947		function = "MDIO2";
948		groups = "MDIO2";
949	};
950
951	pinctrl_ncts1_default: ncts1_default {
952		function = "NCTS1";
953		groups = "NCTS1";
954	};
955
956	pinctrl_ncts2_default: ncts2_default {
957		function = "NCTS2";
958		groups = "NCTS2";
959	};
960
961	pinctrl_ncts3_default: ncts3_default {
962		function = "NCTS3";
963		groups = "NCTS3";
964	};
965
966	pinctrl_ncts4_default: ncts4_default {
967		function = "NCTS4";
968		groups = "NCTS4";
969	};
970
971	pinctrl_ndcd1_default: ndcd1_default {
972		function = "NDCD1";
973		groups = "NDCD1";
974	};
975
976	pinctrl_ndcd2_default: ndcd2_default {
977		function = "NDCD2";
978		groups = "NDCD2";
979	};
980
981	pinctrl_ndcd3_default: ndcd3_default {
982		function = "NDCD3";
983		groups = "NDCD3";
984	};
985
986	pinctrl_ndcd4_default: ndcd4_default {
987		function = "NDCD4";
988		groups = "NDCD4";
989	};
990
991	pinctrl_ndsr1_default: ndsr1_default {
992		function = "NDSR1";
993		groups = "NDSR1";
994	};
995
996	pinctrl_ndsr2_default: ndsr2_default {
997		function = "NDSR2";
998		groups = "NDSR2";
999	};
1000
1001	pinctrl_ndsr3_default: ndsr3_default {
1002		function = "NDSR3";
1003		groups = "NDSR3";
1004	};
1005
1006	pinctrl_ndsr4_default: ndsr4_default {
1007		function = "NDSR4";
1008		groups = "NDSR4";
1009	};
1010
1011	pinctrl_ndtr1_default: ndtr1_default {
1012		function = "NDTR1";
1013		groups = "NDTR1";
1014	};
1015
1016	pinctrl_ndtr2_default: ndtr2_default {
1017		function = "NDTR2";
1018		groups = "NDTR2";
1019	};
1020
1021	pinctrl_ndtr3_default: ndtr3_default {
1022		function = "NDTR3";
1023		groups = "NDTR3";
1024	};
1025
1026	pinctrl_ndtr4_default: ndtr4_default {
1027		function = "NDTR4";
1028		groups = "NDTR4";
1029	};
1030
1031	pinctrl_ndts4_default: ndts4_default {
1032		function = "NDTS4";
1033		groups = "NDTS4";
1034	};
1035
1036	pinctrl_nri1_default: nri1_default {
1037		function = "NRI1";
1038		groups = "NRI1";
1039	};
1040
1041	pinctrl_nri2_default: nri2_default {
1042		function = "NRI2";
1043		groups = "NRI2";
1044	};
1045
1046	pinctrl_nri3_default: nri3_default {
1047		function = "NRI3";
1048		groups = "NRI3";
1049	};
1050
1051	pinctrl_nri4_default: nri4_default {
1052		function = "NRI4";
1053		groups = "NRI4";
1054	};
1055
1056	pinctrl_nrts1_default: nrts1_default {
1057		function = "NRTS1";
1058		groups = "NRTS1";
1059	};
1060
1061	pinctrl_nrts2_default: nrts2_default {
1062		function = "NRTS2";
1063		groups = "NRTS2";
1064	};
1065
1066	pinctrl_nrts3_default: nrts3_default {
1067		function = "NRTS3";
1068		groups = "NRTS3";
1069	};
1070
1071	pinctrl_oscclk_default: oscclk_default {
1072		function = "OSCCLK";
1073		groups = "OSCCLK";
1074	};
1075
1076	pinctrl_pwm0_default: pwm0_default {
1077		function = "PWM0";
1078		groups = "PWM0";
1079	};
1080
1081	pinctrl_pwm1_default: pwm1_default {
1082		function = "PWM1";
1083		groups = "PWM1";
1084	};
1085
1086	pinctrl_pwm2_default: pwm2_default {
1087		function = "PWM2";
1088		groups = "PWM2";
1089	};
1090
1091	pinctrl_pwm3_default: pwm3_default {
1092		function = "PWM3";
1093		groups = "PWM3";
1094	};
1095
1096	pinctrl_pwm4_default: pwm4_default {
1097		function = "PWM4";
1098		groups = "PWM4";
1099	};
1100
1101	pinctrl_pwm5_default: pwm5_default {
1102		function = "PWM5";
1103		groups = "PWM5";
1104	};
1105
1106	pinctrl_pwm6_default: pwm6_default {
1107		function = "PWM6";
1108		groups = "PWM6";
1109	};
1110
1111	pinctrl_pwm7_default: pwm7_default {
1112		function = "PWM7";
1113		groups = "PWM7";
1114	};
1115
1116	pinctrl_rgmii1_default: rgmii1_default {
1117		function = "RGMII1";
1118		groups = "RGMII1";
1119	};
1120
1121	pinctrl_rgmii2_default: rgmii2_default {
1122		function = "RGMII2";
1123		groups = "RGMII2";
1124	};
1125
1126	pinctrl_rmii1_default: rmii1_default {
1127		function = "RMII1";
1128		groups = "RMII1";
1129	};
1130
1131	pinctrl_rmii2_default: rmii2_default {
1132		function = "RMII2";
1133		groups = "RMII2";
1134	};
1135
1136	pinctrl_rom16_default: rom16_default {
1137		function = "ROM16";
1138		groups = "ROM16";
1139	};
1140
1141	pinctrl_rom8_default: rom8_default {
1142		function = "ROM8";
1143		groups = "ROM8";
1144	};
1145
1146	pinctrl_romcs1_default: romcs1_default {
1147		function = "ROMCS1";
1148		groups = "ROMCS1";
1149	};
1150
1151	pinctrl_romcs2_default: romcs2_default {
1152		function = "ROMCS2";
1153		groups = "ROMCS2";
1154	};
1155
1156	pinctrl_romcs3_default: romcs3_default {
1157		function = "ROMCS3";
1158		groups = "ROMCS3";
1159	};
1160
1161	pinctrl_romcs4_default: romcs4_default {
1162		function = "ROMCS4";
1163		groups = "ROMCS4";
1164	};
1165
1166	pinctrl_rxd1_default: rxd1_default {
1167		function = "RXD1";
1168		groups = "RXD1";
1169	};
1170
1171	pinctrl_rxd2_default: rxd2_default {
1172		function = "RXD2";
1173		groups = "RXD2";
1174	};
1175
1176	pinctrl_rxd3_default: rxd3_default {
1177		function = "RXD3";
1178		groups = "RXD3";
1179	};
1180
1181	pinctrl_rxd4_default: rxd4_default {
1182		function = "RXD4";
1183		groups = "RXD4";
1184	};
1185
1186	pinctrl_salt1_default: salt1_default {
1187		function = "SALT1";
1188		groups = "SALT1";
1189	};
1190
1191	pinctrl_salt2_default: salt2_default {
1192		function = "SALT2";
1193		groups = "SALT2";
1194	};
1195
1196	pinctrl_salt3_default: salt3_default {
1197		function = "SALT3";
1198		groups = "SALT3";
1199	};
1200
1201	pinctrl_salt4_default: salt4_default {
1202		function = "SALT4";
1203		groups = "SALT4";
1204	};
1205
1206	pinctrl_sd1_default: sd1_default {
1207		function = "SD1";
1208		groups = "SD1";
1209	};
1210
1211	pinctrl_sd2_default: sd2_default {
1212		function = "SD2";
1213		groups = "SD2";
1214	};
1215
1216	pinctrl_sgpmck_default: sgpmck_default {
1217		function = "SGPMCK";
1218		groups = "SGPMCK";
1219	};
1220
1221	pinctrl_sgpmi_default: sgpmi_default {
1222		function = "SGPMI";
1223		groups = "SGPMI";
1224	};
1225
1226	pinctrl_sgpmld_default: sgpmld_default {
1227		function = "SGPMLD";
1228		groups = "SGPMLD";
1229	};
1230
1231	pinctrl_sgpmo_default: sgpmo_default {
1232		function = "SGPMO";
1233		groups = "SGPMO";
1234	};
1235
1236	pinctrl_sgpsck_default: sgpsck_default {
1237		function = "SGPSCK";
1238		groups = "SGPSCK";
1239	};
1240
1241	pinctrl_sgpsi0_default: sgpsi0_default {
1242		function = "SGPSI0";
1243		groups = "SGPSI0";
1244	};
1245
1246	pinctrl_sgpsi1_default: sgpsi1_default {
1247		function = "SGPSI1";
1248		groups = "SGPSI1";
1249	};
1250
1251	pinctrl_sgpsld_default: sgpsld_default {
1252		function = "SGPSLD";
1253		groups = "SGPSLD";
1254	};
1255
1256	pinctrl_sioonctrl_default: sioonctrl_default {
1257		function = "SIOONCTRL";
1258		groups = "SIOONCTRL";
1259	};
1260
1261	pinctrl_siopbi_default: siopbi_default {
1262		function = "SIOPBI";
1263		groups = "SIOPBI";
1264	};
1265
1266	pinctrl_siopbo_default: siopbo_default {
1267		function = "SIOPBO";
1268		groups = "SIOPBO";
1269	};
1270
1271	pinctrl_siopwreq_default: siopwreq_default {
1272		function = "SIOPWREQ";
1273		groups = "SIOPWREQ";
1274	};
1275
1276	pinctrl_siopwrgd_default: siopwrgd_default {
1277		function = "SIOPWRGD";
1278		groups = "SIOPWRGD";
1279	};
1280
1281	pinctrl_sios3_default: sios3_default {
1282		function = "SIOS3";
1283		groups = "SIOS3";
1284	};
1285
1286	pinctrl_sios5_default: sios5_default {
1287		function = "SIOS5";
1288		groups = "SIOS5";
1289	};
1290
1291	pinctrl_siosci_default: siosci_default {
1292		function = "SIOSCI";
1293		groups = "SIOSCI";
1294	};
1295
1296	pinctrl_spi1_default: spi1_default {
1297		function = "SPI1";
1298		groups = "SPI1";
1299	};
1300
1301	pinctrl_spi1debug_default: spi1debug_default {
1302		function = "SPI1DEBUG";
1303		groups = "SPI1DEBUG";
1304	};
1305
1306	pinctrl_spi1passthru_default: spi1passthru_default {
1307		function = "SPI1PASSTHRU";
1308		groups = "SPI1PASSTHRU";
1309	};
1310
1311	pinctrl_spics1_default: spics1_default {
1312		function = "SPICS1";
1313		groups = "SPICS1";
1314	};
1315
1316	pinctrl_timer3_default: timer3_default {
1317		function = "TIMER3";
1318		groups = "TIMER3";
1319	};
1320
1321	pinctrl_timer4_default: timer4_default {
1322		function = "TIMER4";
1323		groups = "TIMER4";
1324	};
1325
1326	pinctrl_timer5_default: timer5_default {
1327		function = "TIMER5";
1328		groups = "TIMER5";
1329	};
1330
1331	pinctrl_timer6_default: timer6_default {
1332		function = "TIMER6";
1333		groups = "TIMER6";
1334	};
1335
1336	pinctrl_timer7_default: timer7_default {
1337		function = "TIMER7";
1338		groups = "TIMER7";
1339	};
1340
1341	pinctrl_timer8_default: timer8_default {
1342		function = "TIMER8";
1343		groups = "TIMER8";
1344	};
1345
1346	pinctrl_txd1_default: txd1_default {
1347		function = "TXD1";
1348		groups = "TXD1";
1349	};
1350
1351	pinctrl_txd2_default: txd2_default {
1352		function = "TXD2";
1353		groups = "TXD2";
1354	};
1355
1356	pinctrl_txd3_default: txd3_default {
1357		function = "TXD3";
1358		groups = "TXD3";
1359	};
1360
1361	pinctrl_txd4_default: txd4_default {
1362		function = "TXD4";
1363		groups = "TXD4";
1364	};
1365
1366	pinctrl_uart6_default: uart6_default {
1367		function = "UART6";
1368		groups = "UART6";
1369	};
1370
1371	pinctrl_usbcki_default: usbcki_default {
1372		function = "USBCKI";
1373		groups = "USBCKI";
1374	};
1375
1376	pinctrl_usb2h_default: usb2h_default {
1377		function = "USB2H1";
1378		groups = "USB2H1";
1379	};
1380
1381	pinctrl_usb2d_default: usb2d_default {
1382		function = "USB2D1";
1383		groups = "USB2D1";
1384	};
1385
1386	pinctrl_vgabios_rom_default: vgabios_rom_default {
1387		function = "VGABIOS_ROM";
1388		groups = "VGABIOS_ROM";
1389	};
1390
1391	pinctrl_vgahs_default: vgahs_default {
1392		function = "VGAHS";
1393		groups = "VGAHS";
1394	};
1395
1396	pinctrl_vgavs_default: vgavs_default {
1397		function = "VGAVS";
1398		groups = "VGAVS";
1399	};
1400
1401	pinctrl_vpi18_default: vpi18_default {
1402		function = "VPI18";
1403		groups = "VPI18";
1404	};
1405
1406	pinctrl_vpi24_default: vpi24_default {
1407		function = "VPI24";
1408		groups = "VPI24";
1409	};
1410
1411	pinctrl_vpi30_default: vpi30_default {
1412		function = "VPI30";
1413		groups = "VPI30";
1414	};
1415
1416	pinctrl_vpo12_default: vpo12_default {
1417		function = "VPO12";
1418		groups = "VPO12";
1419	};
1420
1421	pinctrl_vpo24_default: vpo24_default {
1422		function = "VPO24";
1423		groups = "VPO24";
1424	};
1425
1426	pinctrl_wdtrst1_default: wdtrst1_default {
1427		function = "WDTRST1";
1428		groups = "WDTRST1";
1429	};
1430
1431	pinctrl_wdtrst2_default: wdtrst2_default {
1432		function = "WDTRST2";
1433		groups = "WDTRST2";
1434	};
1435};
1436