1 /* 2 * SNI specific definitions 3 * 4 * This file is subject to the terms and conditions of the GNU General Public 5 * License. See the file "COPYING" in the main directory of this archive 6 * for more details. 7 * 8 * Copyright (C) 1997, 1998 by Ralf Baechle 9 * Copyright (C) 2006 Thomas Bogendoerfer (tsbogend@alpha.franken.de) 10 */ 11 #ifndef __ASM_SNI_H 12 #define __ASM_SNI_H 13 14 extern unsigned int sni_brd_type; 15 16 #define SNI_BRD_10 2 17 #define SNI_BRD_10NEW 3 18 #define SNI_BRD_TOWER_OASIC 4 19 #define SNI_BRD_MINITOWER 5 20 #define SNI_BRD_PCI_TOWER 6 21 #define SNI_BRD_RM200 7 22 #define SNI_BRD_PCI_MTOWER 8 23 #define SNI_BRD_PCI_DESKTOP 9 24 #define SNI_BRD_PCI_TOWER_CPLUS 10 25 #define SNI_BRD_PCI_MTOWER_CPLUS 11 26 27 /* RM400 cpu types */ 28 #define SNI_CPU_M8021 0x01 29 #define SNI_CPU_M8030 0x04 30 #define SNI_CPU_M8031 0x06 31 #define SNI_CPU_M8034 0x0f 32 #define SNI_CPU_M8037 0x07 33 #define SNI_CPU_M8040 0x05 34 #define SNI_CPU_M8043 0x09 35 #define SNI_CPU_M8050 0x0b 36 #define SNI_CPU_M8053 0x0d 37 38 #define SNI_PORT_BASE CKSEG1ADDR(0xb4000000) 39 40 #ifndef __MIPSEL__ 41 /* 42 * ASIC PCI registers for big endian configuration. 43 */ 44 #define PCIMT_UCONF CKSEG1ADDR(0xbfff0004) 45 #define PCIMT_IOADTIMEOUT2 CKSEG1ADDR(0xbfff000c) 46 #define PCIMT_IOMEMCONF CKSEG1ADDR(0xbfff0014) 47 #define PCIMT_IOMMU CKSEG1ADDR(0xbfff001c) 48 #define PCIMT_IOADTIMEOUT1 CKSEG1ADDR(0xbfff0024) 49 #define PCIMT_DMAACCESS CKSEG1ADDR(0xbfff002c) 50 #define PCIMT_DMAHIT CKSEG1ADDR(0xbfff0034) 51 #define PCIMT_ERRSTATUS CKSEG1ADDR(0xbfff003c) 52 #define PCIMT_ERRADDR CKSEG1ADDR(0xbfff0044) 53 #define PCIMT_SYNDROME CKSEG1ADDR(0xbfff004c) 54 #define PCIMT_ITPEND CKSEG1ADDR(0xbfff0054) 55 #define IT_INT2 0x01 56 #define IT_INTD 0x02 57 #define IT_INTC 0x04 58 #define IT_INTB 0x08 59 #define IT_INTA 0x10 60 #define IT_EISA 0x20 61 #define IT_SCSI 0x40 62 #define IT_ETH 0x80 63 #define PCIMT_IRQSEL CKSEG1ADDR(0xbfff005c) 64 #define PCIMT_TESTMEM CKSEG1ADDR(0xbfff0064) 65 #define PCIMT_ECCREG CKSEG1ADDR(0xbfff006c) 66 #define PCIMT_CONFIG_ADDRESS CKSEG1ADDR(0xbfff0074) 67 #define PCIMT_ASIC_ID CKSEG1ADDR(0xbfff007c) /* read */ 68 #define PCIMT_SOFT_RESET CKSEG1ADDR(0xbfff007c) /* write */ 69 #define PCIMT_PIA_OE CKSEG1ADDR(0xbfff0084) 70 #define PCIMT_PIA_DATAOUT CKSEG1ADDR(0xbfff008c) 71 #define PCIMT_PIA_DATAIN CKSEG1ADDR(0xbfff0094) 72 #define PCIMT_CACHECONF CKSEG1ADDR(0xbfff009c) 73 #define PCIMT_INVSPACE CKSEG1ADDR(0xbfff00a4) 74 #else 75 /* 76 * ASIC PCI registers for little endian configuration. 77 */ 78 #define PCIMT_UCONF CKSEG1ADDR(0xbfff0000) 79 #define PCIMT_IOADTIMEOUT2 CKSEG1ADDR(0xbfff0008) 80 #define PCIMT_IOMEMCONF CKSEG1ADDR(0xbfff0010) 81 #define PCIMT_IOMMU CKSEG1ADDR(0xbfff0018) 82 #define PCIMT_IOADTIMEOUT1 CKSEG1ADDR(0xbfff0020) 83 #define PCIMT_DMAACCESS CKSEG1ADDR(0xbfff0028) 84 #define PCIMT_DMAHIT CKSEG1ADDR(0xbfff0030) 85 #define PCIMT_ERRSTATUS CKSEG1ADDR(0xbfff0038) 86 #define PCIMT_ERRADDR CKSEG1ADDR(0xbfff0040) 87 #define PCIMT_SYNDROME CKSEG1ADDR(0xbfff0048) 88 #define PCIMT_ITPEND CKSEG1ADDR(0xbfff0050) 89 #define IT_INT2 0x01 90 #define IT_INTD 0x02 91 #define IT_INTC 0x04 92 #define IT_INTB 0x08 93 #define IT_INTA 0x10 94 #define IT_EISA 0x20 95 #define IT_SCSI 0x40 96 #define IT_ETH 0x80 97 #define PCIMT_IRQSEL CKSEG1ADDR(0xbfff0058) 98 #define PCIMT_TESTMEM CKSEG1ADDR(0xbfff0060) 99 #define PCIMT_ECCREG CKSEG1ADDR(0xbfff0068) 100 #define PCIMT_CONFIG_ADDRESS CKSEG1ADDR(0xbfff0070) 101 #define PCIMT_ASIC_ID CKSEG1ADDR(0xbfff0078) /* read */ 102 #define PCIMT_SOFT_RESET CKSEG1ADDR(0xbfff0078) /* write */ 103 #define PCIMT_PIA_OE CKSEG1ADDR(0xbfff0080) 104 #define PCIMT_PIA_DATAOUT CKSEG1ADDR(0xbfff0088) 105 #define PCIMT_PIA_DATAIN CKSEG1ADDR(0xbfff0090) 106 #define PCIMT_CACHECONF CKSEG1ADDR(0xbfff0098) 107 #define PCIMT_INVSPACE CKSEG1ADDR(0xbfff00a0) 108 #endif 109 110 #define PCIMT_PCI_CONF CKSEG1ADDR(0xbfff0100) 111 112 /* 113 * Data port for the PCI bus in IO space 114 */ 115 #define PCIMT_CONFIG_DATA 0x0cfc 116 117 /* 118 * Board specific registers 119 */ 120 #define PCIMT_CSMSR CKSEG1ADDR(0xbfd00000) 121 #define PCIMT_CSSWITCH CKSEG1ADDR(0xbfd10000) 122 #define PCIMT_CSITPEND CKSEG1ADDR(0xbfd20000) 123 #define PCIMT_AUTO_PO_EN CKSEG1ADDR(0xbfd30000) 124 #define PCIMT_CLR_TEMP CKSEG1ADDR(0xbfd40000) 125 #define PCIMT_AUTO_PO_DIS CKSEG1ADDR(0xbfd50000) 126 #define PCIMT_EXMSR CKSEG1ADDR(0xbfd60000) 127 #define PCIMT_UNUSED1 CKSEG1ADDR(0xbfd70000) 128 #define PCIMT_CSWCSM CKSEG1ADDR(0xbfd80000) 129 #define PCIMT_UNUSED2 CKSEG1ADDR(0xbfd90000) 130 #define PCIMT_CSLED CKSEG1ADDR(0xbfda0000) 131 #define PCIMT_CSMAPISA CKSEG1ADDR(0xbfdb0000) 132 #define PCIMT_CSRSTBP CKSEG1ADDR(0xbfdc0000) 133 #define PCIMT_CLRPOFF CKSEG1ADDR(0xbfdd0000) 134 #define PCIMT_CSTIMER CKSEG1ADDR(0xbfde0000) 135 #define PCIMT_PWDN CKSEG1ADDR(0xbfdf0000) 136 137 /* 138 * A20R based boards 139 */ 140 #define A20R_PT_CLOCK_BASE CKSEG1ADDR(0xbc040000) 141 #define A20R_PT_TIM0_ACK CKSEG1ADDR(0xbc050000) 142 #define A20R_PT_TIM1_ACK CKSEG1ADDR(0xbc060000) 143 144 #define SNI_A20R_IRQ_BASE MIPS_CPU_IRQ_BASE 145 #define SNI_A20R_IRQ_TIMER (SNI_A20R_IRQ_BASE+5) 146 147 #define SNI_PCIT_INT_REG CKSEG1ADDR(0xbfff000c) 148 149 #define SNI_PCIT_INT_START 24 150 #define SNI_PCIT_INT_END 30 151 152 #define PCIT_IRQ_ETHERNET (MIPS_CPU_IRQ_BASE + 5) 153 #define PCIT_IRQ_INTA (SNI_PCIT_INT_START + 0) 154 #define PCIT_IRQ_INTB (SNI_PCIT_INT_START + 1) 155 #define PCIT_IRQ_INTC (SNI_PCIT_INT_START + 2) 156 #define PCIT_IRQ_INTD (SNI_PCIT_INT_START + 3) 157 #define PCIT_IRQ_SCSI0 (SNI_PCIT_INT_START + 4) 158 #define PCIT_IRQ_SCSI1 (SNI_PCIT_INT_START + 5) 159 160 161 /* 162 * Interrupt 0-16 are EISA interrupts. Interrupts from 16 on are assigned 163 * to the other interrupts generated by ASIC PCI. 164 * 165 * INT2 is a wired-or of the push button interrupt, high temperature interrupt 166 * ASIC PCI interrupt. 167 */ 168 #define PCIMT_KEYBOARD_IRQ 1 169 #define PCIMT_IRQ_INT2 24 170 #define PCIMT_IRQ_INTD 25 171 #define PCIMT_IRQ_INTC 26 172 #define PCIMT_IRQ_INTB 27 173 #define PCIMT_IRQ_INTA 28 174 #define PCIMT_IRQ_EISA 29 175 #define PCIMT_IRQ_SCSI 30 176 177 #define PCIMT_IRQ_ETHERNET (MIPS_CPU_IRQ_BASE+6) 178 179 #if 0 180 #define PCIMT_IRQ_TEMPERATURE 24 181 #define PCIMT_IRQ_EISA_NMI 25 182 #define PCIMT_IRQ_POWER_OFF 26 183 #define PCIMT_IRQ_BUTTON 27 184 #endif 185 186 /* 187 * Base address for the mapped 16mb EISA bus segment. 188 */ 189 #define PCIMT_EISA_BASE CKSEG1ADDR(0xb0000000) 190 191 /* PCI EISA Interrupt acknowledge */ 192 #define PCIMT_INT_ACKNOWLEDGE CKSEG1ADDR(0xba000000) 193 194 /* 195 * SNI ID PROM 196 * 197 * SNI_IDPROM_MEMSIZE Memsize in 16MB quantities 198 * SNI_IDPROM_BRDTYPE Board Type 199 * SNI_IDPROM_CPUTYPE CPU Type on RM400 200 */ 201 #ifdef CONFIG_CPU_BIG_ENDIAN 202 #define __SNI_END 0 203 #endif 204 #ifdef CONFIG_CPU_LITTLE_ENDIAN 205 #define __SNI_END 3 206 #endif 207 #define SNI_IDPROM_BASE CKSEG1ADDR(0x1ff00000) 208 #define SNI_IDPROM_MEMSIZE (SNI_IDPROM_BASE + (0x28 ^ __SNI_END)) 209 #define SNI_IDPROM_BRDTYPE (SNI_IDPROM_BASE + (0x29 ^ __SNI_END)) 210 #define SNI_IDPROM_CPUTYPE (SNI_IDPROM_BASE + (0x30 ^ __SNI_END)) 211 212 #define SNI_IDPROM_SIZE 0x1000 213 214 /* board specific init functions */ 215 extern void sni_a20r_init(void); 216 extern void sni_pcit_init(void); 217 extern void sni_rm200_init(void); 218 extern void sni_pcimt_init(void); 219 220 /* board specific irq init functions */ 221 extern void sni_a20r_irq_init(void); 222 extern void sni_pcit_irq_init(void); 223 extern void sni_pcit_cplus_irq_init(void); 224 extern void sni_rm200_irq_init(void); 225 extern void sni_pcimt_irq_init(void); 226 227 /* timer inits */ 228 extern void sni_cpu_time_init(void); 229 230 /* eisa init for RM200/400 */ 231 #ifdef CONFIG_EISA 232 extern int sni_eisa_root_init(void); 233 #else sni_eisa_root_init(void)234static inline int sni_eisa_root_init(void) 235 { 236 return 0; 237 } 238 #endif 239 240 /* common irq stuff */ 241 extern void (*sni_hwint)(void); 242 extern struct irqaction sni_isa_irq; 243 244 #endif /* __ASM_SNI_H */ 245
