1 /*
2 * Atheros AR71XX/AR724X/AR913X common definitions
3 *
4 * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
5 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
6 *
7 * Parts of this file are based on Atheros' 2.6.15 BSP
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License version 2 as published
11 * by the Free Software Foundation.
12 */
13
14 #ifndef __ASM_MACH_ATH79_H
15 #define __ASM_MACH_ATH79_H
16
17 #include <linux/types.h>
18 #include <linux/io.h>
19
20 enum ath79_soc_type {
21 ATH79_SOC_UNKNOWN,
22 ATH79_SOC_AR7130,
23 ATH79_SOC_AR7141,
24 ATH79_SOC_AR7161,
25 ATH79_SOC_AR7240,
26 ATH79_SOC_AR7241,
27 ATH79_SOC_AR7242,
28 ATH79_SOC_AR9130,
29 ATH79_SOC_AR9132,
30 ATH79_SOC_AR9330,
31 ATH79_SOC_AR9331,
32 ATH79_SOC_AR9341,
33 ATH79_SOC_AR9342,
34 ATH79_SOC_AR9344,
35 ATH79_SOC_QCA9533,
36 ATH79_SOC_QCA9556,
37 ATH79_SOC_QCA9558,
38 ATH79_SOC_TP9343,
39 ATH79_SOC_QCA956X,
40 };
41
42 extern enum ath79_soc_type ath79_soc;
43 extern unsigned int ath79_soc_rev;
44
soc_is_ar71xx(void)45 static inline int soc_is_ar71xx(void)
46 {
47 return (ath79_soc == ATH79_SOC_AR7130 ||
48 ath79_soc == ATH79_SOC_AR7141 ||
49 ath79_soc == ATH79_SOC_AR7161);
50 }
51
soc_is_ar724x(void)52 static inline int soc_is_ar724x(void)
53 {
54 return (ath79_soc == ATH79_SOC_AR7240 ||
55 ath79_soc == ATH79_SOC_AR7241 ||
56 ath79_soc == ATH79_SOC_AR7242);
57 }
58
soc_is_ar7240(void)59 static inline int soc_is_ar7240(void)
60 {
61 return (ath79_soc == ATH79_SOC_AR7240);
62 }
63
soc_is_ar7241(void)64 static inline int soc_is_ar7241(void)
65 {
66 return (ath79_soc == ATH79_SOC_AR7241);
67 }
68
soc_is_ar7242(void)69 static inline int soc_is_ar7242(void)
70 {
71 return (ath79_soc == ATH79_SOC_AR7242);
72 }
73
soc_is_ar913x(void)74 static inline int soc_is_ar913x(void)
75 {
76 return (ath79_soc == ATH79_SOC_AR9130 ||
77 ath79_soc == ATH79_SOC_AR9132);
78 }
79
soc_is_ar933x(void)80 static inline int soc_is_ar933x(void)
81 {
82 return (ath79_soc == ATH79_SOC_AR9330 ||
83 ath79_soc == ATH79_SOC_AR9331);
84 }
85
soc_is_ar9341(void)86 static inline int soc_is_ar9341(void)
87 {
88 return (ath79_soc == ATH79_SOC_AR9341);
89 }
90
soc_is_ar9342(void)91 static inline int soc_is_ar9342(void)
92 {
93 return (ath79_soc == ATH79_SOC_AR9342);
94 }
95
soc_is_ar9344(void)96 static inline int soc_is_ar9344(void)
97 {
98 return (ath79_soc == ATH79_SOC_AR9344);
99 }
100
soc_is_ar934x(void)101 static inline int soc_is_ar934x(void)
102 {
103 return soc_is_ar9341() || soc_is_ar9342() || soc_is_ar9344();
104 }
105
soc_is_qca9533(void)106 static inline int soc_is_qca9533(void)
107 {
108 return ath79_soc == ATH79_SOC_QCA9533;
109 }
110
soc_is_qca953x(void)111 static inline int soc_is_qca953x(void)
112 {
113 return soc_is_qca9533();
114 }
115
soc_is_qca9556(void)116 static inline int soc_is_qca9556(void)
117 {
118 return ath79_soc == ATH79_SOC_QCA9556;
119 }
120
soc_is_qca9558(void)121 static inline int soc_is_qca9558(void)
122 {
123 return ath79_soc == ATH79_SOC_QCA9558;
124 }
125
soc_is_qca955x(void)126 static inline int soc_is_qca955x(void)
127 {
128 return soc_is_qca9556() || soc_is_qca9558();
129 }
130
soc_is_tp9343(void)131 static inline int soc_is_tp9343(void)
132 {
133 return ath79_soc == ATH79_SOC_TP9343;
134 }
135
soc_is_qca9561(void)136 static inline int soc_is_qca9561(void)
137 {
138 return ath79_soc == ATH79_SOC_QCA956X;
139 }
140
soc_is_qca9563(void)141 static inline int soc_is_qca9563(void)
142 {
143 return ath79_soc == ATH79_SOC_QCA956X;
144 }
145
soc_is_qca956x(void)146 static inline int soc_is_qca956x(void)
147 {
148 return soc_is_qca9561() || soc_is_qca9563();
149 }
150
151 void ath79_ddr_wb_flush(unsigned int reg);
152 void ath79_ddr_set_pci_windows(void);
153
154 extern void __iomem *ath79_pll_base;
155 extern void __iomem *ath79_reset_base;
156
ath79_pll_wr(unsigned reg,u32 val)157 static inline void ath79_pll_wr(unsigned reg, u32 val)
158 {
159 __raw_writel(val, ath79_pll_base + reg);
160 }
161
ath79_pll_rr(unsigned reg)162 static inline u32 ath79_pll_rr(unsigned reg)
163 {
164 return __raw_readl(ath79_pll_base + reg);
165 }
166
ath79_reset_wr(unsigned reg,u32 val)167 static inline void ath79_reset_wr(unsigned reg, u32 val)
168 {
169 __raw_writel(val, ath79_reset_base + reg);
170 (void) __raw_readl(ath79_reset_base + reg); /* flush */
171 }
172
ath79_reset_rr(unsigned reg)173 static inline u32 ath79_reset_rr(unsigned reg)
174 {
175 return __raw_readl(ath79_reset_base + reg);
176 }
177
178 void ath79_device_reset_set(u32 mask);
179 void ath79_device_reset_clear(u32 mask);
180
181 void ath79_cpu_irq_init(unsigned irq_wb_chan2, unsigned irq_wb_chan3);
182 void ath79_misc_irq_init(void __iomem *regs, int irq,
183 int irq_base, bool is_ar71xx);
184
185 #endif /* __ASM_MACH_ATH79_H */
186
