1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2/*
3 * Device Tree include file for SolidRun Clearfog 88F6828 based boards
4 *
5 *  Copyright (C) 2015 Russell King
6 */
7
8#include "armada-388.dtsi"
9#include "armada-38x-solidrun-microsom.dtsi"
10
11/ {
12	aliases {
13		/* So that mvebu u-boot can update the MAC addresses */
14		ethernet1 = &eth0;
15		ethernet2 = &eth1;
16		ethernet3 = &eth2;
17	};
18
19	chosen {
20		stdout-path = "serial0:115200n8";
21	};
22
23	reg_3p3v: regulator-3p3v {
24		compatible = "regulator-fixed";
25		regulator-name = "3P3V";
26		regulator-min-microvolt = <3300000>;
27		regulator-max-microvolt = <3300000>;
28		regulator-always-on;
29	};
30
31	soc {
32		internal-regs {
33			sata@a8000 {
34				/* pinctrl? */
35				status = "okay";
36			};
37
38			sata@e0000 {
39				/* pinctrl? */
40				status = "okay";
41			};
42
43			sdhci@d8000 {
44				bus-width = <4>;
45				cd-gpios = <&gpio0 20 GPIO_ACTIVE_LOW>;
46				no-1-8-v;
47				pinctrl-0 = <&microsom_sdhci_pins
48					     &clearfog_sdhci_cd_pins>;
49				pinctrl-names = "default";
50				status = "okay";
51				vmmc-supply = <&reg_3p3v>;
52				wp-inverted;
53			};
54
55			usb@58000 {
56				/* CON3, nearest  power. */
57				status = "okay";
58			};
59
60			usb3@f8000 {
61				/* CON7 */
62				status = "okay";
63			};
64		};
65
66		pcie {
67			status = "okay";
68			/*
69			 * The two PCIe units are accessible through
70			 * the mini-PCIe connectors on the board.
71			 */
72			pcie@2,0 {
73				/* Port 1, Lane 0. CON3, nearest power. */
74				reset-gpios = <&expander0 1 GPIO_ACTIVE_LOW>;
75				status = "okay";
76			};
77		};
78	};
79
80	sfp: sfp {
81		compatible = "sff,sfp";
82		i2c-bus = <&i2c1>;
83		los-gpio = <&expander0 12 GPIO_ACTIVE_HIGH>;
84		mod-def0-gpio = <&expander0 15 GPIO_ACTIVE_LOW>;
85		tx-disable-gpio = <&expander0 14 GPIO_ACTIVE_HIGH>;
86		tx-fault-gpio = <&expander0 13 GPIO_ACTIVE_HIGH>;
87		maximum-power-milliwatt = <2000>;
88	};
89};
90
91&eth1 {
92	/* ethernet@30000 */
93	bm,pool-long = <2>;
94	bm,pool-short = <1>;
95	buffer-manager = <&bm>;
96	phys = <&comphy1 1>;
97	phy-mode = "sgmii";
98	status = "okay";
99};
100
101&eth2 {
102	/* ethernet@34000 */
103	bm,pool-long = <3>;
104	bm,pool-short = <1>;
105	buffer-manager = <&bm>;
106	managed = "in-band-status";
107	phys = <&comphy5 2>;
108	phy-mode = "sgmii";
109	sfp = <&sfp>;
110	status = "okay";
111};
112
113&i2c0 {
114	clock-frequency = <400000>;
115	pinctrl-0 = <&i2c0_pins>;
116	pinctrl-names = "default";
117	status = "okay";
118
119	/*
120	 * PCA9655 GPIO expander, up to 1MHz clock.
121	 *  0-CON3 CLKREQ#
122	 *  1-CON3 PERST#
123	 *  2-
124	 *  3-CON3 W_DISABLE
125	 *  4-
126	 *  5-USB3 overcurrent
127	 *  6-USB3 power
128	 *  7-
129	 *  8-JP4 P1
130	 *  9-JP4 P4
131	 * 10-JP4 P5
132	 * 11-m.2 DEVSLP
133	 * 12-SFP_LOS
134	 * 13-SFP_TX_FAULT
135	 * 14-SFP_TX_DISABLE
136	 * 15-SFP_MOD_DEF0
137	 */
138	expander0: gpio-expander@20 {
139		/*
140		 * This is how it should be:
141		 * compatible = "onnn,pca9655", "nxp,pca9555";
142		 * but you can't do this because of the way I2C works.
143		 */
144		compatible = "nxp,pca9555";
145		gpio-controller;
146		#gpio-cells = <2>;
147		reg = <0x20>;
148
149		pcie1_0_clkreq {
150			gpio-hog;
151			gpios = <0 GPIO_ACTIVE_LOW>;
152			input;
153			line-name = "pcie1.0-clkreq";
154		};
155		pcie1_0_w_disable {
156			gpio-hog;
157			gpios = <3 GPIO_ACTIVE_LOW>;
158			output-low;
159			line-name = "pcie1.0-w-disable";
160		};
161		usb3_ilimit {
162			gpio-hog;
163			gpios = <5 GPIO_ACTIVE_LOW>;
164			input;
165			line-name = "usb3-current-limit";
166		};
167		usb3_power {
168			gpio-hog;
169			gpios = <6 GPIO_ACTIVE_HIGH>;
170			output-high;
171			line-name = "usb3-power";
172		};
173		m2_devslp {
174			gpio-hog;
175			gpios = <11 GPIO_ACTIVE_HIGH>;
176			output-low;
177			line-name = "m.2 devslp";
178		};
179	};
180
181	/* The MCP3021 supports standard and fast modes */
182	mikrobus_adc: mcp3021@4c {
183		compatible = "microchip,mcp3021";
184		reg = <0x4c>;
185	};
186};
187
188&i2c1 {
189	/*
190	 * Routed to SFP, mikrobus, and PCIe.
191	 * SFP limits this to 100kHz, and requires an AT24C01A/02/04 with
192	 *  address pins tied low, which takes addresses 0x50 and 0x51.
193	 * Mikrobus doesn't specify beyond an I2C bus being present.
194	 * PCIe uses ARP to assign addresses, or 0x63-0x64.
195	 */
196	clock-frequency = <100000>;
197	pinctrl-0 = <&clearfog_i2c1_pins>;
198	pinctrl-names = "default";
199	status = "okay";
200};
201
202&pinctrl {
203	clearfog_i2c1_pins: i2c1-pins {
204		/* SFP, PCIe, mSATA, mikrobus */
205		marvell,pins = "mpp26", "mpp27";
206		marvell,function = "i2c1";
207	};
208	clearfog_sdhci_cd_pins: clearfog-sdhci-cd-pins {
209		marvell,pins = "mpp20";
210		marvell,function = "gpio";
211	};
212	mikro_pins: mikro-pins {
213		/* int: mpp22 rst: mpp29 */
214		marvell,pins = "mpp22", "mpp29";
215		marvell,function = "gpio";
216	};
217	mikro_spi_pins: mikro-spi-pins {
218		marvell,pins = "mpp43";
219		marvell,function = "spi1";
220	};
221	mikro_uart_pins: mikro-uart-pins {
222		marvell,pins = "mpp24", "mpp25";
223		marvell,function = "ua1";
224	};
225};
226
227&spi1 {
228	/*
229	 * Add SPI CS pins for clearfog:
230	 * CS0: W25Q32
231	 * CS1: PIC microcontroller (Pro models)
232	 * CS2: mikrobus
233	 */
234	pinctrl-0 = <&spi1_pins &mikro_spi_pins>;
235	pinctrl-names = "default";
236	status = "okay";
237};
238
239&uart1 {
240	/* mikrobus uart */
241	pinctrl-0 = <&mikro_uart_pins>;
242	pinctrl-names = "default";
243	status = "okay";
244};
245