1/*
2 * Copyright 2016 Linaro Ltd
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a copy
5 * of this software and associated documentation files (the "Software"), to deal
6 * in the Software without restriction, including without limitation the rights
7 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
8 * copies of the Software, and to permit persons to whom the Software is
9 * furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
19 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
20 * THE SOFTWARE.
21 */
22
23#include <dt-bindings/interrupt-controller/irq.h>
24#include <dt-bindings/gpio/gpio.h>
25
26/ {
27	#address-cells = <1>;
28	#size-cells = <1>;
29	compatible = "arm,realview-eb";
30
31	chosen { };
32
33	aliases {
34		serial0 = &serial0;
35		serial1 = &serial1;
36		serial2 = &serial2;
37		serial3 = &serial3;
38		i2c0 = &i2c;
39	};
40
41	memory {
42		device_type = "memory";
43		/* 128 MiB memory @ 0x0 */
44		reg = <0x00000000 0x08000000>;
45	};
46
47	/* The voltage to the MMC card is hardwired at 3.3V */
48	vmmc: fixedregulator@0 {
49		compatible = "regulator-fixed";
50		regulator-name = "vmmc";
51		regulator-min-microvolt = <3300000>;
52		regulator-max-microvolt = <3300000>;
53		regulator-boot-on;
54        };
55
56	xtal24mhz: xtal24mhz@24M {
57		#clock-cells = <0>;
58		compatible = "fixed-clock";
59		clock-frequency = <24000000>;
60	};
61
62	timclk: timclk@1M {
63		#clock-cells = <0>;
64		compatible = "fixed-factor-clock";
65		clock-div = <24>;
66		clock-mult = <1>;
67		clocks = <&xtal24mhz>;
68	};
69
70	mclk: mclk@24M {
71		#clock-cells = <0>;
72		compatible = "fixed-factor-clock";
73		clock-div = <1>;
74		clock-mult = <1>;
75		clocks = <&xtal24mhz>;
76	};
77
78	kmiclk: kmiclk@24M {
79		#clock-cells = <0>;
80		compatible = "fixed-factor-clock";
81		clock-div = <1>;
82		clock-mult = <1>;
83		clocks = <&xtal24mhz>;
84	};
85
86	sspclk: sspclk@24M {
87		#clock-cells = <0>;
88		compatible = "fixed-factor-clock";
89		clock-div = <1>;
90		clock-mult = <1>;
91		clocks = <&xtal24mhz>;
92	};
93
94	uartclk: uartclk@24M {
95		#clock-cells = <0>;
96		compatible = "fixed-factor-clock";
97		clock-div = <1>;
98		clock-mult = <1>;
99		clocks = <&xtal24mhz>;
100	};
101
102	wdogclk: wdogclk@24M {
103		#clock-cells = <0>;
104		compatible = "fixed-factor-clock";
105		clock-div = <1>;
106		clock-mult = <1>;
107		clocks = <&xtal24mhz>;
108	};
109
110	/* FIXME: this actually hangs off the PLL clocks */
111	pclk: pclk@0 {
112		#clock-cells = <0>;
113		compatible = "fixed-clock";
114		clock-frequency = <0>;
115	};
116
117	flash0@40000000 {
118		/* 2 * 32MiB NOR Flash memory */
119		compatible = "arm,versatile-flash", "cfi-flash";
120		reg = <0x40000000 0x04000000>;
121		bank-width = <4>;
122		partitions {
123			compatible = "arm,arm-firmware-suite";
124		};
125	};
126
127	flash1@44000000 {
128		/* 2 * 32MiB NOR Flash memory */
129		compatible = "arm,versatile-flash", "cfi-flash";
130		reg = <0x44000000 0x04000000>;
131		bank-width = <4>;
132		partitions {
133			compatible = "arm,arm-firmware-suite";
134		};
135	};
136
137	/* SMSC LAN91C111 ethernet with PHY and EEPROM */
138	ethernet: ethernet@4e000000 {
139		compatible = "smsc,lan91c111";
140		reg = <0x4e000000 0x10000>;
141		/*
142		 * This means the adapter can be accessed with 8, 16 or
143		 * 32 bit reads/writes.
144		 */
145		reg-io-width = <7>;
146	};
147
148	usb: usb@4f000000 {
149		compatible = "nxp,usb-isp1761";
150		reg = <0x4f000000 0x20000>;
151		port1-otg;
152	};
153
154	bridge {
155		compatible = "ti,ths8134a", "ti,ths8134";
156		#address-cells = <1>;
157		#size-cells = <0>;
158
159		ports {
160			#address-cells = <1>;
161			#size-cells = <0>;
162
163			port@0 {
164				reg = <0>;
165
166				vga_bridge_in: endpoint {
167					remote-endpoint = <&clcd_pads>;
168				};
169			};
170
171			port@1 {
172				reg = <1>;
173
174				vga_bridge_out: endpoint {
175					remote-endpoint = <&vga_con_in>;
176				};
177			};
178		};
179	};
180
181	vga {
182		compatible = "vga-connector";
183
184		port {
185			vga_con_in: endpoint {
186				remote-endpoint = <&vga_bridge_out>;
187			};
188		};
189	};
190
191	/* These peripherals are inside the FPGA */
192	fpga {
193		#address-cells = <1>;
194		#size-cells = <1>;
195		compatible = "simple-bus";
196		ranges;
197
198		syscon: syscon@10000000 {
199			compatible = "arm,realview-eb-syscon", "syscon", "simple-mfd";
200			reg = <0x10000000 0x1000>;
201
202			led@08.0 {
203				compatible = "register-bit-led";
204				offset = <0x08>;
205				mask = <0x01>;
206				label = "versatile:0";
207				linux,default-trigger = "heartbeat";
208				default-state = "on";
209			};
210			led@08.1 {
211				compatible = "register-bit-led";
212				offset = <0x08>;
213				mask = <0x02>;
214				label = "versatile:1";
215				linux,default-trigger = "mmc0";
216				default-state = "off";
217			};
218			led@08.2 {
219				compatible = "register-bit-led";
220				offset = <0x08>;
221				mask = <0x04>;
222				label = "versatile:2";
223				linux,default-trigger = "cpu0";
224				default-state = "off";
225			};
226			led@08.3 {
227				compatible = "register-bit-led";
228				offset = <0x08>;
229				mask = <0x08>;
230				label = "versatile:3";
231				default-state = "off";
232			};
233			led@08.4 {
234				compatible = "register-bit-led";
235				offset = <0x08>;
236				mask = <0x10>;
237				label = "versatile:4";
238				default-state = "off";
239			};
240			led@08.5 {
241				compatible = "register-bit-led";
242				offset = <0x08>;
243				mask = <0x20>;
244				label = "versatile:5";
245				default-state = "off";
246			};
247			led@08.6 {
248				compatible = "register-bit-led";
249				offset = <0x08>;
250				mask = <0x40>;
251				label = "versatile:6";
252				default-state = "off";
253			};
254			led@08.7 {
255				compatible = "register-bit-led";
256				offset = <0x08>;
257				mask = <0x80>;
258				label = "versatile:7";
259				default-state = "off";
260			};
261			oscclk0: osc0@0c {
262				compatible = "arm,syscon-icst307";
263				#clock-cells = <0>;
264				lock-offset = <0x20>;
265				vco-offset = <0x0C>;
266				clocks = <&xtal24mhz>;
267			};
268			oscclk1: osc1@10 {
269				compatible = "arm,syscon-icst307";
270				#clock-cells = <0>;
271				lock-offset = <0x20>;
272				vco-offset = <0x10>;
273				clocks = <&xtal24mhz>;
274			};
275			oscclk2: osc2@14 {
276				compatible = "arm,syscon-icst307";
277				#clock-cells = <0>;
278				lock-offset = <0x20>;
279				vco-offset = <0x14>;
280				clocks = <&xtal24mhz>;
281			};
282			oscclk3: osc3@18 {
283				compatible = "arm,syscon-icst307";
284				#clock-cells = <0>;
285				lock-offset = <0x20>;
286				vco-offset = <0x18>;
287				clocks = <&xtal24mhz>;
288			};
289			oscclk4: osc4@1c {
290				compatible = "arm,syscon-icst307";
291				#clock-cells = <0>;
292				lock-offset = <0x20>;
293				vco-offset = <0x1c>;
294				clocks = <&xtal24mhz>;
295			};
296		};
297
298		i2c: i2c@10002000 {
299			#address-cells = <1>;
300			#size-cells = <0>;
301			compatible = "arm,versatile-i2c";
302			reg = <0x10002000 0x1000>;
303
304			rtc@68 {
305				compatible = "dallas,ds1338";
306				reg = <0x68>;
307			};
308		};
309
310		aaci: aaci@10004000 {
311			compatible = "arm,pl041", "arm,primecell";
312			reg = <0x10004000 0x1000>;
313			clocks = <&pclk>;
314			clock-names = "apb_pclk";
315		};
316
317		mmc: mmcsd@10005000 {
318			compatible = "arm,pl18x", "arm,primecell";
319			reg = <0x10005000 0x1000>;
320
321			/* Due to frequent FIFO overruns, use just 500 kHz */
322			max-frequency = <500000>;
323			bus-width = <4>;
324			cap-sd-highspeed;
325			cap-mmc-highspeed;
326			clocks = <&mclk>, <&pclk>;
327			clock-names = "mclk", "apb_pclk";
328			vmmc-supply = <&vmmc>;
329			cd-gpios = <&gpio1 0 GPIO_ACTIVE_LOW>;
330			wp-gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>;
331		};
332
333		kmi0: kmi@10006000 {
334			compatible = "arm,pl050", "arm,primecell";
335			reg = <0x10006000 0x1000>;
336			clocks = <&kmiclk>, <&pclk>;
337			clock-names = "KMIREFCLK", "apb_pclk";
338		};
339
340		kmi1: kmi@10007000 {
341			compatible = "arm,pl050", "arm,primecell";
342			reg = <0x10007000 0x1000>;
343			clocks = <&kmiclk>, <&pclk>;
344			clock-names = "KMIREFCLK", "apb_pclk";
345		};
346
347		charlcd: fpga_charlcd: charlcd@10008000 {
348			compatible = "arm,versatile-lcd";
349			reg = <0x10008000 0x1000>;
350			clocks = <&pclk>;
351			clock-names = "apb_pclk";
352		};
353
354		serial0: serial@10009000 {
355			compatible = "arm,pl011", "arm,primecell";
356			reg = <0x10009000 0x1000>;
357			clocks = <&uartclk>, <&pclk>;
358			clock-names = "uartclk", "apb_pclk";
359		};
360
361		serial1: serial@1000a000 {
362			compatible = "arm,pl011", "arm,primecell";
363			reg = <0x1000a000 0x1000>;
364			clocks = <&uartclk>, <&pclk>;
365			clock-names = "uartclk", "apb_pclk";
366		};
367
368		serial2: serial@1000b000 {
369			compatible = "arm,pl011", "arm,primecell";
370			reg = <0x1000b000 0x1000>;
371			clocks = <&uartclk>, <&pclk>;
372			clock-names = "uartclk", "apb_pclk";
373		};
374
375		serial3: serial@1000c000 {
376			compatible = "arm,pl011", "arm,primecell";
377			reg = <0x1000c000 0x1000>;
378			clocks = <&uartclk>, <&pclk>;
379			clock-names = "uartclk", "apb_pclk";
380		};
381
382		ssp: spi@1000d000 {
383			compatible = "arm,pl022", "arm,primecell";
384			reg = <0x1000d000 0x1000>;
385			clocks = <&sspclk>, <&pclk>;
386			clock-names = "SSPCLK", "apb_pclk";
387		};
388
389		wdog: watchdog@10010000 {
390			compatible = "arm,sp805", "arm,primecell";
391			reg = <0x10010000 0x1000>;
392			clocks = <&wdogclk>, <&pclk>;
393			clock-names = "wdog_clk", "apb_pclk";
394			status = "disabled";
395		};
396
397		timer01: timer@10011000 {
398			compatible = "arm,sp804", "arm,primecell";
399			reg = <0x10011000 0x1000>;
400			clocks = <&timclk>, <&timclk>, <&pclk>;
401			clock-names = "timer1", "timer2", "apb_pclk";
402		};
403
404		timer23: timer@10012000 {
405			compatible = "arm,sp804", "arm,primecell";
406			reg = <0x10012000 0x1000>;
407			clocks = <&timclk>, <&timclk>, <&pclk>;
408			clock-names = "timer1", "timer2", "apb_pclk";
409		};
410
411		gpio0: gpio@10013000 {
412			compatible = "arm,pl061", "arm,primecell";
413			reg = <0x10013000 0x1000>;
414			gpio-controller;
415			#gpio-cells = <2>;
416			interrupt-controller;
417			#interrupt-cells = <2>;
418			clocks = <&pclk>;
419			clock-names = "apb_pclk";
420		};
421
422		gpio1: gpio@10014000 {
423			compatible = "arm,pl061", "arm,primecell";
424			reg = <0x10014000 0x1000>;
425			gpio-controller;
426			#gpio-cells = <2>;
427			interrupt-controller;
428			#interrupt-cells = <2>;
429			clocks = <&pclk>;
430			clock-names = "apb_pclk";
431		};
432
433		gpio2: gpio@10015000 {
434			compatible = "arm,pl061", "arm,primecell";
435			reg = <0x10015000 0x1000>;
436			gpio-controller;
437			#gpio-cells = <2>;
438			interrupt-controller;
439			#interrupt-cells = <2>;
440			clocks = <&pclk>;
441			clock-names = "apb_pclk";
442		};
443
444		rtc: rtc@10017000 {
445			compatible = "arm,pl031", "arm,primecell";
446			reg = <0x10017000 0x1000>;
447			clocks = <&pclk>;
448			clock-names = "apb_pclk";
449		};
450
451		clcd: clcd@10020000 {
452			compatible = "arm,pl111", "arm,primecell";
453			reg = <0x10020000 0x1000>;
454			interrupt-names = "combined";
455			clocks = <&oscclk0>, <&pclk>;
456			clock-names = "clcdclk", "apb_pclk";
457			/* 1024x768 16bpp @65MHz works fine */
458			max-memory-bandwidth = <95000000>;
459
460			port {
461				clcd_pads: endpoint {
462					remote-endpoint = <&vga_bridge_in>;
463					arm,pl11x,tft-r0g0b0-pads = <0 8 16>;
464				};
465			};
466		};
467	};
468};
469