1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  * Hygon Processor Support for Linux
4  *
5  * Copyright (C) 2018 Chengdu Haiguang IC Design Co., Ltd.
6  *
7  * Author: Pu Wen <puwen@hygon.cn>
8  */
9 #include <linux/io.h>
10 
11 #include <asm/cpu.h>
12 #include <asm/smp.h>
13 #include <asm/cacheinfo.h>
14 #include <asm/spec-ctrl.h>
15 #include <asm/delay.h>
16 #ifdef CONFIG_X86_64
17 # include <asm/set_memory.h>
18 #endif
19 
20 #include "cpu.h"
21 
22 #define APICID_SOCKET_ID_BIT 6
23 
24 /*
25  * nodes_per_socket: Stores the number of nodes per socket.
26  * Refer to CPUID Fn8000_001E_ECX Node Identifiers[10:8]
27  */
28 static u32 nodes_per_socket = 1;
29 
30 #ifdef CONFIG_NUMA
31 /*
32  * To workaround broken NUMA config.  Read the comment in
33  * srat_detect_node().
34  */
nearby_node(int apicid)35 static int nearby_node(int apicid)
36 {
37 	int i, node;
38 
39 	for (i = apicid - 1; i >= 0; i--) {
40 		node = __apicid_to_node[i];
41 		if (node != NUMA_NO_NODE && node_online(node))
42 			return node;
43 	}
44 	for (i = apicid + 1; i < MAX_LOCAL_APIC; i++) {
45 		node = __apicid_to_node[i];
46 		if (node != NUMA_NO_NODE && node_online(node))
47 			return node;
48 	}
49 	return first_node(node_online_map); /* Shouldn't happen */
50 }
51 #endif
52 
hygon_get_topology_early(struct cpuinfo_x86 * c)53 static void hygon_get_topology_early(struct cpuinfo_x86 *c)
54 {
55 	if (cpu_has(c, X86_FEATURE_TOPOEXT))
56 		smp_num_siblings = ((cpuid_ebx(0x8000001e) >> 8) & 0xff) + 1;
57 }
58 
59 /*
60  * Fixup core topology information for
61  * (1) Hygon multi-node processors
62  *     Assumption: Number of cores in each internal node is the same.
63  * (2) Hygon processors supporting compute units
64  */
hygon_get_topology(struct cpuinfo_x86 * c)65 static void hygon_get_topology(struct cpuinfo_x86 *c)
66 {
67 	u8 node_id;
68 	int cpu = smp_processor_id();
69 
70 	/* get information required for multi-node processors */
71 	if (boot_cpu_has(X86_FEATURE_TOPOEXT)) {
72 		int err;
73 		u32 eax, ebx, ecx, edx;
74 
75 		cpuid(0x8000001e, &eax, &ebx, &ecx, &edx);
76 
77 		node_id  = ecx & 0xff;
78 
79 		c->cpu_core_id = ebx & 0xff;
80 
81 		if (smp_num_siblings > 1)
82 			c->x86_max_cores /= smp_num_siblings;
83 
84 		/*
85 		 * In case leaf B is available, use it to derive
86 		 * topology information.
87 		 */
88 		err = detect_extended_topology(c);
89 		if (!err)
90 			c->x86_coreid_bits = get_count_order(c->x86_max_cores);
91 
92 		/* Socket ID is ApicId[6] for these processors. */
93 		c->phys_proc_id = c->apicid >> APICID_SOCKET_ID_BIT;
94 
95 		cacheinfo_hygon_init_llc_id(c, cpu, node_id);
96 	} else if (cpu_has(c, X86_FEATURE_NODEID_MSR)) {
97 		u64 value;
98 
99 		rdmsrl(MSR_FAM10H_NODE_ID, value);
100 		node_id = value & 7;
101 
102 		per_cpu(cpu_llc_id, cpu) = node_id;
103 	} else
104 		return;
105 
106 	if (nodes_per_socket > 1)
107 		set_cpu_cap(c, X86_FEATURE_AMD_DCM);
108 }
109 
110 /*
111  * On Hygon setup the lower bits of the APIC id distinguish the cores.
112  * Assumes number of cores is a power of two.
113  */
hygon_detect_cmp(struct cpuinfo_x86 * c)114 static void hygon_detect_cmp(struct cpuinfo_x86 *c)
115 {
116 	unsigned int bits;
117 	int cpu = smp_processor_id();
118 
119 	bits = c->x86_coreid_bits;
120 	/* Low order bits define the core id (index of core in socket) */
121 	c->cpu_core_id = c->initial_apicid & ((1 << bits)-1);
122 	/* Convert the initial APIC ID into the socket ID */
123 	c->phys_proc_id = c->initial_apicid >> bits;
124 	/* use socket ID also for last level cache */
125 	per_cpu(cpu_llc_id, cpu) = c->phys_proc_id;
126 }
127 
srat_detect_node(struct cpuinfo_x86 * c)128 static void srat_detect_node(struct cpuinfo_x86 *c)
129 {
130 #ifdef CONFIG_NUMA
131 	int cpu = smp_processor_id();
132 	int node;
133 	unsigned int apicid = c->apicid;
134 
135 	node = numa_cpu_node(cpu);
136 	if (node == NUMA_NO_NODE)
137 		node = per_cpu(cpu_llc_id, cpu);
138 
139 	/*
140 	 * On multi-fabric platform (e.g. Numascale NumaChip) a
141 	 * platform-specific handler needs to be called to fixup some
142 	 * IDs of the CPU.
143 	 */
144 	if (x86_cpuinit.fixup_cpu_id)
145 		x86_cpuinit.fixup_cpu_id(c, node);
146 
147 	if (!node_online(node)) {
148 		/*
149 		 * Two possibilities here:
150 		 *
151 		 * - The CPU is missing memory and no node was created.  In
152 		 *   that case try picking one from a nearby CPU.
153 		 *
154 		 * - The APIC IDs differ from the HyperTransport node IDs.
155 		 *   Assume they are all increased by a constant offset, but
156 		 *   in the same order as the HT nodeids.  If that doesn't
157 		 *   result in a usable node fall back to the path for the
158 		 *   previous case.
159 		 *
160 		 * This workaround operates directly on the mapping between
161 		 * APIC ID and NUMA node, assuming certain relationship
162 		 * between APIC ID, HT node ID and NUMA topology.  As going
163 		 * through CPU mapping may alter the outcome, directly
164 		 * access __apicid_to_node[].
165 		 */
166 		int ht_nodeid = c->initial_apicid;
167 
168 		if (__apicid_to_node[ht_nodeid] != NUMA_NO_NODE)
169 			node = __apicid_to_node[ht_nodeid];
170 		/* Pick a nearby node */
171 		if (!node_online(node))
172 			node = nearby_node(apicid);
173 	}
174 	numa_set_node(cpu, node);
175 #endif
176 }
177 
early_init_hygon_mc(struct cpuinfo_x86 * c)178 static void early_init_hygon_mc(struct cpuinfo_x86 *c)
179 {
180 #ifdef CONFIG_SMP
181 	unsigned int bits, ecx;
182 
183 	/* Multi core CPU? */
184 	if (c->extended_cpuid_level < 0x80000008)
185 		return;
186 
187 	ecx = cpuid_ecx(0x80000008);
188 
189 	c->x86_max_cores = (ecx & 0xff) + 1;
190 
191 	/* CPU telling us the core id bits shift? */
192 	bits = (ecx >> 12) & 0xF;
193 
194 	/* Otherwise recompute */
195 	if (bits == 0) {
196 		while ((1 << bits) < c->x86_max_cores)
197 			bits++;
198 	}
199 
200 	c->x86_coreid_bits = bits;
201 #endif
202 }
203 
bsp_init_hygon(struct cpuinfo_x86 * c)204 static void bsp_init_hygon(struct cpuinfo_x86 *c)
205 {
206 #ifdef CONFIG_X86_64
207 	unsigned long long tseg;
208 
209 	/*
210 	 * Split up direct mapping around the TSEG SMM area.
211 	 * Don't do it for gbpages because there seems very little
212 	 * benefit in doing so.
213 	 */
214 	if (!rdmsrl_safe(MSR_K8_TSEG_ADDR, &tseg)) {
215 		unsigned long pfn = tseg >> PAGE_SHIFT;
216 
217 		pr_debug("tseg: %010llx\n", tseg);
218 		if (pfn_range_is_mapped(pfn, pfn + 1))
219 			set_memory_4k((unsigned long)__va(tseg), 1);
220 	}
221 #endif
222 
223 	if (cpu_has(c, X86_FEATURE_CONSTANT_TSC)) {
224 		u64 val;
225 
226 		rdmsrl(MSR_K7_HWCR, val);
227 		if (!(val & BIT(24)))
228 			pr_warn(FW_BUG "TSC doesn't count with P0 frequency!\n");
229 	}
230 
231 	if (cpu_has(c, X86_FEATURE_MWAITX))
232 		use_mwaitx_delay();
233 
234 	if (boot_cpu_has(X86_FEATURE_TOPOEXT)) {
235 		u32 ecx;
236 
237 		ecx = cpuid_ecx(0x8000001e);
238 		nodes_per_socket = ((ecx >> 8) & 7) + 1;
239 	} else if (boot_cpu_has(X86_FEATURE_NODEID_MSR)) {
240 		u64 value;
241 
242 		rdmsrl(MSR_FAM10H_NODE_ID, value);
243 		nodes_per_socket = ((value >> 3) & 7) + 1;
244 	}
245 
246 	if (!boot_cpu_has(X86_FEATURE_AMD_SSBD) &&
247 	    !boot_cpu_has(X86_FEATURE_VIRT_SSBD)) {
248 		/*
249 		 * Try to cache the base value so further operations can
250 		 * avoid RMW. If that faults, do not enable SSBD.
251 		 */
252 		if (!rdmsrl_safe(MSR_AMD64_LS_CFG, &x86_amd_ls_cfg_base)) {
253 			setup_force_cpu_cap(X86_FEATURE_LS_CFG_SSBD);
254 			setup_force_cpu_cap(X86_FEATURE_SSBD);
255 			x86_amd_ls_cfg_ssbd_mask = 1ULL << 10;
256 		}
257 	}
258 }
259 
early_init_hygon(struct cpuinfo_x86 * c)260 static void early_init_hygon(struct cpuinfo_x86 *c)
261 {
262 	u32 dummy;
263 
264 	early_init_hygon_mc(c);
265 
266 	set_cpu_cap(c, X86_FEATURE_K8);
267 
268 	rdmsr_safe(MSR_AMD64_PATCH_LEVEL, &c->microcode, &dummy);
269 
270 	/*
271 	 * c->x86_power is 8000_0007 edx. Bit 8 is TSC runs at constant rate
272 	 * with P/T states and does not stop in deep C-states
273 	 */
274 	if (c->x86_power & (1 << 8)) {
275 		set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
276 		set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC);
277 	}
278 
279 	/* Bit 12 of 8000_0007 edx is accumulated power mechanism. */
280 	if (c->x86_power & BIT(12))
281 		set_cpu_cap(c, X86_FEATURE_ACC_POWER);
282 
283 #ifdef CONFIG_X86_64
284 	set_cpu_cap(c, X86_FEATURE_SYSCALL32);
285 #endif
286 
287 #if defined(CONFIG_X86_LOCAL_APIC) && defined(CONFIG_PCI)
288 	/*
289 	 * ApicID can always be treated as an 8-bit value for Hygon APIC So, we
290 	 * can safely set X86_FEATURE_EXTD_APICID unconditionally.
291 	 */
292 	if (boot_cpu_has(X86_FEATURE_APIC))
293 		set_cpu_cap(c, X86_FEATURE_EXTD_APICID);
294 #endif
295 
296 	/*
297 	 * This is only needed to tell the kernel whether to use VMCALL
298 	 * and VMMCALL.  VMMCALL is never executed except under virt, so
299 	 * we can set it unconditionally.
300 	 */
301 	set_cpu_cap(c, X86_FEATURE_VMMCALL);
302 
303 	hygon_get_topology_early(c);
304 }
305 
init_hygon(struct cpuinfo_x86 * c)306 static void init_hygon(struct cpuinfo_x86 *c)
307 {
308 	early_init_hygon(c);
309 
310 	/*
311 	 * Bit 31 in normal CPUID used for nonstandard 3DNow ID;
312 	 * 3DNow is IDd by bit 31 in extended CPUID (1*32+31) anyway
313 	 */
314 	clear_cpu_cap(c, 0*32+31);
315 
316 	set_cpu_cap(c, X86_FEATURE_REP_GOOD);
317 
318 	/* get apicid instead of initial apic id from cpuid */
319 	c->apicid = hard_smp_processor_id();
320 
321 	set_cpu_cap(c, X86_FEATURE_ZEN);
322 	set_cpu_cap(c, X86_FEATURE_CPB);
323 
324 	cpu_detect_cache_sizes(c);
325 
326 	hygon_detect_cmp(c);
327 	hygon_get_topology(c);
328 	srat_detect_node(c);
329 
330 	init_hygon_cacheinfo(c);
331 
332 	if (cpu_has(c, X86_FEATURE_XMM2)) {
333 		/*
334 		 * Use LFENCE for execution serialization.  On families which
335 		 * don't have that MSR, LFENCE is already serializing.
336 		 * msr_set_bit() uses the safe accessors, too, even if the MSR
337 		 * is not present.
338 		 */
339 		msr_set_bit(MSR_F10H_DECFG,
340 			    MSR_F10H_DECFG_LFENCE_SERIALIZE_BIT);
341 
342 		/* A serializing LFENCE stops RDTSC speculation */
343 		set_cpu_cap(c, X86_FEATURE_LFENCE_RDTSC);
344 	}
345 
346 	/*
347 	 * Hygon processors have APIC timer running in deep C states.
348 	 */
349 	set_cpu_cap(c, X86_FEATURE_ARAT);
350 
351 	/* Hygon CPUs don't reset SS attributes on SYSRET, Xen does. */
352 	if (!cpu_has(c, X86_FEATURE_XENPV))
353 		set_cpu_bug(c, X86_BUG_SYSRET_SS_ATTRS);
354 }
355 
cpu_detect_tlb_hygon(struct cpuinfo_x86 * c)356 static void cpu_detect_tlb_hygon(struct cpuinfo_x86 *c)
357 {
358 	u32 ebx, eax, ecx, edx;
359 	u16 mask = 0xfff;
360 
361 	if (c->extended_cpuid_level < 0x80000006)
362 		return;
363 
364 	cpuid(0x80000006, &eax, &ebx, &ecx, &edx);
365 
366 	tlb_lld_4k[ENTRIES] = (ebx >> 16) & mask;
367 	tlb_lli_4k[ENTRIES] = ebx & mask;
368 
369 	/* Handle DTLB 2M and 4M sizes, fall back to L1 if L2 is disabled */
370 	if (!((eax >> 16) & mask))
371 		tlb_lld_2m[ENTRIES] = (cpuid_eax(0x80000005) >> 16) & 0xff;
372 	else
373 		tlb_lld_2m[ENTRIES] = (eax >> 16) & mask;
374 
375 	/* a 4M entry uses two 2M entries */
376 	tlb_lld_4m[ENTRIES] = tlb_lld_2m[ENTRIES] >> 1;
377 
378 	/* Handle ITLB 2M and 4M sizes, fall back to L1 if L2 is disabled */
379 	if (!(eax & mask)) {
380 		cpuid(0x80000005, &eax, &ebx, &ecx, &edx);
381 		tlb_lli_2m[ENTRIES] = eax & 0xff;
382 	} else
383 		tlb_lli_2m[ENTRIES] = eax & mask;
384 
385 	tlb_lli_4m[ENTRIES] = tlb_lli_2m[ENTRIES] >> 1;
386 }
387 
388 static const struct cpu_dev hygon_cpu_dev = {
389 	.c_vendor	= "Hygon",
390 	.c_ident	= { "HygonGenuine" },
391 	.c_early_init   = early_init_hygon,
392 	.c_detect_tlb	= cpu_detect_tlb_hygon,
393 	.c_bsp_init	= bsp_init_hygon,
394 	.c_init		= init_hygon,
395 	.c_x86_vendor	= X86_VENDOR_HYGON,
396 };
397 
398 cpu_dev_register(hygon_cpu_dev);
399