1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ 2 3 /* 4 * This file contains definitions from Hyper-V Hypervisor Top-Level Functional 5 * Specification (TLFS): 6 * https://docs.microsoft.com/en-us/virtualization/hyper-v-on-windows/reference/tlfs 7 */ 8 9 #ifndef _ASM_X86_HYPERV_TLFS_H 10 #define _ASM_X86_HYPERV_TLFS_H 11 12 #include <linux/types.h> 13 14 /* 15 * The below CPUID leaves are present if VersionAndFeatures.HypervisorPresent 16 * is set by CPUID(HvCpuIdFunctionVersionAndFeatures). 17 */ 18 #define HYPERV_CPUID_VENDOR_AND_MAX_FUNCTIONS 0x40000000 19 #define HYPERV_CPUID_INTERFACE 0x40000001 20 #define HYPERV_CPUID_VERSION 0x40000002 21 #define HYPERV_CPUID_FEATURES 0x40000003 22 #define HYPERV_CPUID_ENLIGHTMENT_INFO 0x40000004 23 #define HYPERV_CPUID_IMPLEMENT_LIMITS 0x40000005 24 #define HYPERV_CPUID_NESTED_FEATURES 0x4000000A 25 26 #define HYPERV_HYPERVISOR_PRESENT_BIT 0x80000000 27 #define HYPERV_CPUID_MIN 0x40000005 28 #define HYPERV_CPUID_MAX 0x4000ffff 29 30 /* 31 * Feature identification. EAX indicates which features are available 32 * to the partition based upon the current partition privileges. 33 */ 34 35 /* VP Runtime (HV_X64_MSR_VP_RUNTIME) available */ 36 #define HV_X64_MSR_VP_RUNTIME_AVAILABLE (1 << 0) 37 /* Partition Reference Counter (HV_X64_MSR_TIME_REF_COUNT) available*/ 38 #define HV_MSR_TIME_REF_COUNT_AVAILABLE (1 << 1) 39 /* Partition reference TSC MSR is available */ 40 #define HV_MSR_REFERENCE_TSC_AVAILABLE (1 << 9) 41 42 /* A partition's reference time stamp counter (TSC) page */ 43 #define HV_X64_MSR_REFERENCE_TSC 0x40000021 44 45 /* 46 * There is a single feature flag that signifies if the partition has access 47 * to MSRs with local APIC and TSC frequencies. 48 */ 49 #define HV_X64_ACCESS_FREQUENCY_MSRS (1 << 11) 50 51 /* AccessReenlightenmentControls privilege */ 52 #define HV_X64_ACCESS_REENLIGHTENMENT BIT(13) 53 54 /* 55 * Basic SynIC MSRs (HV_X64_MSR_SCONTROL through HV_X64_MSR_EOM 56 * and HV_X64_MSR_SINT0 through HV_X64_MSR_SINT15) available 57 */ 58 #define HV_X64_MSR_SYNIC_AVAILABLE (1 << 2) 59 /* 60 * Synthetic Timer MSRs (HV_X64_MSR_STIMER0_CONFIG through 61 * HV_X64_MSR_STIMER3_COUNT) available 62 */ 63 #define HV_MSR_SYNTIMER_AVAILABLE (1 << 3) 64 /* 65 * APIC access MSRs (HV_X64_MSR_EOI, HV_X64_MSR_ICR and HV_X64_MSR_TPR) 66 * are available 67 */ 68 #define HV_X64_MSR_APIC_ACCESS_AVAILABLE (1 << 4) 69 /* Hypercall MSRs (HV_X64_MSR_GUEST_OS_ID and HV_X64_MSR_HYPERCALL) available*/ 70 #define HV_X64_MSR_HYPERCALL_AVAILABLE (1 << 5) 71 /* Access virtual processor index MSR (HV_X64_MSR_VP_INDEX) available*/ 72 #define HV_X64_MSR_VP_INDEX_AVAILABLE (1 << 6) 73 /* Virtual system reset MSR (HV_X64_MSR_RESET) is available*/ 74 #define HV_X64_MSR_RESET_AVAILABLE (1 << 7) 75 /* 76 * Access statistics pages MSRs (HV_X64_MSR_STATS_PARTITION_RETAIL_PAGE, 77 * HV_X64_MSR_STATS_PARTITION_INTERNAL_PAGE, HV_X64_MSR_STATS_VP_RETAIL_PAGE, 78 * HV_X64_MSR_STATS_VP_INTERNAL_PAGE) available 79 */ 80 #define HV_X64_MSR_STAT_PAGES_AVAILABLE (1 << 8) 81 82 /* Frequency MSRs available */ 83 #define HV_FEATURE_FREQUENCY_MSRS_AVAILABLE (1 << 8) 84 85 /* Crash MSR available */ 86 #define HV_FEATURE_GUEST_CRASH_MSR_AVAILABLE (1 << 10) 87 88 /* stimer Direct Mode is available */ 89 #define HV_STIMER_DIRECT_MODE_AVAILABLE (1 << 19) 90 91 /* 92 * Feature identification: EBX indicates which flags were specified at 93 * partition creation. The format is the same as the partition creation 94 * flag structure defined in section Partition Creation Flags. 95 */ 96 #define HV_X64_CREATE_PARTITIONS (1 << 0) 97 #define HV_X64_ACCESS_PARTITION_ID (1 << 1) 98 #define HV_X64_ACCESS_MEMORY_POOL (1 << 2) 99 #define HV_X64_ADJUST_MESSAGE_BUFFERS (1 << 3) 100 #define HV_X64_POST_MESSAGES (1 << 4) 101 #define HV_X64_SIGNAL_EVENTS (1 << 5) 102 #define HV_X64_CREATE_PORT (1 << 6) 103 #define HV_X64_CONNECT_PORT (1 << 7) 104 #define HV_X64_ACCESS_STATS (1 << 8) 105 #define HV_X64_DEBUGGING (1 << 11) 106 #define HV_X64_CPU_POWER_MANAGEMENT (1 << 12) 107 #define HV_X64_CONFIGURE_PROFILER (1 << 13) 108 109 /* 110 * Feature identification. EDX indicates which miscellaneous features 111 * are available to the partition. 112 */ 113 /* The MWAIT instruction is available (per section MONITOR / MWAIT) */ 114 #define HV_X64_MWAIT_AVAILABLE (1 << 0) 115 /* Guest debugging support is available */ 116 #define HV_X64_GUEST_DEBUGGING_AVAILABLE (1 << 1) 117 /* Performance Monitor support is available*/ 118 #define HV_X64_PERF_MONITOR_AVAILABLE (1 << 2) 119 /* Support for physical CPU dynamic partitioning events is available*/ 120 #define HV_X64_CPU_DYNAMIC_PARTITIONING_AVAILABLE (1 << 3) 121 /* 122 * Support for passing hypercall input parameter block via XMM 123 * registers is available 124 */ 125 #define HV_X64_HYPERCALL_PARAMS_XMM_AVAILABLE (1 << 4) 126 /* Support for a virtual guest idle state is available */ 127 #define HV_X64_GUEST_IDLE_STATE_AVAILABLE (1 << 5) 128 /* Guest crash data handler available */ 129 #define HV_X64_GUEST_CRASH_MSR_AVAILABLE (1 << 10) 130 131 /* 132 * Implementation recommendations. Indicates which behaviors the hypervisor 133 * recommends the OS implement for optimal performance. 134 */ 135 /* 136 * Recommend using hypercall for address space switches rather 137 * than MOV to CR3 instruction 138 */ 139 #define HV_X64_AS_SWITCH_RECOMMENDED (1 << 0) 140 /* Recommend using hypercall for local TLB flushes rather 141 * than INVLPG or MOV to CR3 instructions */ 142 #define HV_X64_LOCAL_TLB_FLUSH_RECOMMENDED (1 << 1) 143 /* 144 * Recommend using hypercall for remote TLB flushes rather 145 * than inter-processor interrupts 146 */ 147 #define HV_X64_REMOTE_TLB_FLUSH_RECOMMENDED (1 << 2) 148 /* 149 * Recommend using MSRs for accessing APIC registers 150 * EOI, ICR and TPR rather than their memory-mapped counterparts 151 */ 152 #define HV_X64_APIC_ACCESS_RECOMMENDED (1 << 3) 153 /* Recommend using the hypervisor-provided MSR to initiate a system RESET */ 154 #define HV_X64_SYSTEM_RESET_RECOMMENDED (1 << 4) 155 /* 156 * Recommend using relaxed timing for this partition. If used, 157 * the VM should disable any watchdog timeouts that rely on the 158 * timely delivery of external interrupts 159 */ 160 #define HV_X64_RELAXED_TIMING_RECOMMENDED (1 << 5) 161 162 /* 163 * Recommend not using Auto End-Of-Interrupt feature 164 */ 165 #define HV_DEPRECATING_AEOI_RECOMMENDED (1 << 9) 166 167 /* 168 * Recommend using cluster IPI hypercalls. 169 */ 170 #define HV_X64_CLUSTER_IPI_RECOMMENDED (1 << 10) 171 172 /* Recommend using the newer ExProcessorMasks interface */ 173 #define HV_X64_EX_PROCESSOR_MASKS_RECOMMENDED (1 << 11) 174 175 /* Recommend using enlightened VMCS */ 176 #define HV_X64_ENLIGHTENED_VMCS_RECOMMENDED (1 << 14) 177 178 /* 179 * Crash notification flags. 180 */ 181 #define HV_CRASH_CTL_CRASH_NOTIFY_MSG BIT_ULL(62) 182 #define HV_CRASH_CTL_CRASH_NOTIFY BIT_ULL(63) 183 184 /* MSR used to identify the guest OS. */ 185 #define HV_X64_MSR_GUEST_OS_ID 0x40000000 186 187 /* MSR used to setup pages used to communicate with the hypervisor. */ 188 #define HV_X64_MSR_HYPERCALL 0x40000001 189 190 /* MSR used to provide vcpu index */ 191 #define HV_X64_MSR_VP_INDEX 0x40000002 192 193 /* MSR used to reset the guest OS. */ 194 #define HV_X64_MSR_RESET 0x40000003 195 196 /* MSR used to provide vcpu runtime in 100ns units */ 197 #define HV_X64_MSR_VP_RUNTIME 0x40000010 198 199 /* MSR used to read the per-partition time reference counter */ 200 #define HV_X64_MSR_TIME_REF_COUNT 0x40000020 201 202 /* MSR used to retrieve the TSC frequency */ 203 #define HV_X64_MSR_TSC_FREQUENCY 0x40000022 204 205 /* MSR used to retrieve the local APIC timer frequency */ 206 #define HV_X64_MSR_APIC_FREQUENCY 0x40000023 207 208 /* Define the virtual APIC registers */ 209 #define HV_X64_MSR_EOI 0x40000070 210 #define HV_X64_MSR_ICR 0x40000071 211 #define HV_X64_MSR_TPR 0x40000072 212 #define HV_X64_MSR_VP_ASSIST_PAGE 0x40000073 213 214 /* Define synthetic interrupt controller model specific registers. */ 215 #define HV_X64_MSR_SCONTROL 0x40000080 216 #define HV_X64_MSR_SVERSION 0x40000081 217 #define HV_X64_MSR_SIEFP 0x40000082 218 #define HV_X64_MSR_SIMP 0x40000083 219 #define HV_X64_MSR_EOM 0x40000084 220 #define HV_X64_MSR_SINT0 0x40000090 221 #define HV_X64_MSR_SINT1 0x40000091 222 #define HV_X64_MSR_SINT2 0x40000092 223 #define HV_X64_MSR_SINT3 0x40000093 224 #define HV_X64_MSR_SINT4 0x40000094 225 #define HV_X64_MSR_SINT5 0x40000095 226 #define HV_X64_MSR_SINT6 0x40000096 227 #define HV_X64_MSR_SINT7 0x40000097 228 #define HV_X64_MSR_SINT8 0x40000098 229 #define HV_X64_MSR_SINT9 0x40000099 230 #define HV_X64_MSR_SINT10 0x4000009A 231 #define HV_X64_MSR_SINT11 0x4000009B 232 #define HV_X64_MSR_SINT12 0x4000009C 233 #define HV_X64_MSR_SINT13 0x4000009D 234 #define HV_X64_MSR_SINT14 0x4000009E 235 #define HV_X64_MSR_SINT15 0x4000009F 236 237 /* 238 * Synthetic Timer MSRs. Four timers per vcpu. 239 */ 240 #define HV_X64_MSR_STIMER0_CONFIG 0x400000B0 241 #define HV_X64_MSR_STIMER0_COUNT 0x400000B1 242 #define HV_X64_MSR_STIMER1_CONFIG 0x400000B2 243 #define HV_X64_MSR_STIMER1_COUNT 0x400000B3 244 #define HV_X64_MSR_STIMER2_CONFIG 0x400000B4 245 #define HV_X64_MSR_STIMER2_COUNT 0x400000B5 246 #define HV_X64_MSR_STIMER3_CONFIG 0x400000B6 247 #define HV_X64_MSR_STIMER3_COUNT 0x400000B7 248 249 /* Hyper-V guest crash notification MSR's */ 250 #define HV_X64_MSR_CRASH_P0 0x40000100 251 #define HV_X64_MSR_CRASH_P1 0x40000101 252 #define HV_X64_MSR_CRASH_P2 0x40000102 253 #define HV_X64_MSR_CRASH_P3 0x40000103 254 #define HV_X64_MSR_CRASH_P4 0x40000104 255 #define HV_X64_MSR_CRASH_CTL 0x40000105 256 #define HV_X64_MSR_CRASH_CTL_NOTIFY (1ULL << 63) 257 #define HV_X64_MSR_CRASH_PARAMS \ 258 (1 + (HV_X64_MSR_CRASH_P4 - HV_X64_MSR_CRASH_P0)) 259 260 /* 261 * Declare the MSR used to setup pages used to communicate with the hypervisor. 262 */ 263 union hv_x64_msr_hypercall_contents { 264 u64 as_uint64; 265 struct { 266 u64 enable:1; 267 u64 reserved:11; 268 u64 guest_physical_address:52; 269 }; 270 }; 271 272 /* 273 * TSC page layout. 274 */ 275 struct ms_hyperv_tsc_page { 276 volatile u32 tsc_sequence; 277 u32 reserved1; 278 volatile u64 tsc_scale; 279 volatile s64 tsc_offset; 280 u64 reserved2[509]; 281 }; 282 283 /* 284 * The guest OS needs to register the guest ID with the hypervisor. 285 * The guest ID is a 64 bit entity and the structure of this ID is 286 * specified in the Hyper-V specification: 287 * 288 * msdn.microsoft.com/en-us/library/windows/hardware/ff542653%28v=vs.85%29.aspx 289 * 290 * While the current guideline does not specify how Linux guest ID(s) 291 * need to be generated, our plan is to publish the guidelines for 292 * Linux and other guest operating systems that currently are hosted 293 * on Hyper-V. The implementation here conforms to this yet 294 * unpublished guidelines. 295 * 296 * 297 * Bit(s) 298 * 63 - Indicates if the OS is Open Source or not; 1 is Open Source 299 * 62:56 - Os Type; Linux is 0x100 300 * 55:48 - Distro specific identification 301 * 47:16 - Linux kernel version number 302 * 15:0 - Distro specific identification 303 * 304 * 305 */ 306 307 #define HV_LINUX_VENDOR_ID 0x8100 308 309 /* TSC emulation after migration */ 310 #define HV_X64_MSR_REENLIGHTENMENT_CONTROL 0x40000106 311 312 /* Nested features (CPUID 0x4000000A) EAX */ 313 #define HV_X64_NESTED_GUEST_MAPPING_FLUSH BIT(18) 314 #define HV_X64_NESTED_MSR_BITMAP BIT(19) 315 316 struct hv_reenlightenment_control { 317 __u64 vector:8; 318 __u64 reserved1:8; 319 __u64 enabled:1; 320 __u64 reserved2:15; 321 __u64 target_vp:32; 322 }; 323 324 #define HV_X64_MSR_TSC_EMULATION_CONTROL 0x40000107 325 #define HV_X64_MSR_TSC_EMULATION_STATUS 0x40000108 326 327 struct hv_tsc_emulation_control { 328 __u64 enabled:1; 329 __u64 reserved:63; 330 }; 331 332 struct hv_tsc_emulation_status { 333 __u64 inprogress:1; 334 __u64 reserved:63; 335 }; 336 337 #define HV_X64_MSR_HYPERCALL_ENABLE 0x00000001 338 #define HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT 12 339 #define HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_MASK \ 340 (~((1ull << HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT) - 1)) 341 342 #define HV_IPI_LOW_VECTOR 0x10 343 #define HV_IPI_HIGH_VECTOR 0xff 344 345 /* Declare the various hypercall operations. */ 346 #define HVCALL_FLUSH_VIRTUAL_ADDRESS_SPACE 0x0002 347 #define HVCALL_FLUSH_VIRTUAL_ADDRESS_LIST 0x0003 348 #define HVCALL_NOTIFY_LONG_SPIN_WAIT 0x0008 349 #define HVCALL_SEND_IPI 0x000b 350 #define HVCALL_FLUSH_VIRTUAL_ADDRESS_SPACE_EX 0x0013 351 #define HVCALL_FLUSH_VIRTUAL_ADDRESS_LIST_EX 0x0014 352 #define HVCALL_SEND_IPI_EX 0x0015 353 #define HVCALL_POST_MESSAGE 0x005c 354 #define HVCALL_SIGNAL_EVENT 0x005d 355 #define HVCALL_FLUSH_GUEST_PHYSICAL_ADDRESS_SPACE 0x00af 356 357 #define HV_X64_MSR_VP_ASSIST_PAGE_ENABLE 0x00000001 358 #define HV_X64_MSR_VP_ASSIST_PAGE_ADDRESS_SHIFT 12 359 #define HV_X64_MSR_VP_ASSIST_PAGE_ADDRESS_MASK \ 360 (~((1ull << HV_X64_MSR_VP_ASSIST_PAGE_ADDRESS_SHIFT) - 1)) 361 362 /* Hyper-V Enlightened VMCS version mask in nested features CPUID */ 363 #define HV_X64_ENLIGHTENED_VMCS_VERSION 0xff 364 365 #define HV_X64_MSR_TSC_REFERENCE_ENABLE 0x00000001 366 #define HV_X64_MSR_TSC_REFERENCE_ADDRESS_SHIFT 12 367 368 #define HV_PROCESSOR_POWER_STATE_C0 0 369 #define HV_PROCESSOR_POWER_STATE_C1 1 370 #define HV_PROCESSOR_POWER_STATE_C2 2 371 #define HV_PROCESSOR_POWER_STATE_C3 3 372 373 #define HV_FLUSH_ALL_PROCESSORS BIT(0) 374 #define HV_FLUSH_ALL_VIRTUAL_ADDRESS_SPACES BIT(1) 375 #define HV_FLUSH_NON_GLOBAL_MAPPINGS_ONLY BIT(2) 376 #define HV_FLUSH_USE_EXTENDED_RANGE_FORMAT BIT(3) 377 378 enum HV_GENERIC_SET_FORMAT { 379 HV_GENERIC_SET_SPARSE_4K, 380 HV_GENERIC_SET_ALL, 381 }; 382 383 #define HV_HYPERCALL_RESULT_MASK GENMASK_ULL(15, 0) 384 #define HV_HYPERCALL_FAST_BIT BIT(16) 385 #define HV_HYPERCALL_VARHEAD_OFFSET 17 386 #define HV_HYPERCALL_REP_COMP_OFFSET 32 387 #define HV_HYPERCALL_REP_COMP_MASK GENMASK_ULL(43, 32) 388 #define HV_HYPERCALL_REP_START_OFFSET 48 389 #define HV_HYPERCALL_REP_START_MASK GENMASK_ULL(59, 48) 390 391 /* hypercall status code */ 392 #define HV_STATUS_SUCCESS 0 393 #define HV_STATUS_INVALID_HYPERCALL_CODE 2 394 #define HV_STATUS_INVALID_HYPERCALL_INPUT 3 395 #define HV_STATUS_INVALID_ALIGNMENT 4 396 #define HV_STATUS_INVALID_PARAMETER 5 397 #define HV_STATUS_INSUFFICIENT_MEMORY 11 398 #define HV_STATUS_INVALID_PORT_ID 17 399 #define HV_STATUS_INVALID_CONNECTION_ID 18 400 #define HV_STATUS_INSUFFICIENT_BUFFERS 19 401 402 typedef struct _HV_REFERENCE_TSC_PAGE { 403 __u32 tsc_sequence; 404 __u32 res1; 405 __u64 tsc_scale; 406 __s64 tsc_offset; 407 } HV_REFERENCE_TSC_PAGE, *PHV_REFERENCE_TSC_PAGE; 408 409 /* Define the number of synthetic interrupt sources. */ 410 #define HV_SYNIC_SINT_COUNT (16) 411 /* Define the expected SynIC version. */ 412 #define HV_SYNIC_VERSION_1 (0x1) 413 /* Valid SynIC vectors are 16-255. */ 414 #define HV_SYNIC_FIRST_VALID_VECTOR (16) 415 416 #define HV_SYNIC_CONTROL_ENABLE (1ULL << 0) 417 #define HV_SYNIC_SIMP_ENABLE (1ULL << 0) 418 #define HV_SYNIC_SIEFP_ENABLE (1ULL << 0) 419 #define HV_SYNIC_SINT_MASKED (1ULL << 16) 420 #define HV_SYNIC_SINT_AUTO_EOI (1ULL << 17) 421 #define HV_SYNIC_SINT_VECTOR_MASK (0xFF) 422 423 #define HV_SYNIC_STIMER_COUNT (4) 424 425 /* Define synthetic interrupt controller message constants. */ 426 #define HV_MESSAGE_SIZE (256) 427 #define HV_MESSAGE_PAYLOAD_BYTE_COUNT (240) 428 #define HV_MESSAGE_PAYLOAD_QWORD_COUNT (30) 429 430 /* Define hypervisor message types. */ 431 enum hv_message_type { 432 HVMSG_NONE = 0x00000000, 433 434 /* Memory access messages. */ 435 HVMSG_UNMAPPED_GPA = 0x80000000, 436 HVMSG_GPA_INTERCEPT = 0x80000001, 437 438 /* Timer notification messages. */ 439 HVMSG_TIMER_EXPIRED = 0x80000010, 440 441 /* Error messages. */ 442 HVMSG_INVALID_VP_REGISTER_VALUE = 0x80000020, 443 HVMSG_UNRECOVERABLE_EXCEPTION = 0x80000021, 444 HVMSG_UNSUPPORTED_FEATURE = 0x80000022, 445 446 /* Trace buffer complete messages. */ 447 HVMSG_EVENTLOG_BUFFERCOMPLETE = 0x80000040, 448 449 /* Platform-specific processor intercept messages. */ 450 HVMSG_X64_IOPORT_INTERCEPT = 0x80010000, 451 HVMSG_X64_MSR_INTERCEPT = 0x80010001, 452 HVMSG_X64_CPUID_INTERCEPT = 0x80010002, 453 HVMSG_X64_EXCEPTION_INTERCEPT = 0x80010003, 454 HVMSG_X64_APIC_EOI = 0x80010004, 455 HVMSG_X64_LEGACY_FP_ERROR = 0x80010005 456 }; 457 458 /* Define synthetic interrupt controller message flags. */ 459 union hv_message_flags { 460 __u8 asu8; 461 struct { 462 __u8 msg_pending:1; 463 __u8 reserved:7; 464 }; 465 }; 466 467 /* Define port identifier type. */ 468 union hv_port_id { 469 __u32 asu32; 470 struct { 471 __u32 id:24; 472 __u32 reserved:8; 473 } u; 474 }; 475 476 /* Define synthetic interrupt controller message header. */ 477 struct hv_message_header { 478 __u32 message_type; 479 __u8 payload_size; 480 union hv_message_flags message_flags; 481 __u8 reserved[2]; 482 union { 483 __u64 sender; 484 union hv_port_id port; 485 }; 486 }; 487 488 /* Define synthetic interrupt controller message format. */ 489 struct hv_message { 490 struct hv_message_header header; 491 union { 492 __u64 payload[HV_MESSAGE_PAYLOAD_QWORD_COUNT]; 493 } u; 494 }; 495 496 /* Define the synthetic interrupt message page layout. */ 497 struct hv_message_page { 498 struct hv_message sint_message[HV_SYNIC_SINT_COUNT]; 499 }; 500 501 /* Define timer message payload structure. */ 502 struct hv_timer_message_payload { 503 __u32 timer_index; 504 __u32 reserved; 505 __u64 expiration_time; /* When the timer expired */ 506 __u64 delivery_time; /* When the message was delivered */ 507 }; 508 509 /* Define virtual processor assist page structure. */ 510 struct hv_vp_assist_page { 511 __u32 apic_assist; 512 __u32 reserved; 513 __u64 vtl_control[2]; 514 __u64 nested_enlightenments_control[2]; 515 __u32 enlighten_vmentry; 516 __u64 current_nested_vmcs; 517 }; 518 519 struct hv_enlightened_vmcs { 520 u32 revision_id; 521 u32 abort; 522 523 u16 host_es_selector; 524 u16 host_cs_selector; 525 u16 host_ss_selector; 526 u16 host_ds_selector; 527 u16 host_fs_selector; 528 u16 host_gs_selector; 529 u16 host_tr_selector; 530 531 u64 host_ia32_pat; 532 u64 host_ia32_efer; 533 534 u64 host_cr0; 535 u64 host_cr3; 536 u64 host_cr4; 537 538 u64 host_ia32_sysenter_esp; 539 u64 host_ia32_sysenter_eip; 540 u64 host_rip; 541 u32 host_ia32_sysenter_cs; 542 543 u32 pin_based_vm_exec_control; 544 u32 vm_exit_controls; 545 u32 secondary_vm_exec_control; 546 547 u64 io_bitmap_a; 548 u64 io_bitmap_b; 549 u64 msr_bitmap; 550 551 u16 guest_es_selector; 552 u16 guest_cs_selector; 553 u16 guest_ss_selector; 554 u16 guest_ds_selector; 555 u16 guest_fs_selector; 556 u16 guest_gs_selector; 557 u16 guest_ldtr_selector; 558 u16 guest_tr_selector; 559 560 u32 guest_es_limit; 561 u32 guest_cs_limit; 562 u32 guest_ss_limit; 563 u32 guest_ds_limit; 564 u32 guest_fs_limit; 565 u32 guest_gs_limit; 566 u32 guest_ldtr_limit; 567 u32 guest_tr_limit; 568 u32 guest_gdtr_limit; 569 u32 guest_idtr_limit; 570 571 u32 guest_es_ar_bytes; 572 u32 guest_cs_ar_bytes; 573 u32 guest_ss_ar_bytes; 574 u32 guest_ds_ar_bytes; 575 u32 guest_fs_ar_bytes; 576 u32 guest_gs_ar_bytes; 577 u32 guest_ldtr_ar_bytes; 578 u32 guest_tr_ar_bytes; 579 580 u64 guest_es_base; 581 u64 guest_cs_base; 582 u64 guest_ss_base; 583 u64 guest_ds_base; 584 u64 guest_fs_base; 585 u64 guest_gs_base; 586 u64 guest_ldtr_base; 587 u64 guest_tr_base; 588 u64 guest_gdtr_base; 589 u64 guest_idtr_base; 590 591 u64 padding64_1[3]; 592 593 u64 vm_exit_msr_store_addr; 594 u64 vm_exit_msr_load_addr; 595 u64 vm_entry_msr_load_addr; 596 597 u64 cr3_target_value0; 598 u64 cr3_target_value1; 599 u64 cr3_target_value2; 600 u64 cr3_target_value3; 601 602 u32 page_fault_error_code_mask; 603 u32 page_fault_error_code_match; 604 605 u32 cr3_target_count; 606 u32 vm_exit_msr_store_count; 607 u32 vm_exit_msr_load_count; 608 u32 vm_entry_msr_load_count; 609 610 u64 tsc_offset; 611 u64 virtual_apic_page_addr; 612 u64 vmcs_link_pointer; 613 614 u64 guest_ia32_debugctl; 615 u64 guest_ia32_pat; 616 u64 guest_ia32_efer; 617 618 u64 guest_pdptr0; 619 u64 guest_pdptr1; 620 u64 guest_pdptr2; 621 u64 guest_pdptr3; 622 623 u64 guest_pending_dbg_exceptions; 624 u64 guest_sysenter_esp; 625 u64 guest_sysenter_eip; 626 627 u32 guest_activity_state; 628 u32 guest_sysenter_cs; 629 630 u64 cr0_guest_host_mask; 631 u64 cr4_guest_host_mask; 632 u64 cr0_read_shadow; 633 u64 cr4_read_shadow; 634 u64 guest_cr0; 635 u64 guest_cr3; 636 u64 guest_cr4; 637 u64 guest_dr7; 638 639 u64 host_fs_base; 640 u64 host_gs_base; 641 u64 host_tr_base; 642 u64 host_gdtr_base; 643 u64 host_idtr_base; 644 u64 host_rsp; 645 646 u64 ept_pointer; 647 648 u16 virtual_processor_id; 649 u16 padding16[3]; 650 651 u64 padding64_2[5]; 652 u64 guest_physical_address; 653 654 u32 vm_instruction_error; 655 u32 vm_exit_reason; 656 u32 vm_exit_intr_info; 657 u32 vm_exit_intr_error_code; 658 u32 idt_vectoring_info_field; 659 u32 idt_vectoring_error_code; 660 u32 vm_exit_instruction_len; 661 u32 vmx_instruction_info; 662 663 u64 exit_qualification; 664 u64 exit_io_instruction_ecx; 665 u64 exit_io_instruction_esi; 666 u64 exit_io_instruction_edi; 667 u64 exit_io_instruction_eip; 668 669 u64 guest_linear_address; 670 u64 guest_rsp; 671 u64 guest_rflags; 672 673 u32 guest_interruptibility_info; 674 u32 cpu_based_vm_exec_control; 675 u32 exception_bitmap; 676 u32 vm_entry_controls; 677 u32 vm_entry_intr_info_field; 678 u32 vm_entry_exception_error_code; 679 u32 vm_entry_instruction_len; 680 u32 tpr_threshold; 681 682 u64 guest_rip; 683 684 u32 hv_clean_fields; 685 u32 hv_padding_32; 686 u32 hv_synthetic_controls; 687 struct { 688 u32 nested_flush_hypercall:1; 689 u32 msr_bitmap:1; 690 u32 reserved:30; 691 } hv_enlightenments_control; 692 u32 hv_vp_id; 693 694 u64 hv_vm_id; 695 u64 partition_assist_page; 696 u64 padding64_4[4]; 697 u64 guest_bndcfgs; 698 u64 padding64_5[7]; 699 u64 xss_exit_bitmap; 700 u64 padding64_6[7]; 701 }; 702 703 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_NONE 0 704 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_IO_BITMAP BIT(0) 705 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_MSR_BITMAP BIT(1) 706 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_CONTROL_GRP2 BIT(2) 707 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_CONTROL_GRP1 BIT(3) 708 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_CONTROL_PROC BIT(4) 709 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_CONTROL_EVENT BIT(5) 710 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_CONTROL_ENTRY BIT(6) 711 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_CONTROL_EXCPN BIT(7) 712 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_CRDR BIT(8) 713 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_CONTROL_XLAT BIT(9) 714 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_GUEST_BASIC BIT(10) 715 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_GUEST_GRP1 BIT(11) 716 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_GUEST_GRP2 BIT(12) 717 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_HOST_POINTER BIT(13) 718 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_HOST_GRP1 BIT(14) 719 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_ENLIGHTENMENTSCONTROL BIT(15) 720 721 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_ALL 0xFFFF 722 723 #define HV_STIMER_ENABLE (1ULL << 0) 724 #define HV_STIMER_PERIODIC (1ULL << 1) 725 #define HV_STIMER_LAZY (1ULL << 2) 726 #define HV_STIMER_AUTOENABLE (1ULL << 3) 727 #define HV_STIMER_SINT(config) (__u8)(((config) >> 16) & 0x0F) 728 729 struct hv_vpset { 730 u64 format; 731 u64 valid_bank_mask; 732 u64 bank_contents[]; 733 }; 734 735 /* HvCallSendSyntheticClusterIpi hypercall */ 736 struct hv_send_ipi { 737 u32 vector; 738 u32 reserved; 739 u64 cpu_mask; 740 }; 741 742 /* HvCallSendSyntheticClusterIpiEx hypercall */ 743 struct hv_send_ipi_ex { 744 u32 vector; 745 u32 reserved; 746 struct hv_vpset vp_set; 747 }; 748 749 /* HvFlushGuestPhysicalAddressSpace hypercalls */ 750 struct hv_guest_mapping_flush { 751 u64 address_space; 752 u64 flags; 753 }; 754 755 /* HvFlushVirtualAddressSpace, HvFlushVirtualAddressList hypercalls */ 756 struct hv_tlb_flush { 757 u64 address_space; 758 u64 flags; 759 u64 processor_mask; 760 u64 gva_list[]; 761 }; 762 763 /* HvFlushVirtualAddressSpaceEx, HvFlushVirtualAddressListEx hypercalls */ 764 struct hv_tlb_flush_ex { 765 u64 address_space; 766 u64 flags; 767 struct hv_vpset hv_vp_set; 768 u64 gva_list[]; 769 }; 770 771 #endif 772
