1/*
2 * Kernel execution entry point code.
3 *
4 *    Copyright (c) 1995-1996 Gary Thomas <gdt@linuxppc.org>
5 *	Initial PowerPC version.
6 *    Copyright (c) 1996 Cort Dougan <cort@cs.nmt.edu>
7 *	Rewritten for PReP
8 *    Copyright (c) 1996 Paul Mackerras <paulus@cs.anu.edu.au>
9 *	Low-level exception handers, MMU support, and rewrite.
10 *    Copyright (c) 1997 Dan Malek <dmalek@jlc.net>
11 *	PowerPC 8xx modifications.
12 *    Copyright (c) 1998-1999 TiVo, Inc.
13 *	PowerPC 403GCX modifications.
14 *    Copyright (c) 1999 Grant Erickson <grant@lcse.umn.edu>
15 *	PowerPC 403GCX/405GP modifications.
16 *    Copyright 2000 MontaVista Software Inc.
17 *	PPC405 modifications
18 *	PowerPC 403GCX/405GP modifications.
19 *	Author: MontaVista Software, Inc.
20 *		frank_rowand@mvista.com or source@mvista.com
21 *		debbie_chu@mvista.com
22 *    Copyright 2002-2004 MontaVista Software, Inc.
23 *	PowerPC 44x support, Matt Porter <mporter@kernel.crashing.org>
24 *    Copyright 2004 Freescale Semiconductor, Inc
25 *	PowerPC e500 modifications, Kumar Gala <galak@kernel.crashing.org>
26 *
27 * This program is free software; you can redistribute  it and/or modify it
28 * under  the terms of  the GNU General  Public License as published by the
29 * Free Software Foundation;  either version 2 of the  License, or (at your
30 * option) any later version.
31 */
32
33#include <linux/init.h>
34#include <linux/threads.h>
35#include <asm/processor.h>
36#include <asm/page.h>
37#include <asm/mmu.h>
38#include <asm/pgtable.h>
39#include <asm/cputable.h>
40#include <asm/thread_info.h>
41#include <asm/ppc_asm.h>
42#include <asm/asm-offsets.h>
43#include <asm/cache.h>
44#include <asm/ptrace.h>
45#include <asm/export.h>
46#include <asm/feature-fixups.h>
47#include "head_booke.h"
48
49/* As with the other PowerPC ports, it is expected that when code
50 * execution begins here, the following registers contain valid, yet
51 * optional, information:
52 *
53 *   r3 - Board info structure pointer (DRAM, frequency, MAC address, etc.)
54 *   r4 - Starting address of the init RAM disk
55 *   r5 - Ending address of the init RAM disk
56 *   r6 - Start of kernel command line string (e.g. "mem=128")
57 *   r7 - End of kernel command line string
58 *
59 */
60	__HEAD
61_ENTRY(_stext);
62_ENTRY(_start);
63	/*
64	 * Reserve a word at a fixed location to store the address
65	 * of abatron_pteptrs
66	 */
67	nop
68
69	/* Translate device tree address to physical, save in r30/r31 */
70	bl	get_phys_addr
71	mr	r30,r3
72	mr	r31,r4
73
74	li	r25,0			/* phys kernel start (low) */
75	li	r24,0			/* CPU number */
76	li	r23,0			/* phys kernel start (high) */
77
78#ifdef CONFIG_RELOCATABLE
79	LOAD_REG_ADDR_PIC(r3, _stext)	/* Get our current runtime base */
80
81	/* Translate _stext address to physical, save in r23/r25 */
82	bl	get_phys_addr
83	mr	r23,r3
84	mr	r25,r4
85
86	bl	0f
870:	mflr	r8
88	addis	r3,r8,(is_second_reloc - 0b)@ha
89	lwz	r19,(is_second_reloc - 0b)@l(r3)
90
91	/* Check if this is the second relocation. */
92	cmpwi	r19,1
93	bne	1f
94
95	/*
96	 * For the second relocation, we already get the real memstart_addr
97	 * from device tree. So we will map PAGE_OFFSET to memstart_addr,
98	 * then the virtual address of start kernel should be:
99	 *          PAGE_OFFSET + (kernstart_addr - memstart_addr)
100	 * Since the offset between kernstart_addr and memstart_addr should
101	 * never be beyond 1G, so we can just use the lower 32bit of them
102	 * for the calculation.
103	 */
104	lis	r3,PAGE_OFFSET@h
105
106	addis	r4,r8,(kernstart_addr - 0b)@ha
107	addi	r4,r4,(kernstart_addr - 0b)@l
108	lwz	r5,4(r4)
109
110	addis	r6,r8,(memstart_addr - 0b)@ha
111	addi	r6,r6,(memstart_addr - 0b)@l
112	lwz	r7,4(r6)
113
114	subf	r5,r7,r5
115	add	r3,r3,r5
116	b	2f
117
1181:
119	/*
120	 * We have the runtime (virutal) address of our base.
121	 * We calculate our shift of offset from a 64M page.
122	 * We could map the 64M page we belong to at PAGE_OFFSET and
123	 * get going from there.
124	 */
125	lis	r4,KERNELBASE@h
126	ori	r4,r4,KERNELBASE@l
127	rlwinm	r6,r25,0,0x3ffffff		/* r6 = PHYS_START % 64M */
128	rlwinm	r5,r4,0,0x3ffffff		/* r5 = KERNELBASE % 64M */
129	subf	r3,r5,r6			/* r3 = r6 - r5 */
130	add	r3,r4,r3			/* Required Virtual Address */
131
1322:	bl	relocate
133
134	/*
135	 * For the second relocation, we already set the right tlb entries
136	 * for the kernel space, so skip the code in fsl_booke_entry_mapping.S
137	*/
138	cmpwi	r19,1
139	beq	set_ivor
140#endif
141
142/* We try to not make any assumptions about how the boot loader
143 * setup or used the TLBs.  We invalidate all mappings from the
144 * boot loader and load a single entry in TLB1[0] to map the
145 * first 64M of kernel memory.  Any boot info passed from the
146 * bootloader needs to live in this first 64M.
147 *
148 * Requirement on bootloader:
149 *  - The page we're executing in needs to reside in TLB1 and
150 *    have IPROT=1.  If not an invalidate broadcast could
151 *    evict the entry we're currently executing in.
152 *
153 *  r3 = Index of TLB1 were executing in
154 *  r4 = Current MSR[IS]
155 *  r5 = Index of TLB1 temp mapping
156 *
157 * Later in mapin_ram we will correctly map lowmem, and resize TLB1[0]
158 * if needed
159 */
160
161_ENTRY(__early_start)
162
163#define ENTRY_MAPPING_BOOT_SETUP
164#include "fsl_booke_entry_mapping.S"
165#undef ENTRY_MAPPING_BOOT_SETUP
166
167set_ivor:
168	/* Establish the interrupt vector offsets */
169	SET_IVOR(0,  CriticalInput);
170	SET_IVOR(1,  MachineCheck);
171	SET_IVOR(2,  DataStorage);
172	SET_IVOR(3,  InstructionStorage);
173	SET_IVOR(4,  ExternalInput);
174	SET_IVOR(5,  Alignment);
175	SET_IVOR(6,  Program);
176	SET_IVOR(7,  FloatingPointUnavailable);
177	SET_IVOR(8,  SystemCall);
178	SET_IVOR(9,  AuxillaryProcessorUnavailable);
179	SET_IVOR(10, Decrementer);
180	SET_IVOR(11, FixedIntervalTimer);
181	SET_IVOR(12, WatchdogTimer);
182	SET_IVOR(13, DataTLBError);
183	SET_IVOR(14, InstructionTLBError);
184	SET_IVOR(15, DebugCrit);
185
186	/* Establish the interrupt vector base */
187	lis	r4,interrupt_base@h	/* IVPR only uses the high 16-bits */
188	mtspr	SPRN_IVPR,r4
189
190	/* Setup the defaults for TLB entries */
191	li	r2,(MAS4_TSIZED(BOOK3E_PAGESZ_4K))@l
192#ifdef CONFIG_E200
193	oris	r2,r2,MAS4_TLBSELD(1)@h
194#endif
195	mtspr	SPRN_MAS4, r2
196
197#if 0
198	/* Enable DOZE */
199	mfspr	r2,SPRN_HID0
200	oris	r2,r2,HID0_DOZE@h
201	mtspr	SPRN_HID0, r2
202#endif
203
204#if !defined(CONFIG_BDI_SWITCH)
205	/*
206	 * The Abatron BDI JTAG debugger does not tolerate others
207	 * mucking with the debug registers.
208	 */
209	lis	r2,DBCR0_IDM@h
210	mtspr	SPRN_DBCR0,r2
211	isync
212	/* clear any residual debug events */
213	li	r2,-1
214	mtspr	SPRN_DBSR,r2
215#endif
216
217#ifdef CONFIG_SMP
218	/* Check to see if we're the second processor, and jump
219	 * to the secondary_start code if so
220	 */
221	LOAD_REG_ADDR_PIC(r24, boot_cpuid)
222	lwz	r24, 0(r24)
223	cmpwi	r24, -1
224	mfspr   r24,SPRN_PIR
225	bne	__secondary_start
226#endif
227
228	/*
229	 * This is where the main kernel code starts.
230	 */
231
232	/* ptr to current */
233	lis	r2,init_task@h
234	ori	r2,r2,init_task@l
235
236	/* ptr to current thread */
237	addi	r4,r2,THREAD	/* init task's THREAD */
238	mtspr	SPRN_SPRG_THREAD,r4
239
240	/* stack */
241	lis	r1,init_thread_union@h
242	ori	r1,r1,init_thread_union@l
243	li	r0,0
244	stwu	r0,THREAD_SIZE-STACK_FRAME_OVERHEAD(r1)
245
246	CURRENT_THREAD_INFO(r22, r1)
247	stw	r24, TI_CPU(r22)
248
249	bl	early_init
250
251#ifdef CONFIG_RELOCATABLE
252	mr	r3,r30
253	mr	r4,r31
254#ifdef CONFIG_PHYS_64BIT
255	mr	r5,r23
256	mr	r6,r25
257#else
258	mr	r5,r25
259#endif
260	bl	relocate_init
261#endif
262
263#ifdef CONFIG_DYNAMIC_MEMSTART
264	lis	r3,kernstart_addr@ha
265	la	r3,kernstart_addr@l(r3)
266#ifdef CONFIG_PHYS_64BIT
267	stw	r23,0(r3)
268	stw	r25,4(r3)
269#else
270	stw	r25,0(r3)
271#endif
272#endif
273
274/*
275 * Decide what sort of machine this is and initialize the MMU.
276 */
277	mr	r3,r30
278	mr	r4,r31
279	bl	machine_init
280	bl	MMU_init
281
282	/* Setup PTE pointers for the Abatron bdiGDB */
283	lis	r6, swapper_pg_dir@h
284	ori	r6, r6, swapper_pg_dir@l
285	lis	r5, abatron_pteptrs@h
286	ori	r5, r5, abatron_pteptrs@l
287	lis	r4, KERNELBASE@h
288	ori	r4, r4, KERNELBASE@l
289	stw	r5, 0(r4)	/* Save abatron_pteptrs at a fixed location */
290	stw	r6, 0(r5)
291
292	/* Let's move on */
293	lis	r4,start_kernel@h
294	ori	r4,r4,start_kernel@l
295	lis	r3,MSR_KERNEL@h
296	ori	r3,r3,MSR_KERNEL@l
297	mtspr	SPRN_SRR0,r4
298	mtspr	SPRN_SRR1,r3
299	rfi			/* change context and jump to start_kernel */
300
301/* Macros to hide the PTE size differences
302 *
303 * FIND_PTE -- walks the page tables given EA & pgdir pointer
304 *   r10 -- EA of fault
305 *   r11 -- PGDIR pointer
306 *   r12 -- free
307 *   label 2: is the bailout case
308 *
309 * if we find the pte (fall through):
310 *   r11 is low pte word
311 *   r12 is pointer to the pte
312 *   r10 is the pshift from the PGD, if we're a hugepage
313 */
314#ifdef CONFIG_PTE_64BIT
315#ifdef CONFIG_HUGETLB_PAGE
316#define FIND_PTE	\
317	rlwinm	r12, r10, 13, 19, 29;	/* Compute pgdir/pmd offset */	\
318	lwzx	r11, r12, r11;		/* Get pgd/pmd entry */		\
319	rlwinm.	r12, r11, 0, 0, 20;	/* Extract pt base address */	\
320	blt	1000f;			/* Normal non-huge page */	\
321	beq	2f;			/* Bail if no table */		\
322	oris	r11, r11, PD_HUGE@h;	/* Put back address bit */	\
323	andi.	r10, r11, HUGEPD_SHIFT_MASK@l; /* extract size field */	\
324	xor	r12, r10, r11;		/* drop size bits from pointer */ \
325	b	1001f;							\
3261000:	rlwimi	r12, r10, 23, 20, 28;	/* Compute pte address */	\
327	li	r10, 0;			/* clear r10 */			\
3281001:	lwz	r11, 4(r12);		/* Get pte entry */
329#else
330#define FIND_PTE	\
331	rlwinm	r12, r10, 13, 19, 29;	/* Compute pgdir/pmd offset */	\
332	lwzx	r11, r12, r11;		/* Get pgd/pmd entry */		\
333	rlwinm.	r12, r11, 0, 0, 20;	/* Extract pt base address */	\
334	beq	2f;			/* Bail if no table */		\
335	rlwimi	r12, r10, 23, 20, 28;	/* Compute pte address */	\
336	lwz	r11, 4(r12);		/* Get pte entry */
337#endif /* HUGEPAGE */
338#else /* !PTE_64BIT */
339#define FIND_PTE	\
340	rlwimi	r11, r10, 12, 20, 29;	/* Create L1 (pgdir/pmd) address */	\
341	lwz	r11, 0(r11);		/* Get L1 entry */			\
342	rlwinm.	r12, r11, 0, 0, 19;	/* Extract L2 (pte) base address */	\
343	beq	2f;			/* Bail if no table */			\
344	rlwimi	r12, r10, 22, 20, 29;	/* Compute PTE address */		\
345	lwz	r11, 0(r12);		/* Get Linux PTE */
346#endif
347
348/*
349 * Interrupt vector entry code
350 *
351 * The Book E MMUs are always on so we don't need to handle
352 * interrupts in real mode as with previous PPC processors. In
353 * this case we handle interrupts in the kernel virtual address
354 * space.
355 *
356 * Interrupt vectors are dynamically placed relative to the
357 * interrupt prefix as determined by the address of interrupt_base.
358 * The interrupt vectors offsets are programmed using the labels
359 * for each interrupt vector entry.
360 *
361 * Interrupt vectors must be aligned on a 16 byte boundary.
362 * We align on a 32 byte cache line boundary for good measure.
363 */
364
365interrupt_base:
366	/* Critical Input Interrupt */
367	CRITICAL_EXCEPTION(0x0100, CRITICAL, CriticalInput, unknown_exception)
368
369	/* Machine Check Interrupt */
370#ifdef CONFIG_E200
371	/* no RFMCI, MCSRRs on E200 */
372	CRITICAL_EXCEPTION(0x0200, MACHINE_CHECK, MachineCheck, \
373			   machine_check_exception)
374#else
375	MCHECK_EXCEPTION(0x0200, MachineCheck, machine_check_exception)
376#endif
377
378	/* Data Storage Interrupt */
379	START_EXCEPTION(DataStorage)
380	NORMAL_EXCEPTION_PROLOG(DATA_STORAGE)
381	mfspr	r5,SPRN_ESR		/* Grab the ESR, save it, pass arg3 */
382	stw	r5,_ESR(r11)
383	mfspr	r4,SPRN_DEAR		/* Grab the DEAR, save it, pass arg2 */
384	andis.	r10,r5,(ESR_ILK|ESR_DLK)@h
385	bne	1f
386	EXC_XFER_LITE(0x0300, handle_page_fault)
3871:
388	addi	r3,r1,STACK_FRAME_OVERHEAD
389	EXC_XFER_EE_LITE(0x0300, CacheLockingException)
390
391	/* Instruction Storage Interrupt */
392	INSTRUCTION_STORAGE_EXCEPTION
393
394	/* External Input Interrupt */
395	EXCEPTION(0x0500, EXTERNAL, ExternalInput, do_IRQ, EXC_XFER_LITE)
396
397	/* Alignment Interrupt */
398	ALIGNMENT_EXCEPTION
399
400	/* Program Interrupt */
401	PROGRAM_EXCEPTION
402
403	/* Floating Point Unavailable Interrupt */
404#ifdef CONFIG_PPC_FPU
405	FP_UNAVAILABLE_EXCEPTION
406#else
407#ifdef CONFIG_E200
408	/* E200 treats 'normal' floating point instructions as FP Unavail exception */
409	EXCEPTION(0x0800, FP_UNAVAIL, FloatingPointUnavailable, \
410		  program_check_exception, EXC_XFER_EE)
411#else
412	EXCEPTION(0x0800, FP_UNAVAIL, FloatingPointUnavailable, \
413		  unknown_exception, EXC_XFER_EE)
414#endif
415#endif
416
417	/* System Call Interrupt */
418	START_EXCEPTION(SystemCall)
419	NORMAL_EXCEPTION_PROLOG(SYSCALL)
420	EXC_XFER_EE_LITE(0x0c00, DoSyscall)
421
422	/* Auxiliary Processor Unavailable Interrupt */
423	EXCEPTION(0x2900, AP_UNAVAIL, AuxillaryProcessorUnavailable, \
424		  unknown_exception, EXC_XFER_EE)
425
426	/* Decrementer Interrupt */
427	DECREMENTER_EXCEPTION
428
429	/* Fixed Internal Timer Interrupt */
430	/* TODO: Add FIT support */
431	EXCEPTION(0x3100, FIT, FixedIntervalTimer, \
432		  unknown_exception, EXC_XFER_EE)
433
434	/* Watchdog Timer Interrupt */
435#ifdef CONFIG_BOOKE_WDT
436	CRITICAL_EXCEPTION(0x3200, WATCHDOG, WatchdogTimer, WatchdogException)
437#else
438	CRITICAL_EXCEPTION(0x3200, WATCHDOG, WatchdogTimer, unknown_exception)
439#endif
440
441	/* Data TLB Error Interrupt */
442	START_EXCEPTION(DataTLBError)
443	mtspr	SPRN_SPRG_WSCRATCH0, r10 /* Save some working registers */
444	mfspr	r10, SPRN_SPRG_THREAD
445	stw	r11, THREAD_NORMSAVE(0)(r10)
446#ifdef CONFIG_KVM_BOOKE_HV
447BEGIN_FTR_SECTION
448	mfspr	r11, SPRN_SRR1
449END_FTR_SECTION_IFSET(CPU_FTR_EMB_HV)
450#endif
451	stw	r12, THREAD_NORMSAVE(1)(r10)
452	stw	r13, THREAD_NORMSAVE(2)(r10)
453	mfcr	r13
454	stw	r13, THREAD_NORMSAVE(3)(r10)
455	DO_KVM	BOOKE_INTERRUPT_DTLB_MISS SPRN_SRR1
456	mfspr	r10, SPRN_DEAR		/* Get faulting address */
457
458	/* If we are faulting a kernel address, we have to use the
459	 * kernel page tables.
460	 */
461	lis	r11, PAGE_OFFSET@h
462	cmplw	5, r10, r11
463	blt	5, 3f
464	lis	r11, swapper_pg_dir@h
465	ori	r11, r11, swapper_pg_dir@l
466
467	mfspr	r12,SPRN_MAS1		/* Set TID to 0 */
468	rlwinm	r12,r12,0,16,1
469	mtspr	SPRN_MAS1,r12
470
471	b	4f
472
473	/* Get the PGD for the current thread */
4743:
475	mfspr	r11,SPRN_SPRG_THREAD
476	lwz	r11,PGDIR(r11)
477
4784:
479	/* Mask of required permission bits. Note that while we
480	 * do copy ESR:ST to _PAGE_RW position as trying to write
481	 * to an RO page is pretty common, we don't do it with
482	 * _PAGE_DIRTY. We could do it, but it's a fairly rare
483	 * event so I'd rather take the overhead when it happens
484	 * rather than adding an instruction here. We should measure
485	 * whether the whole thing is worth it in the first place
486	 * as we could avoid loading SPRN_ESR completely in the first
487	 * place...
488	 *
489	 * TODO: Is it worth doing that mfspr & rlwimi in the first
490	 *       place or can we save a couple of instructions here ?
491	 */
492	mfspr	r12,SPRN_ESR
493#ifdef CONFIG_PTE_64BIT
494	li	r13,_PAGE_PRESENT
495	oris	r13,r13,_PAGE_ACCESSED@h
496#else
497	li	r13,_PAGE_PRESENT|_PAGE_ACCESSED
498#endif
499	rlwimi	r13,r12,11,29,29
500
501	FIND_PTE
502	andc.	r13,r13,r11		/* Check permission */
503
504#ifdef CONFIG_PTE_64BIT
505#ifdef CONFIG_SMP
506	subf	r13,r11,r12		/* create false data dep */
507	lwzx	r13,r11,r13		/* Get upper pte bits */
508#else
509	lwz	r13,0(r12)		/* Get upper pte bits */
510#endif
511#endif
512
513	bne	2f			/* Bail if permission/valid mismach */
514
515	/* Jump to common tlb load */
516	b	finish_tlb_load
5172:
518	/* The bailout.  Restore registers to pre-exception conditions
519	 * and call the heavyweights to help us out.
520	 */
521	mfspr	r10, SPRN_SPRG_THREAD
522	lwz	r11, THREAD_NORMSAVE(3)(r10)
523	mtcr	r11
524	lwz	r13, THREAD_NORMSAVE(2)(r10)
525	lwz	r12, THREAD_NORMSAVE(1)(r10)
526	lwz	r11, THREAD_NORMSAVE(0)(r10)
527	mfspr	r10, SPRN_SPRG_RSCRATCH0
528	b	DataStorage
529
530	/* Instruction TLB Error Interrupt */
531	/*
532	 * Nearly the same as above, except we get our
533	 * information from different registers and bailout
534	 * to a different point.
535	 */
536	START_EXCEPTION(InstructionTLBError)
537	mtspr	SPRN_SPRG_WSCRATCH0, r10 /* Save some working registers */
538	mfspr	r10, SPRN_SPRG_THREAD
539	stw	r11, THREAD_NORMSAVE(0)(r10)
540#ifdef CONFIG_KVM_BOOKE_HV
541BEGIN_FTR_SECTION
542	mfspr	r11, SPRN_SRR1
543END_FTR_SECTION_IFSET(CPU_FTR_EMB_HV)
544#endif
545	stw	r12, THREAD_NORMSAVE(1)(r10)
546	stw	r13, THREAD_NORMSAVE(2)(r10)
547	mfcr	r13
548	stw	r13, THREAD_NORMSAVE(3)(r10)
549	DO_KVM	BOOKE_INTERRUPT_ITLB_MISS SPRN_SRR1
550	mfspr	r10, SPRN_SRR0		/* Get faulting address */
551
552	/* If we are faulting a kernel address, we have to use the
553	 * kernel page tables.
554	 */
555	lis	r11, PAGE_OFFSET@h
556	cmplw	5, r10, r11
557	blt	5, 3f
558	lis	r11, swapper_pg_dir@h
559	ori	r11, r11, swapper_pg_dir@l
560
561	mfspr	r12,SPRN_MAS1		/* Set TID to 0 */
562	rlwinm	r12,r12,0,16,1
563	mtspr	SPRN_MAS1,r12
564
565	/* Make up the required permissions for kernel code */
566#ifdef CONFIG_PTE_64BIT
567	li	r13,_PAGE_PRESENT | _PAGE_BAP_SX
568	oris	r13,r13,_PAGE_ACCESSED@h
569#else
570	li	r13,_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_EXEC
571#endif
572	b	4f
573
574	/* Get the PGD for the current thread */
5753:
576	mfspr	r11,SPRN_SPRG_THREAD
577	lwz	r11,PGDIR(r11)
578
579	/* Make up the required permissions for user code */
580#ifdef CONFIG_PTE_64BIT
581	li	r13,_PAGE_PRESENT | _PAGE_BAP_UX
582	oris	r13,r13,_PAGE_ACCESSED@h
583#else
584	li	r13,_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_EXEC
585#endif
586
5874:
588	FIND_PTE
589	andc.	r13,r13,r11		/* Check permission */
590
591#ifdef CONFIG_PTE_64BIT
592#ifdef CONFIG_SMP
593	subf	r13,r11,r12		/* create false data dep */
594	lwzx	r13,r11,r13		/* Get upper pte bits */
595#else
596	lwz	r13,0(r12)		/* Get upper pte bits */
597#endif
598#endif
599
600	bne	2f			/* Bail if permission mismach */
601
602	/* Jump to common TLB load point */
603	b	finish_tlb_load
604
6052:
606	/* The bailout.  Restore registers to pre-exception conditions
607	 * and call the heavyweights to help us out.
608	 */
609	mfspr	r10, SPRN_SPRG_THREAD
610	lwz	r11, THREAD_NORMSAVE(3)(r10)
611	mtcr	r11
612	lwz	r13, THREAD_NORMSAVE(2)(r10)
613	lwz	r12, THREAD_NORMSAVE(1)(r10)
614	lwz	r11, THREAD_NORMSAVE(0)(r10)
615	mfspr	r10, SPRN_SPRG_RSCRATCH0
616	b	InstructionStorage
617
618/* Define SPE handlers for e200 and e500v2 */
619#ifdef CONFIG_SPE
620	/* SPE Unavailable */
621	START_EXCEPTION(SPEUnavailable)
622	NORMAL_EXCEPTION_PROLOG(SPE_UNAVAIL)
623	beq	1f
624	bl	load_up_spe
625	b	fast_exception_return
6261:	addi	r3,r1,STACK_FRAME_OVERHEAD
627	EXC_XFER_EE_LITE(0x2010, KernelSPE)
628#elif defined(CONFIG_SPE_POSSIBLE)
629	EXCEPTION(0x2020, SPE_UNAVAIL, SPEUnavailable, \
630		  unknown_exception, EXC_XFER_EE)
631#endif /* CONFIG_SPE_POSSIBLE */
632
633	/* SPE Floating Point Data */
634#ifdef CONFIG_SPE
635	EXCEPTION(0x2030, SPE_FP_DATA, SPEFloatingPointData,
636		  SPEFloatingPointException, EXC_XFER_EE)
637
638	/* SPE Floating Point Round */
639	EXCEPTION(0x2050, SPE_FP_ROUND, SPEFloatingPointRound, \
640		  SPEFloatingPointRoundException, EXC_XFER_EE)
641#elif defined(CONFIG_SPE_POSSIBLE)
642	EXCEPTION(0x2040, SPE_FP_DATA, SPEFloatingPointData,
643		  unknown_exception, EXC_XFER_EE)
644	EXCEPTION(0x2050, SPE_FP_ROUND, SPEFloatingPointRound, \
645		  unknown_exception, EXC_XFER_EE)
646#endif /* CONFIG_SPE_POSSIBLE */
647
648
649	/* Performance Monitor */
650	EXCEPTION(0x2060, PERFORMANCE_MONITOR, PerformanceMonitor, \
651		  performance_monitor_exception, EXC_XFER_STD)
652
653	EXCEPTION(0x2070, DOORBELL, Doorbell, doorbell_exception, EXC_XFER_STD)
654
655	CRITICAL_EXCEPTION(0x2080, DOORBELL_CRITICAL, \
656			   CriticalDoorbell, unknown_exception)
657
658	/* Debug Interrupt */
659	DEBUG_DEBUG_EXCEPTION
660	DEBUG_CRIT_EXCEPTION
661
662	GUEST_DOORBELL_EXCEPTION
663
664	CRITICAL_EXCEPTION(0, GUEST_DBELL_CRIT, CriticalGuestDoorbell, \
665			   unknown_exception)
666
667	/* Hypercall */
668	EXCEPTION(0, HV_SYSCALL, Hypercall, unknown_exception, EXC_XFER_EE)
669
670	/* Embedded Hypervisor Privilege */
671	EXCEPTION(0, HV_PRIV, Ehvpriv, unknown_exception, EXC_XFER_EE)
672
673interrupt_end:
674
675/*
676 * Local functions
677 */
678
679/*
680 * Both the instruction and data TLB miss get to this
681 * point to load the TLB.
682 *	r10 - tsize encoding (if HUGETLB_PAGE) or available to use
683 *	r11 - TLB (info from Linux PTE)
684 *	r12 - available to use
685 *	r13 - upper bits of PTE (if PTE_64BIT) or available to use
686 *	CR5 - results of addr >= PAGE_OFFSET
687 *	MAS0, MAS1 - loaded with proper value when we get here
688 *	MAS2, MAS3 - will need additional info from Linux PTE
689 *	Upon exit, we reload everything and RFI.
690 */
691finish_tlb_load:
692#ifdef CONFIG_HUGETLB_PAGE
693	cmpwi	6, r10, 0			/* check for huge page */
694	beq	6, finish_tlb_load_cont    	/* !huge */
695
696	/* Alas, we need more scratch registers for hugepages */
697	mfspr	r12, SPRN_SPRG_THREAD
698	stw	r14, THREAD_NORMSAVE(4)(r12)
699	stw	r15, THREAD_NORMSAVE(5)(r12)
700	stw	r16, THREAD_NORMSAVE(6)(r12)
701	stw	r17, THREAD_NORMSAVE(7)(r12)
702
703	/* Get the next_tlbcam_idx percpu var */
704#ifdef CONFIG_SMP
705	lwz	r12, THREAD_INFO-THREAD(r12)
706	lwz	r15, TI_CPU(r12)
707	lis     r14, __per_cpu_offset@h
708	ori     r14, r14, __per_cpu_offset@l
709	rlwinm  r15, r15, 2, 0, 29
710	lwzx    r16, r14, r15
711#else
712	li	r16, 0
713#endif
714	lis     r17, next_tlbcam_idx@h
715	ori	r17, r17, next_tlbcam_idx@l
716	add	r17, r17, r16			/* r17 = *next_tlbcam_idx */
717	lwz     r15, 0(r17)			/* r15 = next_tlbcam_idx */
718
719	lis	r14, MAS0_TLBSEL(1)@h		/* select TLB1 (TLBCAM) */
720	rlwimi	r14, r15, 16, 4, 15		/* next_tlbcam_idx entry */
721	mtspr	SPRN_MAS0, r14
722
723	/* Extract TLB1CFG(NENTRY) */
724	mfspr	r16, SPRN_TLB1CFG
725	andi.	r16, r16, 0xfff
726
727	/* Update next_tlbcam_idx, wrapping when necessary */
728	addi	r15, r15, 1
729	cmpw	r15, r16
730	blt 	100f
731	lis	r14, tlbcam_index@h
732	ori	r14, r14, tlbcam_index@l
733	lwz	r15, 0(r14)
734100:	stw	r15, 0(r17)
735
736	/*
737	 * Calc MAS1_TSIZE from r10 (which has pshift encoded)
738	 * tlb_enc = (pshift - 10).
739	 */
740	subi	r15, r10, 10
741	mfspr	r16, SPRN_MAS1
742	rlwimi	r16, r15, 7, 20, 24
743	mtspr	SPRN_MAS1, r16
744
745	/* copy the pshift for use later */
746	mr	r14, r10
747
748	/* fall through */
749
750#endif /* CONFIG_HUGETLB_PAGE */
751
752	/*
753	 * We set execute, because we don't have the granularity to
754	 * properly set this at the page level (Linux problem).
755	 * Many of these bits are software only.  Bits we don't set
756	 * here we (properly should) assume have the appropriate value.
757	 */
758finish_tlb_load_cont:
759#ifdef CONFIG_PTE_64BIT
760	rlwinm	r12, r11, 32-2, 26, 31	/* Move in perm bits */
761	andi.	r10, r11, _PAGE_DIRTY
762	bne	1f
763	li	r10, MAS3_SW | MAS3_UW
764	andc	r12, r12, r10
7651:	rlwimi	r12, r13, 20, 0, 11	/* grab RPN[32:43] */
766	rlwimi	r12, r11, 20, 12, 19	/* grab RPN[44:51] */
7672:	mtspr	SPRN_MAS3, r12
768BEGIN_MMU_FTR_SECTION
769	srwi	r10, r13, 12		/* grab RPN[12:31] */
770	mtspr	SPRN_MAS7, r10
771END_MMU_FTR_SECTION_IFSET(MMU_FTR_BIG_PHYS)
772#else
773	li	r10, (_PAGE_EXEC | _PAGE_PRESENT)
774	mr	r13, r11
775	rlwimi	r10, r11, 31, 29, 29	/* extract _PAGE_DIRTY into SW */
776	and	r12, r11, r10
777	andi.	r10, r11, _PAGE_USER	/* Test for _PAGE_USER */
778	slwi	r10, r12, 1
779	or	r10, r10, r12
780	iseleq	r12, r12, r10
781	rlwimi	r13, r12, 0, 20, 31	/* Get RPN from PTE, merge w/ perms */
782	mtspr	SPRN_MAS3, r13
783#endif
784
785	mfspr	r12, SPRN_MAS2
786#ifdef CONFIG_PTE_64BIT
787	rlwimi	r12, r11, 32-19, 27, 31	/* extract WIMGE from pte */
788#else
789	rlwimi	r12, r11, 26, 27, 31	/* extract WIMGE from pte */
790#endif
791#ifdef CONFIG_HUGETLB_PAGE
792	beq	6, 3f			/* don't mask if page isn't huge */
793	li	r13, 1
794	slw	r13, r13, r14
795	subi	r13, r13, 1
796	rlwinm	r13, r13, 0, 0, 19	/* bottom bits used for WIMGE/etc */
797	andc	r12, r12, r13		/* mask off ea bits within the page */
798#endif
7993:	mtspr	SPRN_MAS2, r12
800
801#ifdef CONFIG_E200
802	/* Round robin TLB1 entries assignment */
803	mfspr	r12, SPRN_MAS0
804
805	/* Extract TLB1CFG(NENTRY) */
806	mfspr	r11, SPRN_TLB1CFG
807	andi.	r11, r11, 0xfff
808
809	/* Extract MAS0(NV) */
810	andi.	r13, r12, 0xfff
811	addi	r13, r13, 1
812	cmpw	0, r13, r11
813	addi	r12, r12, 1
814
815	/* check if we need to wrap */
816	blt	7f
817
818	/* wrap back to first free tlbcam entry */
819	lis	r13, tlbcam_index@ha
820	lwz	r13, tlbcam_index@l(r13)
821	rlwimi	r12, r13, 0, 20, 31
8227:
823	mtspr	SPRN_MAS0,r12
824#endif /* CONFIG_E200 */
825
826tlb_write_entry:
827	tlbwe
828
829	/* Done...restore registers and get out of here.  */
830	mfspr	r10, SPRN_SPRG_THREAD
831#ifdef CONFIG_HUGETLB_PAGE
832	beq	6, 8f /* skip restore for 4k page faults */
833	lwz	r14, THREAD_NORMSAVE(4)(r10)
834	lwz	r15, THREAD_NORMSAVE(5)(r10)
835	lwz	r16, THREAD_NORMSAVE(6)(r10)
836	lwz	r17, THREAD_NORMSAVE(7)(r10)
837#endif
8388:	lwz	r11, THREAD_NORMSAVE(3)(r10)
839	mtcr	r11
840	lwz	r13, THREAD_NORMSAVE(2)(r10)
841	lwz	r12, THREAD_NORMSAVE(1)(r10)
842	lwz	r11, THREAD_NORMSAVE(0)(r10)
843	mfspr	r10, SPRN_SPRG_RSCRATCH0
844	rfi					/* Force context change */
845
846#ifdef CONFIG_SPE
847/* Note that the SPE support is closely modeled after the AltiVec
848 * support.  Changes to one are likely to be applicable to the
849 * other!  */
850_GLOBAL(load_up_spe)
851/*
852 * Disable SPE for the task which had SPE previously,
853 * and save its SPE registers in its thread_struct.
854 * Enables SPE for use in the kernel on return.
855 * On SMP we know the SPE units are free, since we give it up every
856 * switch.  -- Kumar
857 */
858	mfmsr	r5
859	oris	r5,r5,MSR_SPE@h
860	mtmsr	r5			/* enable use of SPE now */
861	isync
862	/* enable use of SPE after return */
863	oris	r9,r9,MSR_SPE@h
864	mfspr	r5,SPRN_SPRG_THREAD	/* current task's THREAD (phys) */
865	li	r4,1
866	li	r10,THREAD_ACC
867	stw	r4,THREAD_USED_SPE(r5)
868	evlddx	evr4,r10,r5
869	evmra	evr4,evr4
870	REST_32EVRS(0,r10,r5,THREAD_EVR0)
871	blr
872
873/*
874 * SPE unavailable trap from kernel - print a message, but let
875 * the task use SPE in the kernel until it returns to user mode.
876 */
877KernelSPE:
878	lwz	r3,_MSR(r1)
879	oris	r3,r3,MSR_SPE@h
880	stw	r3,_MSR(r1)	/* enable use of SPE after return */
881#ifdef CONFIG_PRINTK
882	lis	r3,87f@h
883	ori	r3,r3,87f@l
884	mr	r4,r2		/* current */
885	lwz	r5,_NIP(r1)
886	bl	printk
887#endif
888	b	ret_from_except
889#ifdef CONFIG_PRINTK
89087:	.string	"SPE used in kernel  (task=%p, pc=%x)  \n"
891#endif
892	.align	4,0
893
894#endif /* CONFIG_SPE */
895
896/*
897 * Translate the effec addr in r3 to phys addr. The phys addr will be put
898 * into r3(higher 32bit) and r4(lower 32bit)
899 */
900get_phys_addr:
901	mfmsr	r8
902	mfspr	r9,SPRN_PID
903	rlwinm	r9,r9,16,0x3fff0000	/* turn PID into MAS6[SPID] */
904	rlwimi	r9,r8,28,0x00000001	/* turn MSR[DS] into MAS6[SAS] */
905	mtspr	SPRN_MAS6,r9
906
907	tlbsx	0,r3			/* must succeed */
908
909	mfspr	r8,SPRN_MAS1
910	mfspr	r12,SPRN_MAS3
911	rlwinm	r9,r8,25,0x1f		/* r9 = log2(page size) */
912	li	r10,1024
913	slw	r10,r10,r9		/* r10 = page size */
914	addi	r10,r10,-1
915	and	r11,r3,r10		/* r11 = page offset */
916	andc	r4,r12,r10		/* r4 = page base */
917	or	r4,r4,r11		/* r4 = devtree phys addr */
918#ifdef CONFIG_PHYS_64BIT
919	mfspr	r3,SPRN_MAS7
920#endif
921	blr
922
923/*
924 * Global functions
925 */
926
927#ifdef CONFIG_E200
928/* Adjust or setup IVORs for e200 */
929_GLOBAL(__setup_e200_ivors)
930	li	r3,DebugDebug@l
931	mtspr	SPRN_IVOR15,r3
932	li	r3,SPEUnavailable@l
933	mtspr	SPRN_IVOR32,r3
934	li	r3,SPEFloatingPointData@l
935	mtspr	SPRN_IVOR33,r3
936	li	r3,SPEFloatingPointRound@l
937	mtspr	SPRN_IVOR34,r3
938	sync
939	blr
940#endif
941
942#ifdef CONFIG_E500
943#ifndef CONFIG_PPC_E500MC
944/* Adjust or setup IVORs for e500v1/v2 */
945_GLOBAL(__setup_e500_ivors)
946	li	r3,DebugCrit@l
947	mtspr	SPRN_IVOR15,r3
948	li	r3,SPEUnavailable@l
949	mtspr	SPRN_IVOR32,r3
950	li	r3,SPEFloatingPointData@l
951	mtspr	SPRN_IVOR33,r3
952	li	r3,SPEFloatingPointRound@l
953	mtspr	SPRN_IVOR34,r3
954	li	r3,PerformanceMonitor@l
955	mtspr	SPRN_IVOR35,r3
956	sync
957	blr
958#else
959/* Adjust or setup IVORs for e500mc */
960_GLOBAL(__setup_e500mc_ivors)
961	li	r3,DebugDebug@l
962	mtspr	SPRN_IVOR15,r3
963	li	r3,PerformanceMonitor@l
964	mtspr	SPRN_IVOR35,r3
965	li	r3,Doorbell@l
966	mtspr	SPRN_IVOR36,r3
967	li	r3,CriticalDoorbell@l
968	mtspr	SPRN_IVOR37,r3
969	sync
970	blr
971
972/* setup ehv ivors for */
973_GLOBAL(__setup_ehv_ivors)
974	li	r3,GuestDoorbell@l
975	mtspr	SPRN_IVOR38,r3
976	li	r3,CriticalGuestDoorbell@l
977	mtspr	SPRN_IVOR39,r3
978	li	r3,Hypercall@l
979	mtspr	SPRN_IVOR40,r3
980	li	r3,Ehvpriv@l
981	mtspr	SPRN_IVOR41,r3
982	sync
983	blr
984#endif /* CONFIG_PPC_E500MC */
985#endif /* CONFIG_E500 */
986
987#ifdef CONFIG_SPE
988/*
989 * extern void __giveup_spe(struct task_struct *prev)
990 *
991 */
992_GLOBAL(__giveup_spe)
993	addi	r3,r3,THREAD		/* want THREAD of task */
994	lwz	r5,PT_REGS(r3)
995	cmpi	0,r5,0
996	SAVE_32EVRS(0, r4, r3, THREAD_EVR0)
997	evxor	evr6, evr6, evr6	/* clear out evr6 */
998	evmwumiaa evr6, evr6, evr6	/* evr6 <- ACC = 0 * 0 + ACC */
999	li	r4,THREAD_ACC
1000	evstddx	evr6, r4, r3		/* save off accumulator */
1001	beq	1f
1002	lwz	r4,_MSR-STACK_FRAME_OVERHEAD(r5)
1003	lis	r3,MSR_SPE@h
1004	andc	r4,r4,r3		/* disable SPE for previous task */
1005	stw	r4,_MSR-STACK_FRAME_OVERHEAD(r5)
10061:
1007	blr
1008#endif /* CONFIG_SPE */
1009
1010/*
1011 * extern void abort(void)
1012 *
1013 * At present, this routine just applies a system reset.
1014 */
1015_GLOBAL(abort)
1016	li	r13,0
1017	mtspr	SPRN_DBCR0,r13		/* disable all debug events */
1018	isync
1019	mfmsr	r13
1020	ori	r13,r13,MSR_DE@l	/* Enable Debug Events */
1021	mtmsr	r13
1022	isync
1023	mfspr	r13,SPRN_DBCR0
1024	lis	r13,(DBCR0_IDM|DBCR0_RST_CHIP)@h
1025	mtspr	SPRN_DBCR0,r13
1026	isync
1027
1028_GLOBAL(set_context)
1029
1030#ifdef CONFIG_BDI_SWITCH
1031	/* Context switch the PTE pointer for the Abatron BDI2000.
1032	 * The PGDIR is the second parameter.
1033	 */
1034	lis	r5, abatron_pteptrs@h
1035	ori	r5, r5, abatron_pteptrs@l
1036	stw	r4, 0x4(r5)
1037#endif
1038	mtspr	SPRN_PID,r3
1039	isync			/* Force context change */
1040	blr
1041
1042#ifdef CONFIG_SMP
1043/* When we get here, r24 needs to hold the CPU # */
1044	.globl __secondary_start
1045__secondary_start:
1046	LOAD_REG_ADDR_PIC(r3, tlbcam_index)
1047	lwz	r3,0(r3)
1048	mtctr	r3
1049	li	r26,0		/* r26 safe? */
1050
1051	bl	switch_to_as1
1052	mr	r27,r3		/* tlb entry */
1053	/* Load each CAM entry */
10541:	mr	r3,r26
1055	bl	loadcam_entry
1056	addi	r26,r26,1
1057	bdnz	1b
1058	mr	r3,r27		/* tlb entry */
1059	LOAD_REG_ADDR_PIC(r4, memstart_addr)
1060	lwz	r4,0(r4)
1061	mr	r5,r25		/* phys kernel start */
1062	rlwinm	r5,r5,0,~0x3ffffff	/* aligned 64M */
1063	subf	r4,r5,r4	/* memstart_addr - phys kernel start */
1064	li	r5,0		/* no device tree */
1065	li	r6,0		/* not boot cpu */
1066	bl	restore_to_as0
1067
1068
1069	lis	r3,__secondary_hold_acknowledge@h
1070	ori	r3,r3,__secondary_hold_acknowledge@l
1071	stw	r24,0(r3)
1072
1073	li	r3,0
1074	mr	r4,r24		/* Why? */
1075	bl	call_setup_cpu
1076
1077	/* get current_thread_info and current */
1078	lis	r1,secondary_ti@ha
1079	lwz	r1,secondary_ti@l(r1)
1080	lwz	r2,TI_TASK(r1)
1081
1082	/* stack */
1083	addi	r1,r1,THREAD_SIZE-STACK_FRAME_OVERHEAD
1084	li	r0,0
1085	stw	r0,0(r1)
1086
1087	/* ptr to current thread */
1088	addi	r4,r2,THREAD	/* address of our thread_struct */
1089	mtspr	SPRN_SPRG_THREAD,r4
1090
1091	/* Setup the defaults for TLB entries */
1092	li	r4,(MAS4_TSIZED(BOOK3E_PAGESZ_4K))@l
1093	mtspr	SPRN_MAS4,r4
1094
1095	/* Jump to start_secondary */
1096	lis	r4,MSR_KERNEL@h
1097	ori	r4,r4,MSR_KERNEL@l
1098	lis	r3,start_secondary@h
1099	ori	r3,r3,start_secondary@l
1100	mtspr	SPRN_SRR0,r3
1101	mtspr	SPRN_SRR1,r4
1102	sync
1103	rfi
1104	sync
1105
1106	.globl __secondary_hold_acknowledge
1107__secondary_hold_acknowledge:
1108	.long	-1
1109#endif
1110
1111/*
1112 * Create a tlb entry with the same effective and physical address as
1113 * the tlb entry used by the current running code. But set the TS to 1.
1114 * Then switch to the address space 1. It will return with the r3 set to
1115 * the ESEL of the new created tlb.
1116 */
1117_GLOBAL(switch_to_as1)
1118	mflr	r5
1119
1120	/* Find a entry not used */
1121	mfspr	r3,SPRN_TLB1CFG
1122	andi.	r3,r3,0xfff
1123	mfspr	r4,SPRN_PID
1124	rlwinm	r4,r4,16,0x3fff0000	/* turn PID into MAS6[SPID] */
1125	mtspr	SPRN_MAS6,r4
11261:	lis	r4,0x1000		/* Set MAS0(TLBSEL) = 1 */
1127	addi	r3,r3,-1
1128	rlwimi	r4,r3,16,4,15		/* Setup MAS0 = TLBSEL | ESEL(r3) */
1129	mtspr	SPRN_MAS0,r4
1130	tlbre
1131	mfspr	r4,SPRN_MAS1
1132	andis.	r4,r4,MAS1_VALID@h
1133	bne	1b
1134
1135	/* Get the tlb entry used by the current running code */
1136	bl	0f
11370:	mflr	r4
1138	tlbsx	0,r4
1139
1140	mfspr	r4,SPRN_MAS1
1141	ori	r4,r4,MAS1_TS		/* Set the TS = 1 */
1142	mtspr	SPRN_MAS1,r4
1143
1144	mfspr	r4,SPRN_MAS0
1145	rlwinm	r4,r4,0,~MAS0_ESEL_MASK
1146	rlwimi	r4,r3,16,4,15		/* Setup MAS0 = TLBSEL | ESEL(r3) */
1147	mtspr	SPRN_MAS0,r4
1148	tlbwe
1149	isync
1150	sync
1151
1152	mfmsr	r4
1153	ori	r4,r4,MSR_IS | MSR_DS
1154	mtspr	SPRN_SRR0,r5
1155	mtspr	SPRN_SRR1,r4
1156	sync
1157	rfi
1158
1159/*
1160 * Restore to the address space 0 and also invalidate the tlb entry created
1161 * by switch_to_as1.
1162 * r3 - the tlb entry which should be invalidated
1163 * r4 - __pa(PAGE_OFFSET in AS1) - __pa(PAGE_OFFSET in AS0)
1164 * r5 - device tree virtual address. If r4 is 0, r5 is ignored.
1165 * r6 - boot cpu
1166*/
1167_GLOBAL(restore_to_as0)
1168	mflr	r0
1169
1170	bl	0f
11710:	mflr	r9
1172	addi	r9,r9,1f - 0b
1173
1174	/*
1175	 * We may map the PAGE_OFFSET in AS0 to a different physical address,
1176	 * so we need calculate the right jump and device tree address based
1177	 * on the offset passed by r4.
1178	 */
1179	add	r9,r9,r4
1180	add	r5,r5,r4
1181	add	r0,r0,r4
1182
11832:	mfmsr	r7
1184	li	r8,(MSR_IS | MSR_DS)
1185	andc	r7,r7,r8
1186
1187	mtspr	SPRN_SRR0,r9
1188	mtspr	SPRN_SRR1,r7
1189	sync
1190	rfi
1191
1192	/* Invalidate the temporary tlb entry for AS1 */
11931:	lis	r9,0x1000		/* Set MAS0(TLBSEL) = 1 */
1194	rlwimi	r9,r3,16,4,15		/* Setup MAS0 = TLBSEL | ESEL(r3) */
1195	mtspr	SPRN_MAS0,r9
1196	tlbre
1197	mfspr	r9,SPRN_MAS1
1198	rlwinm	r9,r9,0,2,31		/* Clear MAS1 Valid and IPPROT */
1199	mtspr	SPRN_MAS1,r9
1200	tlbwe
1201	isync
1202
1203	cmpwi	r4,0
1204	cmpwi	cr1,r6,0
1205	cror	eq,4*cr1+eq,eq
1206	bne	3f			/* offset != 0 && is_boot_cpu */
1207	mtlr	r0
1208	blr
1209
1210	/*
1211	 * The PAGE_OFFSET will map to a different physical address,
1212	 * jump to _start to do another relocation again.
1213	*/
12143:	mr	r3,r5
1215	bl	_start
1216
1217/*
1218 * We put a few things here that have to be page-aligned. This stuff
1219 * goes at the beginning of the data segment, which is page-aligned.
1220 */
1221	.data
1222	.align	12
1223	.globl	sdata
1224sdata:
1225	.globl	empty_zero_page
1226empty_zero_page:
1227	.space	4096
1228EXPORT_SYMBOL(empty_zero_page)
1229	.globl	swapper_pg_dir
1230swapper_pg_dir:
1231	.space	PGD_TABLE_SIZE
1232
1233/*
1234 * Room for two PTE pointers, usually the kernel and current user pointers
1235 * to their respective root page table.
1236 */
1237abatron_pteptrs:
1238	.space	8
1239