1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Google Cheza device tree source (common between revisions) 4 * 5 * Copyright 2018 Google LLC. 6 */ 7 8#include <dt-bindings/input/input.h> 9#include <dt-bindings/regulator/qcom,rpmh-regulator.h> 10#include "sdm845.dtsi" 11 12/* PMICs depend on spmi_bus label and so must come after SoC */ 13#include "pm8005.dtsi" 14#include "pm8998.dtsi" 15 16/ { 17 aliases { 18 bluetooth0 = &bluetooth; 19 serial1 = &uart6; 20 serial0 = &uart9; 21 wifi0 = &wifi; 22 }; 23 24 chosen { 25 stdout-path = "serial0:115200n8"; 26 }; 27 28 backlight: backlight { 29 compatible = "pwm-backlight"; 30 pwms = <&cros_ec_pwm 0>; 31 enable-gpios = <&tlmm 37 GPIO_ACTIVE_HIGH>; 32 power-supply = <&ppvar_sys>; 33 pinctrl-names = "default"; 34 pinctrl-0 = <&ap_edp_bklten>; 35 }; 36 37 /* FIXED REGULATORS - parents above children */ 38 39 /* This is the top level supply and variable voltage */ 40 ppvar_sys: ppvar-sys-regulator { 41 compatible = "regulator-fixed"; 42 regulator-name = "ppvar_sys"; 43 regulator-always-on; 44 regulator-boot-on; 45 }; 46 47 /* This divides ppvar_sys by 2, so voltage is variable */ 48 src_vph_pwr: src-vph-pwr-regulator { 49 compatible = "regulator-fixed"; 50 regulator-name = "src_vph_pwr"; 51 52 /* EC turns on with switchcap_on_l; always on for AP */ 53 regulator-always-on; 54 regulator-boot-on; 55 56 vin-supply = <&ppvar_sys>; 57 }; 58 59 pp5000_a: pp5000-a-regulator { 60 compatible = "regulator-fixed"; 61 regulator-name = "pp5000_a"; 62 63 /* EC turns on with en_pp5000_a; always on for AP */ 64 regulator-always-on; 65 regulator-boot-on; 66 regulator-min-microvolt = <5000000>; 67 regulator-max-microvolt = <5000000>; 68 69 vin-supply = <&ppvar_sys>; 70 }; 71 72 src_vreg_bob: src-vreg-bob-regulator { 73 compatible = "regulator-fixed"; 74 regulator-name = "src_vreg_bob"; 75 76 /* EC turns on with vbob_en; always on for AP */ 77 regulator-always-on; 78 regulator-boot-on; 79 regulator-min-microvolt = <3600000>; 80 regulator-max-microvolt = <3600000>; 81 82 vin-supply = <&ppvar_sys>; 83 }; 84 85 pp3300_dx_edp: pp3300-dx-edp-regulator { 86 compatible = "regulator-fixed"; 87 regulator-name = "pp3300_dx_edp"; 88 89 regulator-min-microvolt = <3300000>; 90 regulator-max-microvolt = <3300000>; 91 92 gpio = <&tlmm 43 GPIO_ACTIVE_HIGH>; 93 enable-active-high; 94 pinctrl-names = "default"; 95 pinctrl-0 = <&en_pp3300_dx_edp>; 96 }; 97 98 /* 99 * Apparently RPMh does not provide support for PM8998 S4 because it 100 * is always-on; model it as a fixed regulator. 101 */ 102 src_pp1800_s4a: pm8998-smps4 { 103 compatible = "regulator-fixed"; 104 regulator-name = "src_pp1800_s4a"; 105 106 regulator-min-microvolt = <1800000>; 107 regulator-max-microvolt = <1800000>; 108 109 regulator-always-on; 110 regulator-boot-on; 111 112 vin-supply = <&src_vph_pwr>; 113 }; 114 115 /* BOARD-SPECIFIC TOP LEVEL NODES */ 116 117 gpio-keys { 118 compatible = "gpio-keys"; 119 pinctrl-names = "default"; 120 pinctrl-0 = <&pen_eject_odl>; 121 122 switch-pen-insert { 123 label = "Pen Insert"; 124 /* Insert = low, eject = high */ 125 gpios = <&tlmm 119 GPIO_ACTIVE_LOW>; 126 linux,code = <SW_PEN_INSERTED>; 127 linux,input-type = <EV_SW>; 128 wakeup-source; 129 }; 130 }; 131 132 panel: panel { 133 compatible = "innolux,p120zdg-bf1"; 134 power-supply = <&pp3300_dx_edp>; 135 backlight = <&backlight>; 136 no-hpd; 137 138 panel_in: port { 139 panel_in_edp: endpoint { 140 remote-endpoint = <&sn65dsi86_out>; 141 }; 142 }; 143 }; 144}; 145 146&psci { 147 /delete-node/ cpu0; 148 /delete-node/ cpu1; 149 /delete-node/ cpu2; 150 /delete-node/ cpu3; 151 /delete-node/ cpu4; 152 /delete-node/ cpu5; 153 /delete-node/ cpu6; 154 /delete-node/ cpu7; 155 /delete-node/ cpu-cluster0; 156}; 157 158&cpus { 159 /delete-node/ domain-idle-states; 160}; 161 162&cpu_idle_states { 163 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { 164 compatible = "arm,idle-state"; 165 idle-state-name = "little-power-down"; 166 arm,psci-suspend-param = <0x40000003>; 167 entry-latency-us = <350>; 168 exit-latency-us = <461>; 169 min-residency-us = <1890>; 170 local-timer-stop; 171 }; 172 173 LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 { 174 compatible = "arm,idle-state"; 175 idle-state-name = "little-rail-power-down"; 176 arm,psci-suspend-param = <0x40000004>; 177 entry-latency-us = <360>; 178 exit-latency-us = <531>; 179 min-residency-us = <3934>; 180 local-timer-stop; 181 }; 182 183 BIG_CPU_SLEEP_0: cpu-sleep-1-0 { 184 compatible = "arm,idle-state"; 185 idle-state-name = "big-power-down"; 186 arm,psci-suspend-param = <0x40000003>; 187 entry-latency-us = <264>; 188 exit-latency-us = <621>; 189 min-residency-us = <952>; 190 local-timer-stop; 191 }; 192 193 BIG_CPU_SLEEP_1: cpu-sleep-1-1 { 194 compatible = "arm,idle-state"; 195 idle-state-name = "big-rail-power-down"; 196 arm,psci-suspend-param = <0x40000004>; 197 entry-latency-us = <702>; 198 exit-latency-us = <1061>; 199 min-residency-us = <4488>; 200 local-timer-stop; 201 }; 202 203 CLUSTER_SLEEP_0: cluster-sleep-0 { 204 compatible = "arm,idle-state"; 205 idle-state-name = "cluster-power-down"; 206 arm,psci-suspend-param = <0x400000F4>; 207 entry-latency-us = <3263>; 208 exit-latency-us = <6562>; 209 min-residency-us = <9987>; 210 local-timer-stop; 211 }; 212}; 213 214&CPU0 { 215 /delete-property/ power-domains; 216 /delete-property/ power-domain-names; 217 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 218 &LITTLE_CPU_SLEEP_1 219 &CLUSTER_SLEEP_0>; 220}; 221 222&CPU1 { 223 /delete-property/ power-domains; 224 /delete-property/ power-domain-names; 225 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 226 &LITTLE_CPU_SLEEP_1 227 &CLUSTER_SLEEP_0>; 228}; 229 230&CPU2 { 231 /delete-property/ power-domains; 232 /delete-property/ power-domain-names; 233 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 234 &LITTLE_CPU_SLEEP_1 235 &CLUSTER_SLEEP_0>; 236}; 237 238&CPU3 { 239 /delete-property/ power-domains; 240 /delete-property/ power-domain-names; 241 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 242 &LITTLE_CPU_SLEEP_1 243 &CLUSTER_SLEEP_0>; 244}; 245 246&CPU4 { 247 /delete-property/ power-domains; 248 /delete-property/ power-domain-names; 249 cpu-idle-states = <&BIG_CPU_SLEEP_0 250 &BIG_CPU_SLEEP_1 251 &CLUSTER_SLEEP_0>; 252}; 253 254&CPU5 { 255 /delete-property/ power-domains; 256 /delete-property/ power-domain-names; 257 cpu-idle-states = <&BIG_CPU_SLEEP_0 258 &BIG_CPU_SLEEP_1 259 &CLUSTER_SLEEP_0>; 260}; 261 262&CPU6 { 263 /delete-property/ power-domains; 264 /delete-property/ power-domain-names; 265 cpu-idle-states = <&BIG_CPU_SLEEP_0 266 &BIG_CPU_SLEEP_1 267 &CLUSTER_SLEEP_0>; 268}; 269 270&CPU7 { 271 /delete-property/ power-domains; 272 /delete-property/ power-domain-names; 273 cpu-idle-states = <&BIG_CPU_SLEEP_0 274 &BIG_CPU_SLEEP_1 275 &CLUSTER_SLEEP_0>; 276}; 277 278/* 279 * Reserved memory changes 280 * 281 * Putting this all together (out of order with the rest of the file) to keep 282 * all modifications to the memory map (from sdm845.dtsi) in one place. 283 */ 284 285/* 286 * Our mpss_region is 8MB bigger than the default one and that conflicts 287 * with venus_mem and cdsp_mem. 288 * 289 * For venus_mem we'll delete and re-create at a different address. 290 * 291 * cdsp_mem isn't used on cheza right now so we won't bother re-creating it; but 292 * that also means we need to delete cdsp_pas. 293 */ 294/delete-node/ &venus_mem; 295/delete-node/ &cdsp_mem; 296/delete-node/ &cdsp_pas; 297/delete-node/ &gpu_mem; 298 299/* Increase the size from 120 MB to 128 MB */ 300&mpss_region { 301 reg = <0 0x8e000000 0 0x8000000>; 302}; 303 304/* Increase the size from 2MB to 8MB */ 305&rmtfs_mem { 306 reg = <0 0x88f00000 0 0x800000>; 307}; 308 309/ { 310 reserved-memory { 311 venus_mem: memory@96000000 { 312 reg = <0 0x96000000 0 0x500000>; 313 no-map; 314 }; 315 }; 316}; 317 318&qspi { 319 status = "okay"; 320 pinctrl-names = "default", "sleep"; 321 pinctrl-0 = <&qspi_clk>, <&qspi_cs0>, <&qspi_data0>, <&qspi_data1>; 322 pinctrl-1 = <&qspi_sleep>; 323 324 flash@0 { 325 compatible = "jedec,spi-nor"; 326 reg = <0>; 327 328 /* 329 * In theory chip supports up to 104 MHz and controller up 330 * to 80 MHz, but above 25 MHz wasn't reliable so we'll use 331 * that for now. b:117440651 332 */ 333 spi-max-frequency = <25000000>; 334 spi-tx-bus-width = <2>; 335 spi-rx-bus-width = <2>; 336 }; 337}; 338 339 340&apps_rsc { 341 regulators-0 { 342 compatible = "qcom,pm8998-rpmh-regulators"; 343 qcom,pmic-id = "a"; 344 345 vdd-s1-supply = <&src_vph_pwr>; 346 vdd-s2-supply = <&src_vph_pwr>; 347 vdd-s3-supply = <&src_vph_pwr>; 348 vdd-s4-supply = <&src_vph_pwr>; 349 vdd-s5-supply = <&src_vph_pwr>; 350 vdd-s6-supply = <&src_vph_pwr>; 351 vdd-s7-supply = <&src_vph_pwr>; 352 vdd-s8-supply = <&src_vph_pwr>; 353 vdd-s9-supply = <&src_vph_pwr>; 354 vdd-s10-supply = <&src_vph_pwr>; 355 vdd-s11-supply = <&src_vph_pwr>; 356 vdd-s12-supply = <&src_vph_pwr>; 357 vdd-s13-supply = <&src_vph_pwr>; 358 vdd-l1-l27-supply = <&src_pp1025_s7a>; 359 vdd-l2-l8-l17-supply = <&src_pp1350_s3a>; 360 vdd-l3-l11-supply = <&src_pp1025_s7a>; 361 vdd-l4-l5-supply = <&src_pp1025_s7a>; 362 vdd-l6-supply = <&src_vph_pwr>; 363 vdd-l7-l12-l14-l15-supply = <&src_pp2040_s5a>; 364 vdd-l9-supply = <&src_pp2040_s5a>; 365 vdd-l10-l23-l25-supply = <&src_vreg_bob>; 366 vdd-l13-l19-l21-supply = <&src_vreg_bob>; 367 vdd-l16-l28-supply = <&src_vreg_bob>; 368 vdd-l18-l22-supply = <&src_vreg_bob>; 369 vdd-l20-l24-supply = <&src_vreg_bob>; 370 vdd-l26-supply = <&src_pp1350_s3a>; 371 vin-lvs-1-2-supply = <&src_pp1800_s4a>; 372 373 src_pp1125_s2a: smps2 { 374 regulator-min-microvolt = <1100000>; 375 regulator-max-microvolt = <1100000>; 376 }; 377 378 src_pp1350_s3a: smps3 { 379 regulator-min-microvolt = <1352000>; 380 regulator-max-microvolt = <1352000>; 381 }; 382 383 src_pp2040_s5a: smps5 { 384 regulator-min-microvolt = <1904000>; 385 regulator-max-microvolt = <2040000>; 386 }; 387 388 src_pp1025_s7a: smps7 { 389 regulator-min-microvolt = <900000>; 390 regulator-max-microvolt = <1028000>; 391 }; 392 393 vdd_qusb_hs0: 394 vdda_hp_pcie_core: 395 vdda_mipi_csi0_0p9: 396 vdda_mipi_csi1_0p9: 397 vdda_mipi_csi2_0p9: 398 vdda_mipi_dsi0_pll: 399 vdda_mipi_dsi1_pll: 400 vdda_qlink_lv: 401 vdda_qlink_lv_ck: 402 vdda_qrefs_0p875: 403 vdda_pcie_core: 404 vdda_pll_cc_ebi01: 405 vdda_pll_cc_ebi23: 406 vdda_sp_sensor: 407 vdda_ufs1_core: 408 vdda_ufs2_core: 409 vdda_usb1_ss_core: 410 vdda_usb2_ss_core: 411 src_pp875_l1a: ldo1 { 412 regulator-min-microvolt = <880000>; 413 regulator-max-microvolt = <880000>; 414 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 415 }; 416 417 vddpx_10: 418 src_pp1200_l2a: ldo2 { 419 regulator-min-microvolt = <1200000>; 420 regulator-max-microvolt = <1200000>; 421 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 422 423 /* TODO: why??? */ 424 regulator-always-on; 425 }; 426 427 pp1000_l3a_sdr845: ldo3 { 428 regulator-min-microvolt = <1000000>; 429 regulator-max-microvolt = <1000000>; 430 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 431 }; 432 433 vdd_wcss_cx: 434 vdd_wcss_mx: 435 vdda_wcss_pll: 436 src_pp800_l5a: ldo5 { 437 regulator-min-microvolt = <800000>; 438 regulator-max-microvolt = <800000>; 439 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 440 }; 441 442 vddpx_13: 443 src_pp1800_l6a: ldo6 { 444 regulator-min-microvolt = <1856000>; 445 regulator-max-microvolt = <1856000>; 446 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 447 }; 448 449 pp1800_l7a_wcn3990: ldo7 { 450 regulator-min-microvolt = <1800000>; 451 regulator-max-microvolt = <1800000>; 452 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 453 }; 454 455 src_pp1200_l8a: ldo8 { 456 regulator-min-microvolt = <1200000>; 457 regulator-max-microvolt = <1248000>; 458 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 459 }; 460 461 pp1800_dx_pen: 462 src_pp1800_l9a: ldo9 { 463 regulator-min-microvolt = <1800000>; 464 regulator-max-microvolt = <1800000>; 465 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 466 }; 467 468 src_pp1800_l10a: ldo10 { 469 regulator-min-microvolt = <1800000>; 470 regulator-max-microvolt = <1800000>; 471 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 472 }; 473 474 pp1000_l11a_sdr845: ldo11 { 475 regulator-min-microvolt = <1000000>; 476 regulator-max-microvolt = <1048000>; 477 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 478 }; 479 480 vdd_qfprom: 481 vdd_qfprom_sp: 482 vdda_apc1_cs_1p8: 483 vdda_gfx_cs_1p8: 484 vdda_qrefs_1p8: 485 vdda_qusb_hs0_1p8: 486 vddpx_11: 487 src_pp1800_l12a: ldo12 { 488 regulator-min-microvolt = <1800000>; 489 regulator-max-microvolt = <1800000>; 490 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 491 }; 492 493 vddpx_2: 494 src_pp2950_l13a: ldo13 { 495 regulator-min-microvolt = <1800000>; 496 regulator-max-microvolt = <2960000>; 497 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 498 }; 499 500 src_pp1800_l14a: ldo14 { 501 regulator-min-microvolt = <1800000>; 502 regulator-max-microvolt = <1800000>; 503 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 504 }; 505 506 src_pp1800_l15a: ldo15 { 507 regulator-min-microvolt = <1800000>; 508 regulator-max-microvolt = <1800000>; 509 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 510 }; 511 512 pp2700_l16a: ldo16 { 513 regulator-min-microvolt = <2704000>; 514 regulator-max-microvolt = <2704000>; 515 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 516 }; 517 518 src_pp1300_l17a: ldo17 { 519 regulator-min-microvolt = <1304000>; 520 regulator-max-microvolt = <1304000>; 521 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 522 }; 523 524 pp2700_l18a: ldo18 { 525 regulator-min-microvolt = <2704000>; 526 regulator-max-microvolt = <2960000>; 527 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 528 }; 529 530 /* 531 * NOTE: this rail should have been called 532 * src_pp3300_l19a in the schematic 533 */ 534 src_pp3000_l19a: ldo19 { 535 regulator-min-microvolt = <3304000>; 536 regulator-max-microvolt = <3304000>; 537 538 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 539 }; 540 541 src_pp2950_l20a: ldo20 { 542 regulator-min-microvolt = <2704000>; 543 regulator-max-microvolt = <2960000>; 544 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 545 }; 546 547 src_pp2950_l21a: ldo21 { 548 regulator-min-microvolt = <2704000>; 549 regulator-max-microvolt = <2960000>; 550 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 551 }; 552 553 pp3300_hub: 554 src_pp3300_l22a: ldo22 { 555 regulator-min-microvolt = <3304000>; 556 regulator-max-microvolt = <3304000>; 557 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 558 /* 559 * HACK: Should add a usb hub node and driver 560 * to turn this on and off at suspend/resume time 561 */ 562 regulator-boot-on; 563 regulator-always-on; 564 }; 565 566 pp3300_l23a_ch1_wcn3990: ldo23 { 567 regulator-min-microvolt = <3000000>; 568 regulator-max-microvolt = <3312000>; 569 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 570 }; 571 572 vdda_qusb_hs0_3p1: 573 src_pp3075_l24a: ldo24 { 574 regulator-min-microvolt = <3088000>; 575 regulator-max-microvolt = <3088000>; 576 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 577 }; 578 579 pp3300_l25a_ch0_wcn3990: ldo25 { 580 regulator-min-microvolt = <3304000>; 581 regulator-max-microvolt = <3304000>; 582 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 583 }; 584 585 pp1200_hub: 586 vdda_hp_pcie_1p2: 587 vdda_hv_ebi0: 588 vdda_hv_ebi1: 589 vdda_hv_ebi2: 590 vdda_hv_ebi3: 591 vdda_mipi_csi_1p25: 592 vdda_mipi_dsi0_1p2: 593 vdda_mipi_dsi1_1p2: 594 vdda_pcie_1p2: 595 vdda_ufs1_1p2: 596 vdda_ufs2_1p2: 597 vdda_usb1_ss_1p2: 598 vdda_usb2_ss_1p2: 599 src_pp1200_l26a: ldo26 { 600 regulator-min-microvolt = <1200000>; 601 regulator-max-microvolt = <1200000>; 602 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 603 }; 604 605 pp3300_dx_pen: 606 src_pp3300_l28a: ldo28 { 607 regulator-min-microvolt = <3304000>; 608 regulator-max-microvolt = <3304000>; 609 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 610 }; 611 612 src_pp1800_lvs1: lvs1 { 613 regulator-min-microvolt = <1800000>; 614 regulator-max-microvolt = <1800000>; 615 }; 616 617 src_pp1800_lvs2: lvs2 { 618 regulator-min-microvolt = <1800000>; 619 regulator-max-microvolt = <1800000>; 620 }; 621 }; 622 623 regulators-1 { 624 compatible = "qcom,pm8005-rpmh-regulators"; 625 qcom,pmic-id = "c"; 626 627 vdd-s1-supply = <&src_vph_pwr>; 628 vdd-s2-supply = <&src_vph_pwr>; 629 vdd-s3-supply = <&src_vph_pwr>; 630 vdd-s4-supply = <&src_vph_pwr>; 631 632 src_pp600_s3c: smps3 { 633 regulator-min-microvolt = <600000>; 634 regulator-max-microvolt = <600000>; 635 }; 636 }; 637}; 638 639edp_brij_i2c: &i2c3 { 640 status = "okay"; 641 clock-frequency = <400000>; 642 643 sn65dsi86_bridge: bridge@2d { 644 compatible = "ti,sn65dsi86"; 645 reg = <0x2d>; 646 pinctrl-names = "default"; 647 pinctrl-0 = <&edp_brij_en &edp_brij_irq>; 648 649 interrupt-parent = <&tlmm>; 650 interrupts = <10 IRQ_TYPE_LEVEL_HIGH>; 651 652 enable-gpios = <&tlmm 102 GPIO_ACTIVE_HIGH>; 653 654 vpll-supply = <&src_pp1800_s4a>; 655 vccio-supply = <&src_pp1800_s4a>; 656 vcca-supply = <&src_pp1200_l2a>; 657 vcc-supply = <&src_pp1200_l2a>; 658 659 clocks = <&rpmhcc RPMH_LN_BB_CLK2>; 660 clock-names = "refclk"; 661 662 no-hpd; 663 664 ports { 665 #address-cells = <1>; 666 #size-cells = <0>; 667 668 port@0 { 669 reg = <0>; 670 sn65dsi86_in: endpoint { 671 remote-endpoint = <&mdss_dsi0_out>; 672 }; 673 }; 674 675 port@1 { 676 reg = <1>; 677 sn65dsi86_out: endpoint { 678 remote-endpoint = <&panel_in_edp>; 679 }; 680 }; 681 }; 682 }; 683}; 684 685ap_pen_1v8: &i2c11 { 686 status = "okay"; 687 clock-frequency = <400000>; 688 689 digitizer@9 { 690 compatible = "wacom,w9013", "hid-over-i2c"; 691 reg = <0x9>; 692 pinctrl-names = "default"; 693 pinctrl-0 = <&pen_irq_l>, <&pen_pdct_l>, <&pen_rst_l>; 694 695 vdd-supply = <&pp3300_dx_pen>; 696 vddl-supply = <&pp1800_dx_pen>; 697 post-power-on-delay-ms = <100>; 698 699 interrupt-parent = <&tlmm>; 700 interrupts = <24 IRQ_TYPE_LEVEL_LOW>; 701 702 hid-descr-addr = <0x1>; 703 }; 704}; 705 706amp_i2c: &i2c12 { 707 status = "okay"; 708 clock-frequency = <400000>; 709}; 710 711ap_ts_i2c: &i2c14 { 712 status = "okay"; 713 clock-frequency = <400000>; 714 715 touchscreen@10 { 716 compatible = "elan,ekth3500"; 717 reg = <0x10>; 718 pinctrl-names = "default"; 719 pinctrl-0 = <&ts_int_l &ts_reset_l>; 720 721 interrupt-parent = <&tlmm>; 722 interrupts = <125 IRQ_TYPE_LEVEL_LOW>; 723 724 vcc33-supply = <&src_pp3300_l28a>; 725 726 reset-gpios = <&tlmm 118 GPIO_ACTIVE_LOW>; 727 }; 728}; 729 730&gmu { 731 status = "okay"; 732}; 733 734&gpu { 735 status = "okay"; 736}; 737 738&ipa { 739 qcom,gsi-loader = "modem"; 740 status = "okay"; 741}; 742 743&lpasscc { 744 status = "okay"; 745}; 746 747&mdss { 748 status = "okay"; 749}; 750 751&mdss_dsi0 { 752 status = "okay"; 753 vdda-supply = <&vdda_mipi_dsi0_1p2>; 754 755 ports { 756 port@1 { 757 endpoint { 758 remote-endpoint = <&sn65dsi86_in>; 759 data-lanes = <0 1 2 3>; 760 }; 761 }; 762 }; 763}; 764 765&mdss_dsi0_phy { 766 status = "okay"; 767 vdds-supply = <&vdda_mipi_dsi0_pll>; 768}; 769 770/* 771 * Cheza fw does not properly program the GPU aperture to allow the 772 * GPU to update the SMMU pagetables for context switches. Work 773 * around this by dropping the "qcom,adreno-smmu" compat string. 774 */ 775&adreno_smmu { 776 compatible = "qcom,sdm845-smmu-v2", "qcom,smmu-v2"; 777}; 778 779&mss_pil { 780 status = "okay"; 781 782 iommus = <&apps_smmu 0x781 0x0>, 783 <&apps_smmu 0x724 0x3>; 784}; 785 786&pm8998_pwrkey { 787 status = "disabled"; 788}; 789 790&qupv3_id_0 { 791 status = "okay"; 792 iommus = <&apps_smmu 0x0 0x3>; 793}; 794 795&qupv3_id_1 { 796 status = "okay"; 797 iommus = <&apps_smmu 0x6c0 0x3>; 798}; 799 800&sdhc_2 { 801 status = "okay"; 802 803 pinctrl-names = "default"; 804 pinctrl-0 = <&sdc2_clk &sdc2_cmd &sdc2_data &sd_cd_odl>; 805 806 vmmc-supply = <&src_pp2950_l21a>; 807 vqmmc-supply = <&vddpx_2>; 808 809 cd-gpios = <&tlmm 44 GPIO_ACTIVE_LOW>; 810}; 811 812&spi0 { 813 status = "okay"; 814}; 815 816&spi5 { 817 status = "okay"; 818 819 tpm@0 { 820 compatible = "google,cr50"; 821 reg = <0>; 822 pinctrl-names = "default"; 823 pinctrl-0 = <&h1_ap_int_odl>; 824 spi-max-frequency = <800000>; 825 interrupt-parent = <&tlmm>; 826 interrupts = <129 IRQ_TYPE_EDGE_RISING>; 827 }; 828}; 829 830&spi10 { 831 status = "okay"; 832 833 cros_ec: ec@0 { 834 compatible = "google,cros-ec-spi"; 835 reg = <0>; 836 interrupt-parent = <&tlmm>; 837 interrupts = <122 IRQ_TYPE_LEVEL_LOW>; 838 pinctrl-names = "default"; 839 pinctrl-0 = <&ec_ap_int_l>; 840 spi-max-frequency = <3000000>; 841 842 cros_ec_pwm: pwm { 843 compatible = "google,cros-ec-pwm"; 844 #pwm-cells = <1>; 845 }; 846 847 i2c_tunnel: i2c-tunnel { 848 compatible = "google,cros-ec-i2c-tunnel"; 849 google,remote-bus = <0>; 850 #address-cells = <1>; 851 #size-cells = <0>; 852 }; 853 }; 854}; 855 856#include <arm/cros-ec-keyboard.dtsi> 857#include <arm/cros-ec-sbs.dtsi> 858 859&uart6 { 860 status = "okay"; 861 862 pinctrl-0 = <&qup_uart6_4pin>; 863 864 bluetooth: bluetooth { 865 compatible = "qcom,wcn3990-bt"; 866 vddio-supply = <&src_pp1800_s4a>; 867 vddxo-supply = <&pp1800_l7a_wcn3990>; 868 vddrf-supply = <&src_pp1300_l17a>; 869 vddch0-supply = <&pp3300_l25a_ch0_wcn3990>; 870 max-speed = <3200000>; 871 }; 872}; 873 874&uart9 { 875 status = "okay"; 876}; 877 878&ufs_mem_hc { 879 status = "okay"; 880 881 reset-gpios = <&tlmm 150 GPIO_ACTIVE_LOW>; 882 883 vcc-supply = <&src_pp2950_l20a>; 884 vcc-max-microamp = <600000>; 885}; 886 887&ufs_mem_phy { 888 status = "okay"; 889 890 vdda-phy-supply = <&vdda_ufs1_core>; 891 vdda-pll-supply = <&vdda_ufs1_1p2>; 892}; 893 894&usb_1 { 895 status = "okay"; 896 897 /* We'll use this as USB 2.0 only */ 898 qcom,select-utmi-as-pipe-clk; 899}; 900 901&usb_1_dwc3 { 902 /* 903 * The hardware design intends this port to be hooked up in peripheral 904 * mode, so we'll hardcode it here. Some details: 905 * - SDM845 expects only a single Type C connector so it has only one 906 * native Type C port but cheza has two Type C connectors. 907 * - The only source of DP is the single native Type C port. 908 * - On cheza we want to be able to hook DP up to _either_ of the 909 * two Type C connectors and want to be able to achieve 4 lanes of DP. 910 * - When you configure a Type C port for 4 lanes of DP you lose USB3. 911 * - In order to make everything work, the native Type C port is always 912 * configured as 4-lanes DP so it's always available. 913 * - The extra USB3 port on SDM845 goes to a USB 3 hub which is then 914 * sent to the two Type C connectors. 915 * - The extra USB2 lines from the native Type C port are always 916 * setup as "peripheral" so that we can mux them over to one connector 917 * or the other if someone needs the connector configured as a gadget 918 * (but they only get USB2 speeds). 919 * 920 * All the hardware muxes would allow us to hook things up in different 921 * ways to some potential benefit for static configurations (you could 922 * achieve extra USB2 bandwidth by using two different ports for the 923 * two connectors or possibly even get USB3 peripheral mode), but in 924 * each case you end up forcing to disconnect/reconnect an in-use 925 * USB session in some cases depending on what you hotplug into the 926 * other connector. Thus hardcoding this as peripheral makes sense. 927 */ 928 dr_mode = "peripheral"; 929 930 /* 931 * We always need the high speed pins as 4-lanes DP in case someone 932 * hotplugs a DP peripheral. Thus limit this port to a max of high 933 * speed. 934 */ 935 maximum-speed = "high-speed"; 936 937 /* 938 * We don't need the usb3-phy since we run in highspeed mode always, so 939 * re-define these properties removing the superspeed USB PHY reference. 940 */ 941 phys = <&usb_1_hsphy>; 942 phy-names = "usb2-phy"; 943}; 944 945&usb_1_hsphy { 946 status = "okay"; 947 948 vdd-supply = <&vdda_usb1_ss_core>; 949 vdda-pll-supply = <&vdda_qusb_hs0_1p8>; 950 vdda-phy-dpdm-supply = <&vdda_qusb_hs0_3p1>; 951 952 qcom,imp-res-offset-value = <8>; 953 qcom,hstx-trim-value = <QUSB2_V2_HSTX_TRIM_21_6_MA>; 954 qcom,preemphasis-level = <QUSB2_V2_PREEMPHASIS_5_PERCENT>; 955 qcom,preemphasis-width = <QUSB2_V2_PREEMPHASIS_WIDTH_HALF_BIT>; 956}; 957 958&usb_2 { 959 status = "okay"; 960}; 961 962&usb_2_dwc3 { 963 /* We have this hooked up to a hub and we always use in host mode */ 964 dr_mode = "host"; 965}; 966 967&usb_2_hsphy { 968 status = "okay"; 969 970 vdd-supply = <&vdda_usb2_ss_core>; 971 vdda-pll-supply = <&vdda_qusb_hs0_1p8>; 972 vdda-phy-dpdm-supply = <&vdda_qusb_hs0_3p1>; 973 974 qcom,imp-res-offset-value = <8>; 975 qcom,hstx-trim-value = <QUSB2_V2_HSTX_TRIM_22_8_MA>; 976}; 977 978&usb_2_qmpphy { 979 status = "okay"; 980 981 vdda-phy-supply = <&vdda_usb2_ss_1p2>; 982 vdda-pll-supply = <&vdda_usb2_ss_core>; 983}; 984 985&wifi { 986 status = "okay"; 987 988 vdd-0.8-cx-mx-supply = <&src_pp800_l5a >; 989 vdd-1.8-xo-supply = <&pp1800_l7a_wcn3990>; 990 vdd-1.3-rfa-supply = <&src_pp1300_l17a>; 991 vdd-3.3-ch0-supply = <&pp3300_l25a_ch0_wcn3990>; 992}; 993 994/* PINCTRL - additions to nodes defined in sdm845.dtsi */ 995 996&qspi_cs0 { 997 bias-disable; /* External pullup */ 998}; 999 1000&qspi_clk { 1001 bias-disable; /* Rely on Cr50 internal pulldown */ 1002}; 1003 1004&qspi_data0 { 1005 bias-disable; /* Rely on Cr50 internal pulldown */ 1006}; 1007 1008&qspi_data1 { 1009 bias-pull-down; 1010}; 1011 1012&qup_i2c3_default { 1013 drive-strength = <2>; 1014 1015 /* Has external pullup */ 1016 bias-disable; 1017}; 1018 1019&qup_i2c11_default { 1020 drive-strength = <2>; 1021 1022 /* Has external pullup */ 1023 bias-disable; 1024}; 1025 1026&qup_i2c12_default { 1027 drive-strength = <2>; 1028 1029 /* Has external pullup */ 1030 bias-disable; 1031}; 1032 1033&qup_i2c14_default { 1034 drive-strength = <2>; 1035 1036 /* Has external pullup */ 1037 bias-disable; 1038}; 1039 1040&qup_spi0_default { 1041 drive-strength = <2>; 1042 bias-disable; 1043}; 1044 1045&qup_spi5_default { 1046 drive-strength = <2>; 1047 bias-disable; 1048}; 1049 1050&qup_spi10_default { 1051 drive-strength = <2>; 1052 bias-disable; 1053}; 1054 1055&qup_uart9_rx { 1056 drive-strength = <2>; 1057 bias-pull-up; 1058}; 1059 1060&qup_uart9_tx { 1061 drive-strength = <2>; 1062 bias-disable; 1063}; 1064 1065/* PINCTRL - board-specific pinctrl */ 1066&pm8005_gpios { 1067 gpio-line-names = "", 1068 "", 1069 "SLB", 1070 ""; 1071}; 1072 1073&pm8998_adc { 1074 channel@4d { 1075 reg = <ADC5_AMUX_THM1_100K_PU>; 1076 label = "sdm_temp"; 1077 }; 1078 1079 channel@4e { 1080 reg = <ADC5_AMUX_THM2_100K_PU>; 1081 label = "quiet_temp"; 1082 }; 1083 1084 channel@4f { 1085 reg = <ADC5_AMUX_THM3_100K_PU>; 1086 label = "lte_temp_1"; 1087 }; 1088 1089 channel@50 { 1090 reg = <ADC5_AMUX_THM4_100K_PU>; 1091 label = "lte_temp_2"; 1092 }; 1093 1094 channel@51 { 1095 reg = <ADC5_AMUX_THM5_100K_PU>; 1096 label = "charger_temp"; 1097 }; 1098}; 1099 1100&pm8998_gpios { 1101 gpio-line-names = "", 1102 "", 1103 "SW_CTRL", 1104 "", 1105 "", 1106 "", 1107 "", 1108 "", 1109 "", 1110 "", 1111 "", 1112 "", 1113 "", 1114 "", 1115 "", 1116 "", 1117 "", 1118 "", 1119 "", 1120 "", 1121 "", 1122 "CFG_OPT1", 1123 "WCSS_PWR_REQ", 1124 "", 1125 "CFG_OPT2", 1126 "SLB"; 1127}; 1128 1129&tlmm { 1130 /* 1131 * pinctrl settings for pins that have no real owners. 1132 */ 1133 pinctrl-names = "default", "sleep"; 1134 pinctrl-0 = <&bios_flash_wp_r_l>, 1135 <&ap_suspend_l_deassert>; 1136 1137 pinctrl-1 = <&bios_flash_wp_r_l>, 1138 <&ap_suspend_l_assert>; 1139 1140 /* 1141 * Hogs prevent usermode from changing the value. A GPIO can be both 1142 * here and in the pinctrl section. 1143 */ 1144 ap-suspend-l-hog { 1145 gpio-hog; 1146 gpios = <126 GPIO_ACTIVE_LOW>; 1147 output-low; 1148 }; 1149 1150 ap_edp_bklten: ap-edp-bklten-state { 1151 pins = "gpio37"; 1152 function = "gpio"; 1153 drive-strength = <2>; 1154 bias-disable; 1155 }; 1156 1157 bios_flash_wp_r_l: bios-flash-wp-r-l-state { 1158 pins = "gpio128"; 1159 function = "gpio"; 1160 bias-disable; 1161 }; 1162 1163 ec_ap_int_l: ec-ap-int-l-state { 1164 pins = "gpio122"; 1165 function = "gpio"; 1166 bias-pull-up; 1167 }; 1168 1169 edp_brij_en: edp-brij-en-state { 1170 pins = "gpio102"; 1171 function = "gpio"; 1172 drive-strength = <2>; 1173 bias-disable; 1174 }; 1175 1176 edp_brij_irq: edp-brij-irq-state { 1177 pins = "gpio10"; 1178 function = "gpio"; 1179 drive-strength = <2>; 1180 bias-pull-down; 1181 }; 1182 1183 en_pp3300_dx_edp: en-pp3300-dx-edp-state { 1184 pins = "gpio43"; 1185 function = "gpio"; 1186 drive-strength = <2>; 1187 bias-disable; 1188 }; 1189 1190 h1_ap_int_odl: h1-ap-int-odl-state { 1191 pins = "gpio129"; 1192 function = "gpio"; 1193 bias-pull-up; 1194 }; 1195 1196 pen_eject_odl: pen-eject-odl-state { 1197 pins = "gpio119"; 1198 function = "gpio"; 1199 bias-pull-up; 1200 }; 1201 1202 pen_irq_l: pen-irq-l-state { 1203 pins = "gpio24"; 1204 function = "gpio"; 1205 1206 /* Has external pullup */ 1207 bias-disable; 1208 }; 1209 1210 pen_pdct_l: pen-pdct-l-state { 1211 pins = "gpio63"; 1212 function = "gpio"; 1213 1214 /* Has external pullup */ 1215 bias-disable; 1216 }; 1217 1218 pen_rst_l: pen-rst-l-state { 1219 pins = "gpio23"; 1220 function = "gpio"; 1221 bias-disable; 1222 drive-strength = <2>; 1223 1224 /* 1225 * The pen driver doesn't currently support 1226 * driving this reset line. By specifying 1227 * output-high here we're relying on the fact 1228 * that this pin has a default pulldown at boot 1229 * (which makes sure the pen was in reset if it 1230 * was powered) and then we set it high here to 1231 * take it out of reset. Better would be if the 1232 * pen driver could control this and we could 1233 * remove "output-high" here. 1234 */ 1235 output-high; 1236 }; 1237 1238 qspi_sleep: qspi-sleep-state { 1239 pins = "gpio90", "gpio91", "gpio92", "gpio95"; 1240 1241 /* 1242 * When we're not actively transferring we want pins as GPIOs 1243 * with output disabled so that the quad SPI IP block stops 1244 * driving them. We rely on the normal pulls configured in 1245 * the active state and don't redefine them here. Also note 1246 * that we don't need the reverse (output-enable) in the 1247 * normal mode since the "output-enable" only matters for 1248 * GPIO function. 1249 */ 1250 function = "gpio"; 1251 output-disable; 1252 }; 1253 1254 sdc2_clk: sdc2-clk-state { 1255 pins = "sdc2_clk"; 1256 bias-disable; 1257 1258 /* 1259 * It seems that mmc_test reports errors if drive 1260 * strength is not 16. 1261 */ 1262 drive-strength = <16>; 1263 }; 1264 1265 sdc2_cmd: sdc2-cmd-state { 1266 pins = "sdc2_cmd"; 1267 bias-pull-up; 1268 drive-strength = <16>; 1269 }; 1270 1271 sdc2_data: sdc2-data-state { 1272 pins = "sdc2_data"; 1273 bias-pull-up; 1274 drive-strength = <16>; 1275 }; 1276 1277 sd_cd_odl: sd-cd-odl-state { 1278 pins = "gpio44"; 1279 function = "gpio"; 1280 bias-pull-up; 1281 }; 1282 1283 ts_int_l: ts-int-l-state { 1284 pins = "gpio125"; 1285 function = "gpio"; 1286 bias-pull-up; 1287 }; 1288 1289 ts_reset_l: ts-reset-l-state { 1290 pins = "gpio118"; 1291 function = "gpio"; 1292 bias-disable; 1293 drive-strength = <2>; 1294 }; 1295 1296 ap_suspend_l_assert: ap-suspend-l-assert-state { 1297 pins = "gpio126"; 1298 function = "gpio"; 1299 bias-disable; 1300 drive-strength = <2>; 1301 output-low; 1302 }; 1303 1304 ap_suspend_l_deassert: ap-suspend-l-deassert-state { 1305 pins = "gpio126"; 1306 function = "gpio"; 1307 bias-disable; 1308 drive-strength = <2>; 1309 output-high; 1310 }; 1311}; 1312 1313&venus { 1314 status = "okay"; 1315 1316 video-firmware { 1317 iommus = <&apps_smmu 0x10b2 0x0>; 1318 }; 1319}; 1320
