1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * RDA8810PL SoC
4 *
5 * Copyright (c) 2017 Andreas Färber
6 * Copyright (c) 2018 Manivannan Sadhasivam
7 */
8
9#include <dt-bindings/interrupt-controller/irq.h>
10
11/ {
12	compatible = "rda,8810pl";
13	interrupt-parent = <&intc>;
14	#address-cells = <1>;
15	#size-cells = <1>;
16
17	cpus {
18		#address-cells = <1>;
19		#size-cells = <0>;
20
21		cpu@0 {
22			device_type = "cpu";
23			compatible = "arm,cortex-a5";
24			reg = <0x0>;
25		};
26	};
27
28	sram@100000 {
29		compatible = "mmio-sram";
30		reg = <0x100000 0x10000>;
31		#address-cells = <1>;
32		#size-cells = <1>;
33		ranges;
34	};
35
36	apb@20800000 {
37		compatible = "simple-bus";
38		#address-cells = <1>;
39		#size-cells = <1>;
40		ranges = <0x0 0x20800000 0x100000>;
41
42		intc: interrupt-controller@0 {
43			compatible = "rda,8810pl-intc";
44			reg = <0x0 0x1000>;
45			interrupt-controller;
46			#interrupt-cells = <2>;
47		};
48	};
49
50	apb@20900000 {
51		compatible = "simple-bus";
52		#address-cells = <1>;
53		#size-cells = <1>;
54		ranges = <0x0 0x20900000 0x100000>;
55
56		timer@10000 {
57			compatible = "rda,8810pl-timer";
58			reg = <0x10000 0x1000>;
59			interrupts = <16 IRQ_TYPE_LEVEL_HIGH>,
60				     <17 IRQ_TYPE_LEVEL_HIGH>;
61			interrupt-names = "hwtimer", "ostimer";
62		};
63	};
64
65	apb@20a00000 {
66		compatible = "simple-bus";
67		#address-cells = <1>;
68		#size-cells = <1>;
69		ranges = <0x0 0x20a00000 0x100000>;
70
71		uart1: serial@0 {
72			compatible = "rda,8810pl-uart";
73			reg = <0x0 0x1000>;
74			interrupts = <9 IRQ_TYPE_LEVEL_HIGH>;
75			status = "disabled";
76		};
77
78		uart2: serial@10000 {
79			compatible = "rda,8810pl-uart";
80			reg = <0x10000 0x1000>;
81			interrupts = <10 IRQ_TYPE_LEVEL_HIGH>;
82			status = "disabled";
83		};
84
85		uart3: serial@90000 {
86			compatible = "rda,8810pl-uart";
87			reg = <0x90000 0x1000>;
88			interrupts = <11 IRQ_TYPE_LEVEL_HIGH>;
89			status = "disabled";
90		};
91	};
92
93	l2: cache-controller@21100000 {
94		compatible = "arm,pl310-cache";
95		reg = <0x21100000 0x1000>;
96		cache-unified;
97		cache-level = <2>;
98	};
99};
100