1// SPDX-License-Identifier: GPL-2.0
2/include/ "skeleton.dtsi"
3
4#include <dt-bindings/gpio/gpio.h>
5#include <dt-bindings/interrupt-controller/irq.h>
6
7#define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16))
8
9/ {
10	compatible = "marvell,dove";
11	model = "Marvell Armada 88AP510 SoC";
12	interrupt-parent = <&intc>;
13
14	aliases {
15		gpio0 = &gpio0;
16		gpio1 = &gpio1;
17		gpio2 = &gpio2;
18	};
19
20	cpus {
21		#address-cells = <1>;
22		#size-cells = <0>;
23
24		cpu0: cpu@0 {
25			compatible = "marvell,pj4a", "marvell,sheeva-v7";
26			device_type = "cpu";
27			next-level-cache = <&l2>;
28			reg = <0>;
29		};
30	};
31
32	l2: l2-cache {
33		compatible = "marvell,tauros2-cache";
34		marvell,tauros2-cache-features = <0>;
35	};
36
37	gpu-subsystem {
38		compatible = "marvell,dove-gpu-subsystem";
39		cores = <&gpu>;
40		status = "disabled";
41	};
42
43	i2c-mux {
44		compatible = "i2c-mux-pinctrl";
45		#address-cells = <1>;
46		#size-cells = <0>;
47
48		i2c-parent = <&i2c>;
49
50		pinctrl-names = "i2c0", "i2c1", "i2c2";
51		pinctrl-0 = <&pmx_i2cmux_0>;
52		pinctrl-1 = <&pmx_i2cmux_1>;
53		pinctrl-2 = <&pmx_i2cmux_2>;
54
55		i2c0: i2c@0 {
56			reg = <0>;
57			#address-cells = <1>;
58			#size-cells = <0>;
59			status = "okay";
60		};
61
62		i2c1: i2c@1 {
63			reg = <1>;
64			#address-cells = <1>;
65			#size-cells = <0>;
66			/* Requires pmx_i2c1 on i2c controller node */
67			status = "disabled";
68		};
69
70		i2c2: i2c@2 {
71			reg = <2>;
72			#address-cells = <1>;
73			#size-cells = <0>;
74			/* Requires pmx_i2c2 on i2c controller node */
75			status = "disabled";
76		};
77	};
78
79	mbus {
80		compatible = "marvell,dove-mbus", "marvell,mbus", "simple-bus";
81		#address-cells = <2>;
82		#size-cells = <1>;
83		controller = <&mbusc>;
84		pcie-mem-aperture = <0xe0000000 0x10000000>; /* 256M MEM space */
85		pcie-io-aperture  = <0xf2000000 0x00200000>; /*   2M I/O space */
86
87		ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x0100000   /* MBUS regs  1M */
88			  MBUS_ID(0xf0, 0x02) 0 0xf1800000 0x1000000   /* AXI  regs 16M */
89			  MBUS_ID(0x01, 0xfd) 0 0xf8000000 0x8000000   /* BootROM  128M */
90			  MBUS_ID(0x03, 0x01) 0 0xc8000000 0x0100000   /* CESA SRAM  1M */
91			  MBUS_ID(0x0d, 0x00) 0 0xf0000000 0x0100000>; /* PMU  SRAM  1M */
92
93		pcie: pcie {
94			compatible = "marvell,dove-pcie";
95			status = "disabled";
96			device_type = "pci";
97			#address-cells = <3>;
98			#size-cells = <2>;
99
100			msi-parent = <&intc>;
101			bus-range = <0x00 0xff>;
102
103			ranges = <0x82000000 0x0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x2000
104			          0x82000000 0x0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x2000
105				  0x82000000 0x1 0x0 MBUS_ID(0x04, 0xe8) 0 1 0   /* Port 0.0 Mem */
106				  0x81000000 0x1 0x0 MBUS_ID(0x04, 0xe0) 0 1 0   /* Port 0.0 I/O */
107				  0x82000000 0x2 0x0 MBUS_ID(0x08, 0xe8) 0 1 0   /* Port 1.0 Mem */
108				  0x81000000 0x2 0x0 MBUS_ID(0x08, 0xe0) 0 1 0>; /* Port 1.0 I/O */
109
110			pcie0: pcie@1 {
111				device_type = "pci";
112				status = "disabled";
113				assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
114				reg = <0x0800 0 0 0 0>;
115				clocks = <&gate_clk 4>;
116				marvell,pcie-port = <0>;
117
118				#address-cells = <3>;
119				#size-cells = <2>;
120				ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
121				          0x81000000 0 0 0x81000000 0x1 0 1 0>;
122				bus-range = <0x00 0xff>;
123
124				#interrupt-cells = <1>;
125				interrupt-map-mask = <0 0 0 0>;
126				interrupt-map = <0 0 0 0 &intc 16>;
127			};
128
129			pcie1: pcie@2 {
130				device_type = "pci";
131				status = "disabled";
132				assigned-addresses = <0x82002800 0 0x80000 0 0x2000>;
133				reg = <0x1000 0 0 0 0>;
134				clocks = <&gate_clk 5>;
135				marvell,pcie-port = <1>;
136
137				#address-cells = <3>;
138				#size-cells = <2>;
139				ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
140				          0x81000000 0 0 0x81000000 0x2 0 1 0>;
141				bus-range = <0x00 0xff>;
142
143				#interrupt-cells = <1>;
144				interrupt-map-mask = <0 0 0 0>;
145				interrupt-map = <0 0 0 0 &intc 18>;
146			};
147		};
148
149		internal-regs {
150			compatible = "simple-bus";
151			#address-cells = <1>;
152			#size-cells = <1>;
153			ranges = <0x00000000 MBUS_ID(0xf0, 0x01) 0 0x0100000   /* MBUS regs  1M */
154				  0x00800000 MBUS_ID(0xf0, 0x02) 0 0x1000000   /* AXI  regs 16M */
155				  0xffffe000 MBUS_ID(0x03, 0x01) 0 0x0000800   /* CESA SRAM  2k */
156				  0xfffff000 MBUS_ID(0x0d, 0x00) 0 0x0000800>; /* PMU  SRAM  2k */
157
158			spi0: spi-ctrl@10600 {
159				compatible = "marvell,orion-spi";
160				#address-cells = <1>;
161				#size-cells = <0>;
162				cell-index = <0>;
163				interrupts = <6>;
164				reg = <0x10600 0x28>;
165				clocks = <&core_clk 0>;
166				pinctrl-0 = <&pmx_spi0>;
167				pinctrl-names = "default";
168				status = "disabled";
169			};
170
171			i2c: i2c-ctrl@11000 {
172				compatible = "marvell,mv64xxx-i2c";
173				reg = <0x11000 0x20>;
174				#address-cells = <1>;
175				#size-cells = <0>;
176				interrupts = <11>;
177				clock-frequency = <400000>;
178				timeout-ms = <1000>;
179				clocks = <&core_clk 0>;
180				status = "okay";
181			};
182
183			uart0: serial@12000 {
184				compatible = "ns16550a";
185				reg = <0x12000 0x100>;
186				reg-shift = <2>;
187				interrupts = <7>;
188				clocks = <&core_clk 0>;
189				status = "disabled";
190			};
191
192			uart1: serial@12100 {
193				compatible = "ns16550a";
194				reg = <0x12100 0x100>;
195				reg-shift = <2>;
196				interrupts = <8>;
197				clocks = <&core_clk 0>;
198				pinctrl-0 = <&pmx_uart1>;
199				pinctrl-names = "default";
200				status = "disabled";
201			};
202
203			uart2: serial@12200 {
204				compatible = "ns16550a";
205				reg = <0x12200 0x100>;
206				reg-shift = <2>;
207				interrupts = <9>;
208				clocks = <&core_clk 0>;
209				status = "disabled";
210			};
211
212			uart3: serial@12300 {
213				compatible = "ns16550a";
214				reg = <0x12300 0x100>;
215				reg-shift = <2>;
216				interrupts = <10>;
217				clocks = <&core_clk 0>;
218				status = "disabled";
219			};
220
221			spi1: spi-ctrl@14600 {
222				compatible = "marvell,orion-spi";
223				#address-cells = <1>;
224				#size-cells = <0>;
225				cell-index = <1>;
226				interrupts = <5>;
227				reg = <0x14600 0x28>;
228				clocks = <&core_clk 0>;
229				status = "disabled";
230			};
231
232			mbusc: mbus-ctrl@20000 {
233				compatible = "marvell,mbus-controller";
234				reg = <0x20000 0x80>, <0x800100 0x8>;
235			};
236
237			sysc: system-ctrl@20000 {
238				compatible = "marvell,orion-system-controller";
239				reg = <0x20000 0x110>;
240			};
241
242			bridge_intc: bridge-interrupt-ctrl@20110 {
243				compatible = "marvell,orion-bridge-intc";
244				interrupt-controller;
245				#interrupt-cells = <1>;
246				reg = <0x20110 0x8>;
247				interrupts = <0>;
248				marvell,#interrupts = <5>;
249			};
250
251			intc: main-interrupt-ctrl@20200 {
252				compatible = "marvell,orion-intc";
253				interrupt-controller;
254				#interrupt-cells = <1>;
255				reg = <0x20200 0x10>, <0x20210 0x10>;
256			};
257
258			timer: timer@20300 {
259				compatible = "marvell,orion-timer";
260				reg = <0x20300 0x20>;
261				interrupt-parent = <&bridge_intc>;
262				interrupts = <1>, <2>;
263				clocks = <&core_clk 0>;
264			};
265
266			watchdog@20300 {
267				compatible = "marvell,orion-wdt";
268				reg = <0x20300 0x28>, <0x20108 0x4>;
269				interrupt-parent = <&bridge_intc>;
270				interrupts = <3>;
271				clocks = <&core_clk 0>;
272			};
273
274			crypto: crypto-engine@30000 {
275				compatible = "marvell,dove-crypto";
276				reg = <0x30000 0x10000>;
277				reg-names = "regs";
278				interrupts = <31>;
279				clocks = <&gate_clk 15>;
280				marvell,crypto-srams = <&crypto_sram>;
281				marvell,crypto-sram-size = <0x800>;
282				status = "okay";
283			};
284
285			ehci0: usb-host@50000 {
286				compatible = "marvell,orion-ehci";
287				reg = <0x50000 0x1000>;
288				interrupts = <24>;
289				clocks = <&gate_clk 0>;
290				status = "okay";
291			};
292
293			ehci1: usb-host@51000 {
294				compatible = "marvell,orion-ehci";
295				reg = <0x51000 0x1000>;
296				interrupts = <25>;
297				clocks = <&gate_clk 1>;
298				status = "okay";
299			};
300
301			xor0: dma-engine@60800 {
302				compatible = "marvell,orion-xor";
303				reg = <0x60800 0x100
304				       0x60a00 0x100>;
305				clocks = <&gate_clk 23>;
306				status = "okay";
307
308				channel0 {
309					interrupts = <39>;
310					dmacap,memcpy;
311					dmacap,xor;
312				};
313
314				channel1 {
315					interrupts = <40>;
316					dmacap,memcpy;
317					dmacap,xor;
318				};
319			};
320
321			xor1: dma-engine@60900 {
322				compatible = "marvell,orion-xor";
323				reg = <0x60900 0x100
324				       0x60b00 0x100>;
325				clocks = <&gate_clk 24>;
326				status = "okay";
327
328				channel0 {
329					interrupts = <42>;
330					dmacap,memcpy;
331					dmacap,xor;
332				};
333
334				channel1 {
335					interrupts = <43>;
336					dmacap,memcpy;
337					dmacap,xor;
338				};
339			};
340
341			sdio1: sdio-host@90000 {
342				compatible = "marvell,dove-sdhci";
343				reg = <0x90000 0x100>;
344				interrupts = <36>, <38>;
345				clocks = <&gate_clk 9>;
346				pinctrl-0 = <&pmx_sdio1>;
347				pinctrl-names = "default";
348				status = "disabled";
349			};
350
351			eth: ethernet-ctrl@72000 {
352				compatible = "marvell,orion-eth";
353				#address-cells = <1>;
354				#size-cells = <0>;
355				reg = <0x72000 0x4000>;
356				clocks = <&gate_clk 2>;
357				marvell,tx-checksum-limit = <1600>;
358				status = "disabled";
359
360				ethernet-port@0 {
361					compatible = "marvell,orion-eth-port";
362					reg = <0>;
363					interrupts = <29>;
364					/* overwrite MAC address in bootloader */
365					local-mac-address = [00 00 00 00 00 00];
366					phy-handle = <&ethphy>;
367				};
368			};
369
370			mdio: mdio-bus@72004 {
371				compatible = "marvell,orion-mdio";
372				#address-cells = <1>;
373				#size-cells = <0>;
374				reg = <0x72004 0x84>;
375				interrupts = <30>;
376				clocks = <&gate_clk 2>;
377				status = "disabled";
378
379				ethphy: ethernet-phy {
380					/* set phy address in board file */
381				};
382			};
383
384			sdio0: sdio-host@92000 {
385				compatible = "marvell,dove-sdhci";
386				reg = <0x92000 0x100>;
387				interrupts = <35>, <37>;
388				clocks = <&gate_clk 8>;
389				pinctrl-0 = <&pmx_sdio0>;
390				pinctrl-names = "default";
391				status = "disabled";
392			};
393
394			sata0: sata-host@a0000 {
395				compatible = "marvell,orion-sata";
396				reg = <0xa0000 0x2400>;
397				interrupts = <62>;
398				clocks = <&gate_clk 3>;
399				phys = <&sata_phy0>;
400				phy-names = "port0";
401				nr-ports = <1>;
402				status = "disabled";
403			};
404
405			sata_phy0: sata-phy@a2000 {
406				compatible = "marvell,mvebu-sata-phy";
407				reg = <0xa2000 0x0334>;
408				clocks = <&gate_clk 3>;
409				clock-names = "sata";
410				#phy-cells = <0>;
411				status = "ok";
412			};
413
414			audio0: audio-controller@b0000 {
415				compatible = "marvell,dove-audio";
416				reg = <0xb0000 0x2210>;
417				interrupts = <19>, <20>;
418				clocks = <&gate_clk 12>;
419				clock-names = "internal";
420				status = "disabled";
421			};
422
423			audio1: audio-controller@b4000 {
424				compatible = "marvell,dove-audio";
425				reg = <0xb4000 0x2210>;
426				interrupts = <21>, <22>;
427				clocks = <&gate_clk 13>;
428				clock-names = "internal";
429				status = "disabled";
430			};
431
432			pmu: power-management@d0000 {
433				compatible = "marvell,dove-pmu", "simple-bus";
434				reg = <0xd0000 0x8000>, <0xd8000 0x8000>;
435				ranges = <0x00000000 0x000d0000 0x8000
436					  0x00008000 0x000d8000 0x8000>;
437				interrupts = <33>;
438				interrupt-controller;
439				#address-cells = <1>;
440				#size-cells = <1>;
441				#interrupt-cells = <1>;
442				#reset-cells = <1>;
443
444				domains {
445					vpu_domain: vpu-domain {
446						#power-domain-cells = <0>;
447						marvell,pmu_pwr_mask = <0x00000008>;
448						marvell,pmu_iso_mask = <0x00000001>;
449						resets = <&pmu 16>;
450					};
451
452					gpu_domain: gpu-domain {
453						#power-domain-cells = <0>;
454						marvell,pmu_pwr_mask = <0x00000004>;
455						marvell,pmu_iso_mask = <0x00000002>;
456						resets = <&pmu 18>;
457					};
458				};
459
460				thermal: thermal-diode@1c {
461					compatible = "marvell,dove-thermal";
462					reg = <0x001c 0x0c>, <0x005c 0x08>;
463				};
464
465				gate_clk: clock-gating-ctrl@38 {
466					compatible = "marvell,dove-gating-clock";
467					reg = <0x0038 0x4>;
468					clocks = <&core_clk 0>;
469					#clock-cells = <1>;
470				};
471
472				divider_clk: core-clock@64 {
473					compatible = "marvell,dove-divider-clock";
474					reg = <0x0064 0x8>;
475					#clock-cells = <1>;
476				};
477
478				pinctrl: pin-ctrl@200 {
479					compatible = "marvell,dove-pinctrl";
480					reg = <0x0200 0x14>,
481					      <0x0440 0x04>;
482					clocks = <&gate_clk 22>;
483
484					pmx_gpio_0: pmx-gpio-0 {
485						marvell,pins = "mpp0";
486						marvell,function = "gpio";
487					};
488
489					pmx_gpio_1: pmx-gpio-1 {
490						marvell,pins = "mpp1";
491						marvell,function = "gpio";
492					};
493
494					pmx_gpio_2: pmx-gpio-2 {
495						marvell,pins = "mpp2";
496						marvell,function = "gpio";
497					};
498
499					pmx_gpio_3: pmx-gpio-3 {
500						marvell,pins = "mpp3";
501						marvell,function = "gpio";
502					};
503
504					pmx_gpio_4: pmx-gpio-4 {
505						marvell,pins = "mpp4";
506						marvell,function = "gpio";
507					};
508
509					pmx_gpio_5: pmx-gpio-5 {
510						marvell,pins = "mpp5";
511						marvell,function = "gpio";
512					};
513
514					pmx_gpio_6: pmx-gpio-6 {
515						marvell,pins = "mpp6";
516						marvell,function = "gpio";
517					};
518
519					pmx_gpio_7: pmx-gpio-7 {
520						marvell,pins = "mpp7";
521						marvell,function = "gpio";
522					};
523
524					pmx_gpio_8: pmx-gpio-8 {
525						marvell,pins = "mpp8";
526						marvell,function = "gpio";
527					};
528
529					pmx_gpio_9: pmx-gpio-9 {
530						marvell,pins = "mpp9";
531						marvell,function = "gpio";
532					};
533
534					pmx_pcie1_clkreq: pmx-pcie1-clkreq {
535						marvell,pins = "mpp9";
536						marvell,function = "pex1";
537					};
538
539					pmx_gpio_10: pmx-gpio-10 {
540						marvell,pins = "mpp10";
541						marvell,function = "gpio";
542					};
543
544					pmx_gpio_11: pmx-gpio-11 {
545						marvell,pins = "mpp11";
546						marvell,function = "gpio";
547					};
548
549					pmx_pcie0_clkreq: pmx-pcie0-clkreq {
550						marvell,pins = "mpp11";
551						marvell,function = "pex0";
552					};
553
554					pmx_gpio_12: pmx-gpio-12 {
555						marvell,pins = "mpp12";
556						marvell,function = "gpio";
557					};
558
559					pmx_gpio_13: pmx-gpio-13 {
560						marvell,pins = "mpp13";
561						marvell,function = "gpio";
562					};
563
564					pmx_audio1_extclk: pmx-audio1-extclk {
565						marvell,pins = "mpp13";
566						marvell,function = "audio1";
567					};
568
569					pmx_gpio_14: pmx-gpio-14 {
570						marvell,pins = "mpp14";
571						marvell,function = "gpio";
572					};
573
574					pmx_gpio_15: pmx-gpio-15 {
575						marvell,pins = "mpp15";
576						marvell,function = "gpio";
577					};
578
579					pmx_gpio_16: pmx-gpio-16 {
580						marvell,pins = "mpp16";
581						marvell,function = "gpio";
582					};
583
584					pmx_gpio_17: pmx-gpio-17 {
585						marvell,pins = "mpp17";
586						marvell,function = "gpio";
587					};
588
589					pmx_gpio_18: pmx-gpio-18 {
590						marvell,pins = "mpp18";
591						marvell,function = "gpio";
592					};
593
594					pmx_gpio_19: pmx-gpio-19 {
595						marvell,pins = "mpp19";
596						marvell,function = "gpio";
597					};
598
599					pmx_gpio_20: pmx-gpio-20 {
600						marvell,pins = "mpp20";
601						marvell,function = "gpio";
602					};
603
604					pmx_gpio_21: pmx-gpio-21 {
605						marvell,pins = "mpp21";
606						marvell,function = "gpio";
607					};
608
609					pmx_camera: pmx-camera {
610						marvell,pins = "mpp_camera";
611						marvell,function = "camera";
612					};
613
614					pmx_camera_gpio: pmx-camera-gpio {
615						marvell,pins = "mpp_camera";
616						marvell,function = "gpio";
617					};
618
619					pmx_sdio0: pmx-sdio0 {
620						marvell,pins = "mpp_sdio0";
621						marvell,function = "sdio0";
622					};
623
624					pmx_sdio0_gpio: pmx-sdio0-gpio {
625						marvell,pins = "mpp_sdio0";
626						marvell,function = "gpio";
627					};
628
629					pmx_sdio1: pmx-sdio1 {
630						marvell,pins = "mpp_sdio1";
631						marvell,function = "sdio1";
632					};
633
634					pmx_sdio1_gpio: pmx-sdio1-gpio {
635						marvell,pins = "mpp_sdio1";
636						marvell,function = "gpio";
637					};
638
639					pmx_audio1_gpio: pmx-audio1-gpio {
640						marvell,pins = "mpp_audio1";
641						marvell,function = "gpio";
642					};
643
644					pmx_audio1_i2s1_spdifo: pmx-audio1-i2s1-spdifo {
645						marvell,pins = "mpp_audio1";
646						marvell,function = "i2s1/spdifo";
647					};
648
649					pmx_spi0: pmx-spi0 {
650						marvell,pins = "mpp_spi0";
651						marvell,function = "spi0";
652					};
653
654					pmx_spi0_gpio: pmx-spi0-gpio {
655						marvell,pins = "mpp_spi0";
656						marvell,function = "gpio";
657					};
658
659					pmx_spi1_4_7: pmx-spi1-4-7 {
660						marvell,pins = "mpp4", "mpp5",
661							"mpp6", "mpp7";
662						marvell,function = "spi1";
663					};
664
665					pmx_spi1_20_23: pmx-spi1-20-23 {
666						marvell,pins = "mpp20", "mpp21",
667							"mpp22", "mpp23";
668						marvell,function = "spi1";
669					};
670
671					pmx_uart1: pmx-uart1 {
672						marvell,pins = "mpp_uart1";
673						marvell,function = "uart1";
674					};
675
676					pmx_uart1_gpio: pmx-uart1-gpio {
677						marvell,pins = "mpp_uart1";
678						marvell,function = "gpio";
679					};
680
681					pmx_nand: pmx-nand {
682						marvell,pins = "mpp_nand";
683						marvell,function = "nand";
684					};
685
686					pmx_nand_gpo: pmx-nand-gpo {
687						marvell,pins = "mpp_nand";
688						marvell,function = "gpo";
689					};
690
691					pmx_i2c1: pmx-i2c1 {
692						marvell,pins = "mpp17", "mpp19";
693						marvell,function = "twsi";
694					};
695
696					pmx_i2c2: pmx-i2c2 {
697						marvell,pins = "mpp_audio1";
698						marvell,function = "twsi";
699					};
700
701					pmx_ssp_i2c2: pmx-ssp-i2c2 {
702						marvell,pins = "mpp_audio1";
703						marvell,function = "ssp/twsi";
704					};
705
706					pmx_i2cmux_0: pmx-i2cmux-0 {
707						marvell,pins = "twsi";
708						marvell,function = "twsi-opt1";
709					};
710
711					pmx_i2cmux_1: pmx-i2cmux-1 {
712						marvell,pins = "twsi";
713						marvell,function = "twsi-opt2";
714					};
715
716					pmx_i2cmux_2: pmx-i2cmux-2 {
717						marvell,pins = "twsi";
718						marvell,function = "twsi-opt3";
719					};
720				};
721
722				core_clk: core-clocks@214 {
723					compatible = "marvell,dove-core-clock";
724					reg = <0x0214 0x4>;
725					#clock-cells = <1>;
726				};
727
728				gpio0: gpio-ctrl@400 {
729					compatible = "marvell,orion-gpio";
730					#gpio-cells = <2>;
731					gpio-controller;
732					reg = <0x0400 0x20>;
733					ngpios = <32>;
734					interrupt-controller;
735					#interrupt-cells = <2>;
736					interrupt-parent = <&intc>;
737					interrupts = <12>, <13>, <14>, <60>;
738				};
739
740				gpio1: gpio-ctrl@420 {
741					compatible = "marvell,orion-gpio";
742					#gpio-cells = <2>;
743					gpio-controller;
744					reg = <0x0420 0x20>;
745					ngpios = <32>;
746					interrupt-controller;
747					#interrupt-cells = <2>;
748					interrupt-parent = <&intc>;
749					interrupts = <61>;
750				};
751
752				rtc: real-time-clock@8500 {
753					compatible = "marvell,orion-rtc";
754					reg = <0x8500 0x20>;
755					interrupts = <5>;
756				};
757			};
758
759			gconf: global-config@e802c {
760				compatible = "marvell,dove-global-config",
761				             "syscon";
762				reg = <0xe802c 0x14>;
763			};
764
765			gpio2: gpio-ctrl@e8400 {
766				compatible = "marvell,orion-gpio";
767				#gpio-cells = <2>;
768				gpio-controller;
769				reg = <0xe8400 0x0c>;
770				ngpios = <8>;
771			};
772
773			lcd1: lcd-controller@810000 {
774				compatible = "marvell,dove-lcd";
775				reg = <0x810000 0x1000>;
776				interrupts = <46>;
777				status = "disabled";
778			};
779
780			lcd0: lcd-controller@820000 {
781				compatible = "marvell,dove-lcd";
782				reg = <0x820000 0x1000>;
783				interrupts = <47>;
784				status = "disabled";
785			};
786
787			crypto_sram: sa-sram@ffffe000 {
788				compatible = "mmio-sram";
789				reg = <0xffffe000 0x800>;
790				clocks = <&gate_clk 15>;
791				#address-cells = <1>;
792				#size-cells = <1>;
793			};
794
795			gpu: gpu@840000 {
796				clocks = <&divider_clk 1>;
797				clock-names = "core";
798				compatible = "vivante,gc";
799				interrupts = <48>;
800				power-domains = <&gpu_domain>;
801				reg = <0x840000 0x4000>;
802				status = "disabled";
803			};
804		};
805	};
806};
807