1/* 2 * Copyright 2012 DENX Software Engineering GmbH 3 * Heiko Schocher <hs@denx.de> 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of the GNU General Public License as published by the 7 * Free Software Foundation; either version 2 of the License, or (at your 8 * option) any later version. 9 */ 10#include <dt-bindings/interrupt-controller/irq.h> 11 12/ { 13 #address-cells = <1>; 14 #size-cells = <1>; 15 chosen { }; 16 aliases { }; 17 18 memory@c0000000 { 19 device_type = "memory"; 20 reg = <0xc0000000 0x0>; 21 }; 22 23 arm { 24 #address-cells = <1>; 25 #size-cells = <1>; 26 ranges; 27 intc: interrupt-controller@fffee000 { 28 compatible = "ti,cp-intc"; 29 interrupt-controller; 30 #interrupt-cells = <1>; 31 ti,intc-size = <101>; 32 reg = <0xfffee000 0x2000>; 33 }; 34 }; 35 clocks: clocks { 36 ref_clk: ref_clk { 37 compatible = "fixed-clock"; 38 #clock-cells = <0>; 39 clock-output-names = "ref_clk"; 40 }; 41 sata_refclk: sata_refclk { 42 compatible = "fixed-clock"; 43 #clock-cells = <0>; 44 clock-output-names = "sata_refclk"; 45 status = "disabled"; 46 }; 47 usb_refclkin: usb_refclkin { 48 compatible = "fixed-clock"; 49 #clock-cells = <0>; 50 clock-output-names = "usb_refclkin"; 51 status = "disabled"; 52 }; 53 }; 54 dsp: dsp@11800000 { 55 compatible = "ti,da850-dsp"; 56 reg = <0x11800000 0x40000>, 57 <0x11e00000 0x8000>, 58 <0x11f00000 0x8000>, 59 <0x01c14044 0x4>, 60 <0x01c14174 0x8>; 61 reg-names = "l2sram", "l1pram", "l1dram", "host1cfg", "chipsig"; 62 interrupt-parent = <&intc>; 63 interrupts = <28>; 64 clocks = <&psc0 15>; 65 resets = <&psc0 15>; 66 status = "disabled"; 67 }; 68 soc@1c00000 { 69 compatible = "simple-bus"; 70 model = "da850"; 71 #address-cells = <1>; 72 #size-cells = <1>; 73 ranges = <0x0 0x01c00000 0x400000>; 74 interrupt-parent = <&intc>; 75 76 psc0: clock-controller@10000 { 77 compatible = "ti,da850-psc0"; 78 reg = <0x10000 0x1000>; 79 #clock-cells = <1>; 80 #reset-cells = <1>; 81 #power-domain-cells = <1>; 82 clocks = <&pll0_sysclk 1>, <&pll0_sysclk 2>, 83 <&pll0_sysclk 4>, <&pll0_sysclk 6>, 84 <&async1_clk>; 85 clock-names = "pll0_sysclk1", "pll0_sysclk2", 86 "pll0_sysclk4", "pll0_sysclk6", 87 "async1"; 88 }; 89 pll0: clock-controller@11000 { 90 compatible = "ti,da850-pll0"; 91 reg = <0x11000 0x1000>; 92 clocks = <&ref_clk>, <&pll1_sysclk 3>; 93 clock-names = "clksrc", "extclksrc"; 94 95 pll0_pllout: pllout { 96 #clock-cells = <0>; 97 }; 98 pll0_sysclk: sysclk { 99 #clock-cells = <1>; 100 }; 101 pll0_auxclk: auxclk { 102 #clock-cells = <0>; 103 }; 104 pll0_obsclk: obsclk { 105 #clock-cells = <0>; 106 }; 107 }; 108 pmx_core: pinmux@14120 { 109 compatible = "pinctrl-single"; 110 reg = <0x14120 0x50>; 111 #pinctrl-cells = <2>; 112 pinctrl-single,bit-per-mux; 113 pinctrl-single,register-width = <32>; 114 pinctrl-single,function-mask = <0xf>; 115 /* pin base, nr pins & gpio function */ 116 pinctrl-single,gpio-range = <&range 0 17 0x8>, 117 <&range 17 8 0x4>, 118 <&range 26 8 0x4>, 119 <&range 34 80 0x8>, 120 <&range 129 31 0x8>; 121 status = "disabled"; 122 123 range: gpio-range { 124 #pinctrl-single,gpio-range-cells = <3>; 125 }; 126 127 serial0_rtscts_pins: pinmux_serial0_rtscts_pins { 128 pinctrl-single,bits = < 129 /* UART0_RTS UART0_CTS */ 130 0x0c 0x22000000 0xff000000 131 >; 132 }; 133 serial0_rxtx_pins: pinmux_serial0_rxtx_pins { 134 pinctrl-single,bits = < 135 /* UART0_TXD UART0_RXD */ 136 0x0c 0x00220000 0x00ff0000 137 >; 138 }; 139 serial1_rtscts_pins: pinmux_serial1_rtscts_pins { 140 pinctrl-single,bits = < 141 /* UART1_CTS UART1_RTS */ 142 0x00 0x00440000 0x00ff0000 143 >; 144 }; 145 serial1_rxtx_pins: pinmux_serial1_rxtx_pins { 146 pinctrl-single,bits = < 147 /* UART1_TXD UART1_RXD */ 148 0x10 0x22000000 0xff000000 149 >; 150 }; 151 serial2_rtscts_pins: pinmux_serial2_rtscts_pins { 152 pinctrl-single,bits = < 153 /* UART2_CTS UART2_RTS */ 154 0x00 0x44000000 0xff000000 155 >; 156 }; 157 serial2_rxtx_pins: pinmux_serial2_rxtx_pins { 158 pinctrl-single,bits = < 159 /* UART2_TXD UART2_RXD */ 160 0x10 0x00220000 0x00ff0000 161 >; 162 }; 163 i2c0_pins: pinmux_i2c0_pins { 164 pinctrl-single,bits = < 165 /* I2C0_SDA,I2C0_SCL */ 166 0x10 0x00002200 0x0000ff00 167 >; 168 }; 169 i2c1_pins: pinmux_i2c1_pins { 170 pinctrl-single,bits = < 171 /* I2C1_SDA, I2C1_SCL */ 172 0x10 0x00440000 0x00ff0000 173 >; 174 }; 175 mmc0_pins: pinmux_mmc_pins { 176 pinctrl-single,bits = < 177 /* MMCSD0_DAT[3] MMCSD0_DAT[2] 178 * MMCSD0_DAT[1] MMCSD0_DAT[0] 179 * MMCSD0_CMD MMCSD0_CLK 180 */ 181 0x28 0x00222222 0x00ffffff 182 >; 183 }; 184 ehrpwm0a_pins: pinmux_ehrpwm0a_pins { 185 pinctrl-single,bits = < 186 /* EPWM0A */ 187 0xc 0x00000002 0x0000000f 188 >; 189 }; 190 ehrpwm0b_pins: pinmux_ehrpwm0b_pins { 191 pinctrl-single,bits = < 192 /* EPWM0B */ 193 0xc 0x00000020 0x000000f0 194 >; 195 }; 196 ehrpwm1a_pins: pinmux_ehrpwm1a_pins { 197 pinctrl-single,bits = < 198 /* EPWM1A */ 199 0x14 0x00000002 0x0000000f 200 >; 201 }; 202 ehrpwm1b_pins: pinmux_ehrpwm1b_pins { 203 pinctrl-single,bits = < 204 /* EPWM1B */ 205 0x14 0x00000020 0x000000f0 206 >; 207 }; 208 ecap0_pins: pinmux_ecap0_pins { 209 pinctrl-single,bits = < 210 /* ECAP0_APWM0 */ 211 0x8 0x20000000 0xf0000000 212 >; 213 }; 214 ecap1_pins: pinmux_ecap1_pins { 215 pinctrl-single,bits = < 216 /* ECAP1_APWM1 */ 217 0x4 0x40000000 0xf0000000 218 >; 219 }; 220 ecap2_pins: pinmux_ecap2_pins { 221 pinctrl-single,bits = < 222 /* ECAP2_APWM2 */ 223 0x4 0x00000004 0x0000000f 224 >; 225 }; 226 spi0_pins: pinmux_spi0_pins { 227 pinctrl-single,bits = < 228 /* SIMO, SOMI, CLK */ 229 0xc 0x00001101 0x0000ff0f 230 >; 231 }; 232 spi0_cs0_pin: pinmux_spi0_cs0 { 233 pinctrl-single,bits = < 234 /* CS0 */ 235 0x10 0x00000010 0x000000f0 236 >; 237 }; 238 spi0_cs3_pin: pinmux_spi0_cs3_pin { 239 pinctrl-single,bits = < 240 /* CS3 */ 241 0xc 0x01000000 0x0f000000 242 >; 243 }; 244 spi1_pins: pinmux_spi1_pins { 245 pinctrl-single,bits = < 246 /* SIMO, SOMI, CLK */ 247 0x14 0x00110100 0x00ff0f00 248 >; 249 }; 250 spi1_cs0_pin: pinmux_spi1_cs0 { 251 pinctrl-single,bits = < 252 /* CS0 */ 253 0x14 0x00000010 0x000000f0 254 >; 255 }; 256 mdio_pins: pinmux_mdio_pins { 257 pinctrl-single,bits = < 258 /* MDIO_CLK, MDIO_D */ 259 0x10 0x00000088 0x000000ff 260 >; 261 }; 262 mii_pins: pinmux_mii_pins { 263 pinctrl-single,bits = < 264 /* 265 * MII_TXEN, MII_TXCLK, MII_COL 266 * MII_TXD_3, MII_TXD_2, MII_TXD_1 267 * MII_TXD_0 268 */ 269 0x8 0x88888880 0xfffffff0 270 /* 271 * MII_RXER, MII_CRS, MII_RXCLK 272 * MII_RXDV, MII_RXD_3, MII_RXD_2 273 * MII_RXD_1, MII_RXD_0 274 */ 275 0xc 0x88888888 0xffffffff 276 >; 277 }; 278 lcd_pins: pinmux_lcd_pins { 279 pinctrl-single,bits = < 280 /* 281 * LCD_D[2], LCD_D[3], LCD_D[4], LCD_D[5], 282 * LCD_D[6], LCD_D[7] 283 */ 284 0x40 0x22222200 0xffffff00 285 /* 286 * LCD_D[10], LCD_D[11], LCD_D[12], LCD_D[13], 287 * LCD_D[14], LCD_D[15], LCD_D[0], LCD_D[1] 288 */ 289 0x44 0x22222222 0xffffffff 290 /* LCD_D[8], LCD_D[9] */ 291 0x48 0x00000022 0x000000ff 292 293 /* LCD_PCLK */ 294 0x48 0x02000000 0x0f000000 295 /* LCD_AC_ENB_CS, LCD_VSYNC, LCD_HSYNC */ 296 0x4c 0x02000022 0x0f0000ff 297 >; 298 }; 299 vpif_capture_pins: vpif_capture_pins { 300 pinctrl-single,bits = < 301 /* VP_DIN[2..7], VP_CLKIN1, VP_CLKIN0 */ 302 0x38 0x11111111 0xffffffff 303 /* VP_DIN[10..15,0..1] */ 304 0x3c 0x11111111 0xffffffff 305 /* VP_DIN[8..9] */ 306 0x40 0x00000011 0x000000ff 307 >; 308 }; 309 vpif_display_pins: vpif_display_pins { 310 pinctrl-single,bits = < 311 /* VP_DOUT[2..7] */ 312 0x40 0x11111100 0xffffff00 313 /* VP_DOUT[10..15,0..1] */ 314 0x44 0x11111111 0xffffffff 315 /* VP_DOUT[8..9] */ 316 0x48 0x00000011 0x000000ff 317 /* 318 * VP_CLKOUT3, VP_CLKIN3, 319 * VP_CLKOUT2, VP_CLKIN2 320 */ 321 0x4c 0x00111100 0x00ffff00 322 >; 323 }; 324 }; 325 prictrl: priority-controller@14110 { 326 compatible = "ti,da850-mstpri"; 327 reg = <0x14110 0x0c>; 328 status = "disabled"; 329 }; 330 cfgchip: chip-controller@1417c { 331 compatible = "ti,da830-cfgchip", "syscon", "simple-mfd"; 332 reg = <0x1417c 0x14>; 333 334 usb_phy: usb-phy { 335 compatible = "ti,da830-usb-phy"; 336 #phy-cells = <1>; 337 clocks = <&usb_phy_clk 0>, <&usb_phy_clk 1>; 338 clock-names = "usb0_clk48", "usb1_clk48"; 339 status = "disabled"; 340 }; 341 usb_phy_clk: usb-phy-clocks { 342 compatible = "ti,da830-usb-phy-clocks"; 343 #clock-cells = <1>; 344 clocks = <&psc1 1>, <&usb_refclkin>, 345 <&pll0_auxclk>; 346 clock-names = "fck", "usb_refclkin", "auxclk"; 347 }; 348 ehrpwm_tbclk: ehrpwm_tbclk { 349 compatible = "ti,da830-tbclksync"; 350 #clock-cells = <0>; 351 clocks = <&psc1 17>; 352 clock-names = "fck"; 353 }; 354 div4p5_clk: div4.5 { 355 compatible = "ti,da830-div4p5ena"; 356 #clock-cells = <0>; 357 clocks = <&pll0_pllout>; 358 clock-names = "pll0_pllout"; 359 }; 360 async1_clk: async1 { 361 compatible = "ti,da850-async1-clksrc"; 362 #clock-cells = <0>; 363 clocks = <&pll0_sysclk 3>, <&div4p5_clk>; 364 clock-names = "pll0_sysclk3", "div4.5"; 365 }; 366 async3_clk: async3 { 367 compatible = "ti,da850-async3-clksrc"; 368 #clock-cells = <0>; 369 clocks = <&pll0_sysclk 2>, <&pll1_sysclk 2>; 370 clock-names = "pll0_sysclk2", "pll1_sysclk2"; 371 }; 372 }; 373 edma0: edma@0 { 374 compatible = "ti,edma3-tpcc"; 375 /* eDMA3 CC0: 0x01c0 0000 - 0x01c0 7fff */ 376 reg = <0x0 0x8000>; 377 reg-names = "edma3_cc"; 378 interrupts = <11 12>; 379 interrupt-names = "edma3_ccint", "edma3_ccerrint"; 380 #dma-cells = <2>; 381 382 ti,tptcs = <&edma0_tptc0 7>, <&edma0_tptc1 0>; 383 power-domains = <&psc0 0>; 384 }; 385 edma0_tptc0: tptc@8000 { 386 compatible = "ti,edma3-tptc"; 387 reg = <0x8000 0x400>; 388 interrupts = <13>; 389 interrupt-names = "edm3_tcerrint"; 390 power-domains = <&psc0 1>; 391 }; 392 edma0_tptc1: tptc@8400 { 393 compatible = "ti,edma3-tptc"; 394 reg = <0x8400 0x400>; 395 interrupts = <32>; 396 interrupt-names = "edm3_tcerrint"; 397 power-domains = <&psc0 2>; 398 }; 399 edma1: edma@230000 { 400 compatible = "ti,edma3-tpcc"; 401 /* eDMA3 CC1: 0x01e3 0000 - 0x01e3 7fff */ 402 reg = <0x230000 0x8000>; 403 reg-names = "edma3_cc"; 404 interrupts = <93 94>; 405 interrupt-names = "edma3_ccint", "edma3_ccerrint"; 406 #dma-cells = <2>; 407 408 ti,tptcs = <&edma1_tptc0 7>; 409 power-domains = <&psc1 0>; 410 }; 411 edma1_tptc0: tptc@238000 { 412 compatible = "ti,edma3-tptc"; 413 reg = <0x238000 0x400>; 414 interrupts = <95>; 415 interrupt-names = "edm3_tcerrint"; 416 power-domains = <&psc1 21>; 417 }; 418 serial0: serial@42000 { 419 compatible = "ti,da830-uart", "ns16550a"; 420 reg = <0x42000 0x100>; 421 reg-io-width = <4>; 422 reg-shift = <2>; 423 interrupts = <25>; 424 clocks = <&psc0 9>; 425 power-domains = <&psc0 9>; 426 status = "disabled"; 427 }; 428 serial1: serial@10c000 { 429 compatible = "ti,da830-uart", "ns16550a"; 430 reg = <0x10c000 0x100>; 431 reg-io-width = <4>; 432 reg-shift = <2>; 433 interrupts = <53>; 434 clocks = <&psc1 12>; 435 power-domains = <&psc1 12>; 436 status = "disabled"; 437 }; 438 serial2: serial@10d000 { 439 compatible = "ti,da830-uart", "ns16550a"; 440 reg = <0x10d000 0x100>; 441 reg-io-width = <4>; 442 reg-shift = <2>; 443 interrupts = <61>; 444 clocks = <&psc1 13>; 445 power-domains = <&psc1 13>; 446 status = "disabled"; 447 }; 448 rtc0: rtc@23000 { 449 compatible = "ti,da830-rtc"; 450 reg = <0x23000 0x1000>; 451 interrupts = <19 452 19>; 453 clocks = <&pll0_auxclk>; 454 clock-names = "int-clk"; 455 status = "disabled"; 456 }; 457 i2c0: i2c@22000 { 458 compatible = "ti,davinci-i2c"; 459 reg = <0x22000 0x1000>; 460 interrupts = <15>; 461 #address-cells = <1>; 462 #size-cells = <0>; 463 clocks = <&pll0_auxclk>; 464 status = "disabled"; 465 }; 466 i2c1: i2c@228000 { 467 compatible = "ti,davinci-i2c"; 468 reg = <0x228000 0x1000>; 469 interrupts = <51>; 470 #address-cells = <1>; 471 #size-cells = <0>; 472 clocks = <&psc1 11>; 473 power-domains = <&psc1 11>; 474 status = "disabled"; 475 }; 476 clocksource: timer@20000 { 477 compatible = "ti,da830-timer"; 478 reg = <0x20000 0x1000>; 479 interrupts = <12>, <13>; 480 interrupt-names = "tint12", "tint34"; 481 clocks = <&pll0_auxclk>; 482 }; 483 wdt: wdt@21000 { 484 compatible = "ti,davinci-wdt"; 485 reg = <0x21000 0x1000>; 486 clocks = <&pll0_auxclk>; 487 status = "disabled"; 488 }; 489 mmc0: mmc@40000 { 490 compatible = "ti,da830-mmc"; 491 reg = <0x40000 0x1000>; 492 cap-sd-highspeed; 493 cap-mmc-highspeed; 494 interrupts = <16>; 495 dmas = <&edma0 16 0>, <&edma0 17 0>; 496 dma-names = "rx", "tx"; 497 clocks = <&psc0 5>; 498 status = "disabled"; 499 }; 500 vpif: video@217000 { 501 compatible = "ti,da850-vpif"; 502 reg = <0x217000 0x1000>; 503 interrupts = <92>; 504 power-domains = <&psc1 9>; 505 status = "disabled"; 506 507 /* VPIF capture port */ 508 port@0 { 509 #address-cells = <1>; 510 #size-cells = <0>; 511 }; 512 513 /* VPIF display port */ 514 port@1 { 515 #address-cells = <1>; 516 #size-cells = <0>; 517 }; 518 }; 519 mmc1: mmc@21b000 { 520 compatible = "ti,da830-mmc"; 521 reg = <0x21b000 0x1000>; 522 cap-sd-highspeed; 523 cap-mmc-highspeed; 524 interrupts = <72>; 525 dmas = <&edma1 28 0>, <&edma1 29 0>; 526 dma-names = "rx", "tx"; 527 clocks = <&psc1 18>; 528 status = "disabled"; 529 }; 530 ehrpwm0: pwm@300000 { 531 compatible = "ti,da850-ehrpwm", "ti,am3352-ehrpwm", 532 "ti,am33xx-ehrpwm"; 533 #pwm-cells = <3>; 534 reg = <0x300000 0x2000>; 535 clocks = <&psc1 17>, <&ehrpwm_tbclk>; 536 clock-names = "fck", "tbclk"; 537 power-domains = <&psc1 17>; 538 status = "disabled"; 539 }; 540 ehrpwm1: pwm@302000 { 541 compatible = "ti,da850-ehrpwm", "ti,am3352-ehrpwm", 542 "ti,am33xx-ehrpwm"; 543 #pwm-cells = <3>; 544 reg = <0x302000 0x2000>; 545 clocks = <&psc1 17>, <&ehrpwm_tbclk>; 546 clock-names = "fck", "tbclk"; 547 power-domains = <&psc1 17>; 548 status = "disabled"; 549 }; 550 ecap0: ecap@306000 { 551 compatible = "ti,da850-ecap", "ti,am3352-ecap", 552 "ti,am33xx-ecap"; 553 #pwm-cells = <3>; 554 reg = <0x306000 0x80>; 555 clocks = <&psc1 20>; 556 clock-names = "fck"; 557 power-domains = <&psc1 20>; 558 status = "disabled"; 559 }; 560 ecap1: ecap@307000 { 561 compatible = "ti,da850-ecap", "ti,am3352-ecap", 562 "ti,am33xx-ecap"; 563 #pwm-cells = <3>; 564 reg = <0x307000 0x80>; 565 clocks = <&psc1 20>; 566 clock-names = "fck"; 567 power-domains = <&psc1 20>; 568 status = "disabled"; 569 }; 570 ecap2: ecap@308000 { 571 compatible = "ti,da850-ecap", "ti,am3352-ecap", 572 "ti,am33xx-ecap"; 573 #pwm-cells = <3>; 574 reg = <0x308000 0x80>; 575 clocks = <&psc1 20>; 576 clock-names = "fck"; 577 power-domains = <&psc1 20>; 578 status = "disabled"; 579 }; 580 spi0: spi@41000 { 581 #address-cells = <1>; 582 #size-cells = <0>; 583 compatible = "ti,da830-spi"; 584 reg = <0x41000 0x1000>; 585 num-cs = <6>; 586 ti,davinci-spi-intr-line = <1>; 587 interrupts = <20>; 588 dmas = <&edma0 14 0>, <&edma0 15 0>; 589 dma-names = "rx", "tx"; 590 clocks = <&psc0 4>; 591 power-domains = <&psc0 4>; 592 status = "disabled"; 593 }; 594 spi1: spi@30e000 { 595 #address-cells = <1>; 596 #size-cells = <0>; 597 compatible = "ti,da830-spi"; 598 reg = <0x30e000 0x1000>; 599 num-cs = <4>; 600 ti,davinci-spi-intr-line = <1>; 601 interrupts = <56>; 602 dmas = <&edma0 18 0>, <&edma0 19 0>; 603 dma-names = "rx", "tx"; 604 clocks = <&psc1 10>; 605 power-domains = <&psc1 10>; 606 status = "disabled"; 607 }; 608 usb0: usb@200000 { 609 compatible = "ti,da830-musb"; 610 reg = <0x200000 0x1000>; 611 ranges; 612 interrupts = <58>; 613 interrupt-names = "mc"; 614 dr_mode = "otg"; 615 phys = <&usb_phy 0>; 616 phy-names = "usb-phy"; 617 clocks = <&psc1 1>; 618 clock-ranges; 619 status = "disabled"; 620 621 #address-cells = <1>; 622 #size-cells = <1>; 623 624 dmas = <&cppi41dma 0 0 &cppi41dma 1 0 625 &cppi41dma 2 0 &cppi41dma 3 0 626 &cppi41dma 0 1 &cppi41dma 1 1 627 &cppi41dma 2 1 &cppi41dma 3 1>; 628 dma-names = 629 "rx1", "rx2", "rx3", "rx4", 630 "tx1", "tx2", "tx3", "tx4"; 631 632 cppi41dma: dma-controller@201000 { 633 compatible = "ti,da830-cppi41"; 634 reg = <0x201000 0x1000 635 0x202000 0x1000 636 0x204000 0x4000>; 637 reg-names = "controller", 638 "scheduler", "queuemgr"; 639 interrupts = <58>; 640 #dma-cells = <2>; 641 #dma-channels = <4>; 642 power-domains = <&psc1 1>; 643 status = "okay"; 644 }; 645 }; 646 sata: sata@218000 { 647 compatible = "ti,da850-ahci"; 648 reg = <0x218000 0x2000>, <0x22c018 0x4>; 649 interrupts = <67>; 650 clocks = <&psc1 8>, <&sata_refclk>; 651 clock-names = "fck", "refclk"; 652 status = "disabled"; 653 }; 654 pll1: clock-controller@21a000 { 655 compatible = "ti,da850-pll1"; 656 reg = <0x21a000 0x1000>; 657 clocks = <&ref_clk>; 658 clock-names = "clksrc"; 659 660 pll1_sysclk: sysclk { 661 #clock-cells = <1>; 662 }; 663 pll1_obsclk: obsclk { 664 #clock-cells = <0>; 665 }; 666 }; 667 mdio: mdio@224000 { 668 compatible = "ti,davinci_mdio"; 669 #address-cells = <1>; 670 #size-cells = <0>; 671 reg = <0x224000 0x1000>; 672 clocks = <&psc1 5>; 673 clock-names = "fck"; 674 power-domains = <&psc1 5>; 675 status = "disabled"; 676 }; 677 eth0: ethernet@220000 { 678 compatible = "ti,davinci-dm6467-emac"; 679 reg = <0x220000 0x4000>; 680 ti,davinci-ctrl-reg-offset = <0x3000>; 681 ti,davinci-ctrl-mod-reg-offset = <0x2000>; 682 ti,davinci-ctrl-ram-offset = <0>; 683 ti,davinci-ctrl-ram-size = <0x2000>; 684 local-mac-address = [ 00 00 00 00 00 00 ]; 685 interrupts = <33 686 34 687 35 688 36 689 >; 690 clocks = <&psc1 5>; 691 power-domains = <&psc1 5>; 692 status = "disabled"; 693 }; 694 usb1: usb@225000 { 695 compatible = "ti,da830-ohci"; 696 reg = <0x225000 0x1000>; 697 interrupts = <59>; 698 phys = <&usb_phy 1>; 699 phy-names = "usb-phy"; 700 clocks = <&psc1 2>; 701 status = "disabled"; 702 }; 703 gpio: gpio@226000 { 704 compatible = "ti,dm6441-gpio"; 705 gpio-controller; 706 #gpio-cells = <2>; 707 reg = <0x226000 0x1000>; 708 interrupts = <42 43 44 45 46 47 48 49 50>; 709 ti,ngpio = <144>; 710 ti,davinci-gpio-unbanked = <0>; 711 clocks = <&psc1 3>; 712 clock-names = "gpio"; 713 status = "disabled"; 714 interrupt-controller; 715 #interrupt-cells = <2>; 716 gpio-ranges = <&pmx_core 0 15 1>, 717 <&pmx_core 1 14 1>, 718 <&pmx_core 2 13 1>, 719 <&pmx_core 3 12 1>, 720 <&pmx_core 4 11 1>, 721 <&pmx_core 5 10 1>, 722 <&pmx_core 6 9 1>, 723 <&pmx_core 7 8 1>, 724 <&pmx_core 8 7 1>, 725 <&pmx_core 9 6 1>, 726 <&pmx_core 10 5 1>, 727 <&pmx_core 11 4 1>, 728 <&pmx_core 12 3 1>, 729 <&pmx_core 13 2 1>, 730 <&pmx_core 14 1 1>, 731 <&pmx_core 15 0 1>, 732 <&pmx_core 16 39 1>, 733 <&pmx_core 17 38 1>, 734 <&pmx_core 18 37 1>, 735 <&pmx_core 19 36 1>, 736 <&pmx_core 20 35 1>, 737 <&pmx_core 21 34 1>, 738 <&pmx_core 22 33 1>, 739 <&pmx_core 23 32 1>, 740 <&pmx_core 24 24 1>, 741 <&pmx_core 25 22 1>, 742 <&pmx_core 26 21 1>, 743 <&pmx_core 27 20 1>, 744 <&pmx_core 28 19 1>, 745 <&pmx_core 29 18 1>, 746 <&pmx_core 30 17 1>, 747 <&pmx_core 31 16 1>, 748 <&pmx_core 32 55 1>, 749 <&pmx_core 33 54 1>, 750 <&pmx_core 34 53 1>, 751 <&pmx_core 35 52 1>, 752 <&pmx_core 36 51 1>, 753 <&pmx_core 37 50 1>, 754 <&pmx_core 38 49 1>, 755 <&pmx_core 39 48 1>, 756 <&pmx_core 40 47 1>, 757 <&pmx_core 41 46 1>, 758 <&pmx_core 42 45 1>, 759 <&pmx_core 43 44 1>, 760 <&pmx_core 44 43 1>, 761 <&pmx_core 45 42 1>, 762 <&pmx_core 46 41 1>, 763 <&pmx_core 47 40 1>, 764 <&pmx_core 48 71 1>, 765 <&pmx_core 49 70 1>, 766 <&pmx_core 50 69 1>, 767 <&pmx_core 51 68 1>, 768 <&pmx_core 52 67 1>, 769 <&pmx_core 53 66 1>, 770 <&pmx_core 54 65 1>, 771 <&pmx_core 55 64 1>, 772 <&pmx_core 56 63 1>, 773 <&pmx_core 57 62 1>, 774 <&pmx_core 58 61 1>, 775 <&pmx_core 59 60 1>, 776 <&pmx_core 60 59 1>, 777 <&pmx_core 61 58 1>, 778 <&pmx_core 62 57 1>, 779 <&pmx_core 63 56 1>, 780 <&pmx_core 64 87 1>, 781 <&pmx_core 65 86 1>, 782 <&pmx_core 66 85 1>, 783 <&pmx_core 67 84 1>, 784 <&pmx_core 68 83 1>, 785 <&pmx_core 69 82 1>, 786 <&pmx_core 70 81 1>, 787 <&pmx_core 71 80 1>, 788 <&pmx_core 72 70 1>, 789 <&pmx_core 73 78 1>, 790 <&pmx_core 74 77 1>, 791 <&pmx_core 75 76 1>, 792 <&pmx_core 76 75 1>, 793 <&pmx_core 77 74 1>, 794 <&pmx_core 78 73 1>, 795 <&pmx_core 79 72 1>, 796 <&pmx_core 80 103 1>, 797 <&pmx_core 81 102 1>, 798 <&pmx_core 82 101 1>, 799 <&pmx_core 83 100 1>, 800 <&pmx_core 84 99 1>, 801 <&pmx_core 85 98 1>, 802 <&pmx_core 86 97 1>, 803 <&pmx_core 87 96 1>, 804 <&pmx_core 88 95 1>, 805 <&pmx_core 89 94 1>, 806 <&pmx_core 90 93 1>, 807 <&pmx_core 91 92 1>, 808 <&pmx_core 92 91 1>, 809 <&pmx_core 93 90 1>, 810 <&pmx_core 94 89 1>, 811 <&pmx_core 95 88 1>, 812 <&pmx_core 96 158 1>, 813 <&pmx_core 97 157 1>, 814 <&pmx_core 98 156 1>, 815 <&pmx_core 99 155 1>, 816 <&pmx_core 100 154 1>, 817 <&pmx_core 101 129 1>, 818 <&pmx_core 102 113 1>, 819 <&pmx_core 103 112 1>, 820 <&pmx_core 104 111 1>, 821 <&pmx_core 105 110 1>, 822 <&pmx_core 106 109 1>, 823 <&pmx_core 107 108 1>, 824 <&pmx_core 108 107 1>, 825 <&pmx_core 109 106 1>, 826 <&pmx_core 110 105 1>, 827 <&pmx_core 111 104 1>, 828 <&pmx_core 112 145 1>, 829 <&pmx_core 113 144 1>, 830 <&pmx_core 114 143 1>, 831 <&pmx_core 115 142 1>, 832 <&pmx_core 116 141 1>, 833 <&pmx_core 117 140 1>, 834 <&pmx_core 118 139 1>, 835 <&pmx_core 119 138 1>, 836 <&pmx_core 120 137 1>, 837 <&pmx_core 121 136 1>, 838 <&pmx_core 122 135 1>, 839 <&pmx_core 123 134 1>, 840 <&pmx_core 124 133 1>, 841 <&pmx_core 125 132 1>, 842 <&pmx_core 126 131 1>, 843 <&pmx_core 127 130 1>, 844 <&pmx_core 128 159 1>, 845 <&pmx_core 129 31 1>, 846 <&pmx_core 130 30 1>, 847 <&pmx_core 131 20 1>, 848 <&pmx_core 132 28 1>, 849 <&pmx_core 133 27 1>, 850 <&pmx_core 134 26 1>, 851 <&pmx_core 135 23 1>, 852 <&pmx_core 136 153 1>, 853 <&pmx_core 137 152 1>, 854 <&pmx_core 138 151 1>, 855 <&pmx_core 139 150 1>, 856 <&pmx_core 140 149 1>, 857 <&pmx_core 141 148 1>, 858 <&pmx_core 142 147 1>, 859 <&pmx_core 143 146 1>; 860 }; 861 psc1: clock-controller@227000 { 862 compatible = "ti,da850-psc1"; 863 reg = <0x227000 0x1000>; 864 #clock-cells = <1>; 865 #power-domain-cells = <1>; 866 clocks = <&pll0_sysclk 2>, <&pll0_sysclk 4>, 867 <&async3_clk>; 868 clock-names = "pll0_sysclk2", "pll0_sysclk4", "async3"; 869 assigned-clocks = <&async3_clk>; 870 assigned-clock-parents = <&pll1_sysclk 2>; 871 }; 872 pinconf: pin-controller@22c00c { 873 compatible = "ti,da850-pupd"; 874 reg = <0x22c00c 0x8>; 875 status = "disabled"; 876 }; 877 878 mcasp0: mcasp@100000 { 879 compatible = "ti,da830-mcasp-audio"; 880 reg = <0x100000 0x2000>, 881 <0x102000 0x400000>; 882 reg-names = "mpu", "dat"; 883 interrupts = <54>; 884 interrupt-names = "common"; 885 power-domains = <&psc1 7>; 886 status = "disabled"; 887 dmas = <&edma0 1 1>, 888 <&edma0 0 1>; 889 dma-names = "tx", "rx"; 890 }; 891 892 lcdc: display@213000 { 893 compatible = "ti,da850-tilcdc"; 894 reg = <0x213000 0x1000>; 895 interrupts = <52>; 896 max-pixelclock = <37500>; 897 clocks = <&psc1 16>; 898 clock-names = "fck"; 899 power-domains = <&psc1 16>; 900 status = "disabled"; 901 }; 902 }; 903 aemif: aemif@68000000 { 904 compatible = "ti,da850-aemif"; 905 #address-cells = <2>; 906 #size-cells = <1>; 907 908 reg = <0x68000000 0x00008000>; 909 ranges = <0 0 0x60000000 0x08000000 910 1 0 0x68000000 0x00008000>; 911 clocks = <&psc0 3>; 912 clock-names = "aemif"; 913 clock-ranges; 914 status = "disabled"; 915 }; 916 memctrl: memory-controller@b0000000 { 917 compatible = "ti,da850-ddr-controller"; 918 reg = <0xb0000000 0xe8>; 919 status = "disabled"; 920 }; 921}; 922
