1/*
2 * Broadcom BCM470X / BCM5301X ARM platform code.
3 * Generic DTS part for all BCM53010, BCM53011, BCM53012, BCM53014, BCM53015,
4 * BCM53016, BCM53017, BCM53018, BCM4707, BCM4708 and BCM4709 SoCs
5 *
6 * Copyright 2013-2014 Hauke Mehrtens <hauke@hauke-m.de>
7 *
8 * Licensed under the GNU/GPL. See COPYING for details.
9 */
10
11#include <dt-bindings/clock/bcm-nsp.h>
12#include <dt-bindings/gpio/gpio.h>
13#include <dt-bindings/input/input.h>
14#include <dt-bindings/interrupt-controller/irq.h>
15#include <dt-bindings/interrupt-controller/arm-gic.h>
16#include "skeleton.dtsi"
17
18/ {
19	interrupt-parent = <&gic>;
20
21	chipcommonA {
22		compatible = "simple-bus";
23		ranges = <0x00000000 0x18000000 0x00001000>;
24		#address-cells = <1>;
25		#size-cells = <1>;
26
27		uart0: serial@300 {
28			compatible = "ns16550";
29			reg = <0x0300 0x100>;
30			interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
31			clocks = <&iprocslow>;
32			status = "disabled";
33		};
34
35		uart1: serial@400 {
36			compatible = "ns16550";
37			reg = <0x0400 0x100>;
38			interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
39			clocks = <&iprocslow>;
40			status = "disabled";
41		};
42	};
43
44	mpcore {
45		compatible = "simple-bus";
46		ranges = <0x00000000 0x19000000 0x00023000>;
47		#address-cells = <1>;
48		#size-cells = <1>;
49
50		a9pll: arm_clk@0 {
51			#clock-cells = <0>;
52			compatible = "brcm,nsp-armpll";
53			clocks = <&osc>;
54			reg = <0x00000 0x1000>;
55		};
56
57		scu@20000 {
58			compatible = "arm,cortex-a9-scu";
59			reg = <0x20000 0x100>;
60		};
61
62		timer@20200 {
63			compatible = "arm,cortex-a9-global-timer";
64			reg = <0x20200 0x100>;
65			interrupts = <GIC_PPI 11 IRQ_TYPE_EDGE_RISING>;
66			clocks = <&periph_clk>;
67		};
68
69		timer@20600 {
70			compatible = "arm,cortex-a9-twd-timer";
71			reg = <0x20600 0x20>;
72			interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) |
73						  IRQ_TYPE_EDGE_RISING)>;
74			clocks = <&periph_clk>;
75		};
76
77		watchdog@20620 {
78			compatible = "arm,cortex-a9-twd-wdt";
79			reg = <0x20620 0x20>;
80			interrupts = <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) |
81						  IRQ_TYPE_EDGE_RISING)>;
82			clocks = <&periph_clk>;
83		};
84
85		gic: interrupt-controller@21000 {
86			compatible = "arm,cortex-a9-gic";
87			#interrupt-cells = <3>;
88			#address-cells = <0>;
89			interrupt-controller;
90			reg = <0x21000 0x1000>,
91			      <0x20100 0x100>;
92		};
93
94		L2: cache-controller@22000 {
95			compatible = "arm,pl310-cache";
96			reg = <0x22000 0x1000>;
97			cache-unified;
98			arm,shared-override;
99			prefetch-data = <1>;
100			prefetch-instr = <1>;
101			cache-level = <2>;
102		};
103	};
104
105	pmu {
106		compatible = "arm,cortex-a9-pmu";
107		interrupts =
108			<GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
109			<GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
110	};
111
112	clocks {
113		#address-cells = <1>;
114		#size-cells = <1>;
115		ranges;
116
117		osc: oscillator {
118			#clock-cells = <0>;
119			compatible = "fixed-clock";
120			clock-frequency = <25000000>;
121		};
122
123		iprocmed: iprocmed {
124			#clock-cells = <0>;
125			compatible = "fixed-factor-clock";
126			clocks = <&genpll BCM_NSP_GENPLL_IPROCFAST_CLK>;
127			clock-div = <2>;
128			clock-mult = <1>;
129		};
130
131		iprocslow: iprocslow {
132			#clock-cells = <0>;
133			compatible = "fixed-factor-clock";
134			clocks = <&genpll BCM_NSP_GENPLL_IPROCFAST_CLK>;
135			clock-div = <4>;
136			clock-mult = <1>;
137		};
138
139		periph_clk: periph_clk {
140			#clock-cells = <0>;
141			compatible = "fixed-factor-clock";
142			clocks = <&a9pll>;
143			clock-div = <2>;
144			clock-mult = <1>;
145		};
146	};
147
148	usb2_phy: usb2-phy {
149		compatible = "brcm,ns-usb2-phy";
150		reg = <0x1800c000 0x1000>;
151		reg-names = "dmu";
152		#phy-cells = <0>;
153		clocks = <&genpll BCM_NSP_GENPLL_USB_PHY_REF_CLK>;
154		clock-names = "phy-ref-clk";
155	};
156
157	axi@18000000 {
158		compatible = "brcm,bus-axi";
159		reg = <0x18000000 0x1000>;
160		ranges = <0x00000000 0x18000000 0x00100000>;
161		#address-cells = <1>;
162		#size-cells = <1>;
163
164		#interrupt-cells = <1>;
165		interrupt-map-mask = <0x000fffff 0xffff>;
166		interrupt-map =
167			/* ChipCommon */
168			<0x00000000 0 &gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
169
170			/* Switch Register Access Block */
171			<0x00007000 0 &gic GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
172			<0x00007000 1 &gic GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
173			<0x00007000 2 &gic GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
174			<0x00007000 3 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
175			<0x00007000 4 &gic GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
176			<0x00007000 5 &gic GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
177			<0x00007000 6 &gic GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
178			<0x00007000 7 &gic GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
179			<0x00007000 8 &gic GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
180			<0x00007000 9 &gic GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
181			<0x00007000 10 &gic GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
182			<0x00007000 11 &gic GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
183			<0x00007000 12 &gic GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
184
185			/* PCIe Controller 0 */
186			<0x00012000 0 &gic GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
187			<0x00012000 1 &gic GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>,
188			<0x00012000 2 &gic GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
189			<0x00012000 3 &gic GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
190			<0x00012000 4 &gic GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
191			<0x00012000 5 &gic GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
192
193			/* PCIe Controller 1 */
194			<0x00013000 0 &gic GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
195			<0x00013000 1 &gic GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
196			<0x00013000 2 &gic GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
197			<0x00013000 3 &gic GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
198			<0x00013000 4 &gic GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
199			<0x00013000 5 &gic GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
200
201			/* PCIe Controller 2 */
202			<0x00014000 0 &gic GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
203			<0x00014000 1 &gic GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
204			<0x00014000 2 &gic GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
205			<0x00014000 3 &gic GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
206			<0x00014000 4 &gic GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
207			<0x00014000 5 &gic GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
208
209			/* USB 2.0 Controller */
210			<0x00021000 0 &gic GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>,
211
212			/* USB 3.0 Controller */
213			<0x00023000 0 &gic GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>,
214
215			/* Ethernet Controller 0 */
216			<0x00024000 0 &gic GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
217
218			/* Ethernet Controller 1 */
219			<0x00025000 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
220
221			/* Ethernet Controller 2 */
222			<0x00026000 0 &gic GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
223
224			/* Ethernet Controller 3 */
225			<0x00027000 0 &gic GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
226
227			/* NAND Controller */
228			<0x00028000 0 &gic GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
229			<0x00028000 1 &gic GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
230			<0x00028000 2 &gic GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
231			<0x00028000 3 &gic GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
232			<0x00028000 4 &gic GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
233			<0x00028000 5 &gic GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
234			<0x00028000 6 &gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
235			<0x00028000 7 &gic GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
236
237		chipcommon: chipcommon@0 {
238			reg = <0x00000000 0x1000>;
239
240			gpio-controller;
241			#gpio-cells = <2>;
242		};
243
244		pcie0: pcie@12000 {
245			reg = <0x00012000 0x1000>;
246		};
247
248		pcie1: pcie@13000 {
249			reg = <0x00013000 0x1000>;
250		};
251
252		usb2: usb2@21000 {
253			reg = <0x00021000 0x1000>;
254
255			#address-cells = <1>;
256			#size-cells = <1>;
257			ranges;
258
259			interrupt-parent = <&gic>;
260
261			ehci: ehci@21000 {
262				#usb-cells = <0>;
263
264				compatible = "generic-ehci";
265				reg = <0x00021000 0x1000>;
266				interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
267				phys = <&usb2_phy>;
268
269				#address-cells = <1>;
270				#size-cells = <0>;
271
272				ehci_port1: port@1 {
273					reg = <1>;
274					#trigger-source-cells = <0>;
275				};
276
277				ehci_port2: port@2 {
278					reg = <2>;
279					#trigger-source-cells = <0>;
280				};
281			};
282
283			ohci: ohci@22000 {
284				#usb-cells = <0>;
285
286				compatible = "generic-ohci";
287				reg = <0x00022000 0x1000>;
288				interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
289
290				#address-cells = <1>;
291				#size-cells = <0>;
292
293				ohci_port1: port@1 {
294					reg = <1>;
295					#trigger-source-cells = <0>;
296				};
297
298				ohci_port2: port@2 {
299					reg = <2>;
300					#trigger-source-cells = <0>;
301				};
302			};
303		};
304
305		usb3: usb3@23000 {
306			reg = <0x00023000 0x1000>;
307
308			#address-cells = <1>;
309			#size-cells = <1>;
310			ranges;
311
312			interrupt-parent = <&gic>;
313
314			xhci: xhci@23000 {
315				#usb-cells = <0>;
316
317				compatible = "generic-xhci";
318				reg = <0x00023000 0x1000>;
319				interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
320				phys = <&usb3_phy>;
321				phy-names = "usb";
322
323				#address-cells = <1>;
324				#size-cells = <0>;
325
326				xhci_port1: port@1 {
327					reg = <1>;
328					#trigger-source-cells = <0>;
329				};
330			};
331		};
332
333		gmac0: ethernet@24000 {
334			reg = <0x24000 0x800>;
335		};
336
337		gmac1: ethernet@25000 {
338			reg = <0x25000 0x800>;
339		};
340
341		gmac2: ethernet@26000 {
342			reg = <0x26000 0x800>;
343		};
344
345		gmac3: ethernet@27000 {
346			reg = <0x27000 0x800>;
347		};
348	};
349
350	mdio: mdio@18003000 {
351		compatible = "brcm,iproc-mdio";
352		reg = <0x18003000 0x8>;
353		#size-cells = <1>;
354		#address-cells = <0>;
355	};
356
357	mdio-bus-mux {
358		compatible = "mdio-mux-mmioreg";
359		mdio-parent-bus = <&mdio>;
360		#address-cells = <1>;
361		#size-cells = <0>;
362		reg = <0x18003000 0x4>;
363		mux-mask = <0x200>;
364
365		mdio@0 {
366			reg = <0x0>;
367			#address-cells = <1>;
368			#size-cells = <0>;
369
370			usb3_phy: usb3-phy@10 {
371				compatible = "brcm,ns-ax-usb3-phy";
372				reg = <0x10>;
373				usb3-dmp-syscon = <&usb3_dmp>;
374				#phy-cells = <0>;
375				status = "disabled";
376			};
377		};
378	};
379
380	usb3_dmp: syscon@18105000 {
381		reg = <0x18105000 0x1000>;
382	};
383
384	i2c0: i2c@18009000 {
385		compatible = "brcm,iproc-i2c";
386		reg = <0x18009000 0x50>;
387		interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
388		#address-cells = <1>;
389		#size-cells = <0>;
390		clock-frequency = <100000>;
391		status = "disabled";
392	};
393
394	lcpll0: lcpll0@1800c100 {
395		#clock-cells = <1>;
396		compatible = "brcm,nsp-lcpll0";
397		reg = <0x1800c100 0x14>;
398		clocks = <&osc>;
399		clock-output-names = "lcpll0", "pcie_phy", "sdio",
400				     "ddr_phy";
401	};
402
403	genpll: genpll@1800c140 {
404		#clock-cells = <1>;
405		compatible = "brcm,nsp-genpll";
406		reg = <0x1800c140 0x24>;
407		clocks = <&osc>;
408		clock-output-names = "genpll", "phy", "ethernetclk",
409				     "usbclk", "iprocfast", "sata1",
410				     "sata2";
411	};
412
413	thermal: thermal@1800c2c0 {
414		compatible = "brcm,ns-thermal";
415		reg = <0x1800c2c0 0x10>;
416		#thermal-sensor-cells = <0>;
417	};
418
419	srab: srab@18007000 {
420		compatible = "brcm,bcm5301x-srab";
421		reg = <0x18007000 0x1000>;
422		#address-cells = <1>;
423		#size-cells = <0>;
424
425		status = "disabled";
426
427		/* ports are defined in board DTS */
428	};
429
430	rng: rng@18004000 {
431		compatible = "brcm,bcm5301x-rng";
432		reg = <0x18004000 0x14>;
433	};
434
435	nand: nand@18028000 {
436		compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1", "brcm,brcmnand";
437		reg = <0x18028000 0x600>, <0x1811a408 0x600>, <0x18028f00 0x20>;
438		reg-names = "nand", "iproc-idm", "iproc-ext";
439		interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
440
441		#address-cells = <1>;
442		#size-cells = <0>;
443
444		brcm,nand-has-wp;
445	};
446
447	spi@18029200 {
448		compatible = "brcm,spi-bcm-qspi", "brcm,spi-nsp-qspi";
449		reg = <0x18029200 0x184>,
450		      <0x18029000 0x124>,
451		      <0x1811b408 0x004>,
452		      <0x180293a0 0x01c>;
453		reg-names = "mspi", "bspi", "intr_regs", "intr_status_reg";
454		interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
455			     <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
456			     <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
457			     <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>,
458			     <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
459			     <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
460			     <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
461		interrupt-names = "spi_lr_fullness_reached",
462				  "spi_lr_session_aborted",
463				  "spi_lr_impatient",
464				  "spi_lr_session_done",
465				  "spi_lr_overhead",
466				  "mspi_done",
467				  "mspi_halted";
468		clocks = <&iprocmed>;
469		clock-names = "iprocmed";
470		num-cs = <2>;
471		#address-cells = <1>;
472		#size-cells = <0>;
473
474		spi_nor: spi-nor@0 {
475			compatible = "jedec,spi-nor";
476			reg = <0>;
477			spi-max-frequency = <20000000>;
478			linux,part-probe = "ofpart", "bcm47xxpart";
479			status = "disabled";
480		};
481	};
482
483	thermal-zones {
484		cpu_thermal: cpu-thermal {
485			polling-delay-passive = <0>;
486			polling-delay = <1000>;
487			coefficients = <(-556) 418000>;
488			thermal-sensors = <&thermal>;
489
490			trips {
491				cpu-crit {
492					temperature	= <125000>;
493					hysteresis	= <0>;
494					type		= "critical";
495				};
496			};
497
498			cooling-maps {
499			};
500		};
501	};
502};
503