1 // SPDX-License-Identifier: GPL-2.0-only
2 #include <linux/module.h>
3 #include <linux/types.h>
4 #include <linux/kernel.h>
5 #include <linux/sched.h>
6 #include <asm/ptrace.h>
7
8 #include <linux/uaccess.h>
9
10 #include "sfp-util.h"
11 #include <math-emu/soft-fp.h>
12 #include <math-emu/single.h>
13 #include <math-emu/double.h>
14
15 #define OPC_PAL 0x00
16 #define OPC_INTA 0x10
17 #define OPC_INTL 0x11
18 #define OPC_INTS 0x12
19 #define OPC_INTM 0x13
20 #define OPC_FLTC 0x14
21 #define OPC_FLTV 0x15
22 #define OPC_FLTI 0x16
23 #define OPC_FLTL 0x17
24 #define OPC_MISC 0x18
25 #define OPC_JSR 0x1a
26
27 #define FOP_SRC_S 0
28 #define FOP_SRC_T 2
29 #define FOP_SRC_Q 3
30
31 #define FOP_FNC_ADDx 0
32 #define FOP_FNC_CVTQL 0
33 #define FOP_FNC_SUBx 1
34 #define FOP_FNC_MULx 2
35 #define FOP_FNC_DIVx 3
36 #define FOP_FNC_CMPxUN 4
37 #define FOP_FNC_CMPxEQ 5
38 #define FOP_FNC_CMPxLT 6
39 #define FOP_FNC_CMPxLE 7
40 #define FOP_FNC_SQRTx 11
41 #define FOP_FNC_CVTxS 12
42 #define FOP_FNC_CVTxT 14
43 #define FOP_FNC_CVTxQ 15
44
45 #define MISC_TRAPB 0x0000
46 #define MISC_EXCB 0x0400
47
48 extern unsigned long alpha_read_fp_reg (unsigned long reg);
49 extern void alpha_write_fp_reg (unsigned long reg, unsigned long val);
50 extern unsigned long alpha_read_fp_reg_s (unsigned long reg);
51 extern void alpha_write_fp_reg_s (unsigned long reg, unsigned long val);
52
53
54 #ifdef MODULE
55
56 MODULE_DESCRIPTION("FP Software completion module");
57 MODULE_LICENSE("GPL v2");
58
59 extern long (*alpha_fp_emul_imprecise)(struct pt_regs *, unsigned long);
60 extern long (*alpha_fp_emul) (unsigned long pc);
61
62 static long (*save_emul_imprecise)(struct pt_regs *, unsigned long);
63 static long (*save_emul) (unsigned long pc);
64
65 long do_alpha_fp_emul_imprecise(struct pt_regs *, unsigned long);
66 long do_alpha_fp_emul(unsigned long);
67
init_module(void)68 int init_module(void)
69 {
70 save_emul_imprecise = alpha_fp_emul_imprecise;
71 save_emul = alpha_fp_emul;
72 alpha_fp_emul_imprecise = do_alpha_fp_emul_imprecise;
73 alpha_fp_emul = do_alpha_fp_emul;
74 return 0;
75 }
76
cleanup_module(void)77 void cleanup_module(void)
78 {
79 alpha_fp_emul_imprecise = save_emul_imprecise;
80 alpha_fp_emul = save_emul;
81 }
82
83 #undef alpha_fp_emul_imprecise
84 #define alpha_fp_emul_imprecise do_alpha_fp_emul_imprecise
85 #undef alpha_fp_emul
86 #define alpha_fp_emul do_alpha_fp_emul
87
88 #endif /* MODULE */
89
90
91 /*
92 * Emulate the floating point instruction at address PC. Returns -1 if the
93 * instruction to be emulated is illegal (such as with the opDEC trap), else
94 * the SI_CODE for a SIGFPE signal, else 0 if everything's ok.
95 *
96 * Notice that the kernel does not and cannot use FP regs. This is good
97 * because it means that instead of saving/restoring all fp regs, we simply
98 * stick the result of the operation into the appropriate register.
99 */
100 long
alpha_fp_emul(unsigned long pc)101 alpha_fp_emul (unsigned long pc)
102 {
103 FP_DECL_EX;
104 FP_DECL_S(SA); FP_DECL_S(SB); FP_DECL_S(SR);
105 FP_DECL_D(DA); FP_DECL_D(DB); FP_DECL_D(DR);
106
107 unsigned long fa, fb, fc, func, mode, src;
108 unsigned long res, va, vb, vc, swcr, fpcr;
109 __u32 insn;
110 long si_code;
111
112 get_user(insn, (__u32 __user *)pc);
113 fc = (insn >> 0) & 0x1f; /* destination register */
114 fb = (insn >> 16) & 0x1f;
115 fa = (insn >> 21) & 0x1f;
116 func = (insn >> 5) & 0xf;
117 src = (insn >> 9) & 0x3;
118 mode = (insn >> 11) & 0x3;
119
120 fpcr = rdfpcr();
121 swcr = swcr_update_status(current_thread_info()->ieee_state, fpcr);
122
123 if (mode == 3) {
124 /* Dynamic -- get rounding mode from fpcr. */
125 mode = (fpcr >> FPCR_DYN_SHIFT) & 3;
126 }
127
128 switch (src) {
129 case FOP_SRC_S:
130 va = alpha_read_fp_reg_s(fa);
131 vb = alpha_read_fp_reg_s(fb);
132
133 FP_UNPACK_SP(SA, &va);
134 FP_UNPACK_SP(SB, &vb);
135
136 switch (func) {
137 case FOP_FNC_SUBx:
138 FP_SUB_S(SR, SA, SB);
139 goto pack_s;
140
141 case FOP_FNC_ADDx:
142 FP_ADD_S(SR, SA, SB);
143 goto pack_s;
144
145 case FOP_FNC_MULx:
146 FP_MUL_S(SR, SA, SB);
147 goto pack_s;
148
149 case FOP_FNC_DIVx:
150 FP_DIV_S(SR, SA, SB);
151 goto pack_s;
152
153 case FOP_FNC_SQRTx:
154 FP_SQRT_S(SR, SB);
155 goto pack_s;
156 }
157 goto bad_insn;
158
159 case FOP_SRC_T:
160 va = alpha_read_fp_reg(fa);
161 vb = alpha_read_fp_reg(fb);
162
163 if ((func & ~3) == FOP_FNC_CMPxUN) {
164 FP_UNPACK_RAW_DP(DA, &va);
165 FP_UNPACK_RAW_DP(DB, &vb);
166 if (!DA_e && !_FP_FRAC_ZEROP_1(DA)) {
167 FP_SET_EXCEPTION(FP_EX_DENORM);
168 if (FP_DENORM_ZERO)
169 _FP_FRAC_SET_1(DA, _FP_ZEROFRAC_1);
170 }
171 if (!DB_e && !_FP_FRAC_ZEROP_1(DB)) {
172 FP_SET_EXCEPTION(FP_EX_DENORM);
173 if (FP_DENORM_ZERO)
174 _FP_FRAC_SET_1(DB, _FP_ZEROFRAC_1);
175 }
176 FP_CMP_D(res, DA, DB, 3);
177 vc = 0x4000000000000000UL;
178 /* CMPTEQ, CMPTUN don't trap on QNaN,
179 while CMPTLT and CMPTLE do */
180 if (res == 3
181 && ((func & 3) >= 2
182 || FP_ISSIGNAN_D(DA)
183 || FP_ISSIGNAN_D(DB))) {
184 FP_SET_EXCEPTION(FP_EX_INVALID);
185 }
186 switch (func) {
187 case FOP_FNC_CMPxUN: if (res != 3) vc = 0; break;
188 case FOP_FNC_CMPxEQ: if (res) vc = 0; break;
189 case FOP_FNC_CMPxLT: if (res != -1) vc = 0; break;
190 case FOP_FNC_CMPxLE: if ((long)res > 0) vc = 0; break;
191 }
192 goto done_d;
193 }
194
195 FP_UNPACK_DP(DA, &va);
196 FP_UNPACK_DP(DB, &vb);
197
198 switch (func) {
199 case FOP_FNC_SUBx:
200 FP_SUB_D(DR, DA, DB);
201 goto pack_d;
202
203 case FOP_FNC_ADDx:
204 FP_ADD_D(DR, DA, DB);
205 goto pack_d;
206
207 case FOP_FNC_MULx:
208 FP_MUL_D(DR, DA, DB);
209 goto pack_d;
210
211 case FOP_FNC_DIVx:
212 FP_DIV_D(DR, DA, DB);
213 goto pack_d;
214
215 case FOP_FNC_SQRTx:
216 FP_SQRT_D(DR, DB);
217 goto pack_d;
218
219 case FOP_FNC_CVTxS:
220 /* It is irritating that DEC encoded CVTST with
221 SRC == T_floating. It is also interesting that
222 the bit used to tell the two apart is /U... */
223 if (insn & 0x2000) {
224 FP_CONV(S,D,1,1,SR,DB);
225 goto pack_s;
226 } else {
227 vb = alpha_read_fp_reg_s(fb);
228 FP_UNPACK_SP(SB, &vb);
229 DR_c = DB_c;
230 DR_s = DB_s;
231 DR_e = DB_e + (1024 - 128);
232 DR_f = SB_f << (52 - 23);
233 goto pack_d;
234 }
235
236 case FOP_FNC_CVTxQ:
237 if (DB_c == FP_CLS_NAN
238 && (_FP_FRAC_HIGH_RAW_D(DB) & _FP_QNANBIT_D)) {
239 /* AAHB Table B-2 says QNaN should not trigger INV */
240 vc = 0;
241 } else
242 FP_TO_INT_ROUND_D(vc, DB, 64, 2);
243 goto done_d;
244 }
245 goto bad_insn;
246
247 case FOP_SRC_Q:
248 vb = alpha_read_fp_reg(fb);
249
250 switch (func) {
251 case FOP_FNC_CVTQL:
252 /* Notice: We can get here only due to an integer
253 overflow. Such overflows are reported as invalid
254 ops. We return the result the hw would have
255 computed. */
256 vc = ((vb & 0xc0000000) << 32 | /* sign and msb */
257 (vb & 0x3fffffff) << 29); /* rest of the int */
258 FP_SET_EXCEPTION (FP_EX_INVALID);
259 goto done_d;
260
261 case FOP_FNC_CVTxS:
262 FP_FROM_INT_S(SR, ((long)vb), 64, long);
263 goto pack_s;
264
265 case FOP_FNC_CVTxT:
266 FP_FROM_INT_D(DR, ((long)vb), 64, long);
267 goto pack_d;
268 }
269 goto bad_insn;
270 }
271 goto bad_insn;
272
273 pack_s:
274 FP_PACK_SP(&vc, SR);
275 if ((_fex & FP_EX_UNDERFLOW) && (swcr & IEEE_MAP_UMZ))
276 vc = 0;
277 alpha_write_fp_reg_s(fc, vc);
278 goto done;
279
280 pack_d:
281 FP_PACK_DP(&vc, DR);
282 if ((_fex & FP_EX_UNDERFLOW) && (swcr & IEEE_MAP_UMZ))
283 vc = 0;
284 done_d:
285 alpha_write_fp_reg(fc, vc);
286 goto done;
287
288 /*
289 * Take the appropriate action for each possible
290 * floating-point result:
291 *
292 * - Set the appropriate bits in the FPCR
293 * - If the specified exception is enabled in the FPCR,
294 * return. The caller (entArith) will dispatch
295 * the appropriate signal to the translated program.
296 *
297 * In addition, properly track the exception state in software
298 * as described in the Alpha Architecture Handbook section 4.7.7.3.
299 */
300 done:
301 if (_fex) {
302 /* Record exceptions in software control word. */
303 swcr |= (_fex << IEEE_STATUS_TO_EXCSUM_SHIFT);
304 current_thread_info()->ieee_state
305 |= (_fex << IEEE_STATUS_TO_EXCSUM_SHIFT);
306
307 /* Update hardware control register. */
308 fpcr &= (~FPCR_MASK | FPCR_DYN_MASK);
309 fpcr |= ieee_swcr_to_fpcr(swcr);
310 wrfpcr(fpcr);
311
312 /* Do we generate a signal? */
313 _fex = _fex & swcr & IEEE_TRAP_ENABLE_MASK;
314 si_code = 0;
315 if (_fex) {
316 if (_fex & IEEE_TRAP_ENABLE_DNO) si_code = FPE_FLTUND;
317 if (_fex & IEEE_TRAP_ENABLE_INE) si_code = FPE_FLTRES;
318 if (_fex & IEEE_TRAP_ENABLE_UNF) si_code = FPE_FLTUND;
319 if (_fex & IEEE_TRAP_ENABLE_OVF) si_code = FPE_FLTOVF;
320 if (_fex & IEEE_TRAP_ENABLE_DZE) si_code = FPE_FLTDIV;
321 if (_fex & IEEE_TRAP_ENABLE_INV) si_code = FPE_FLTINV;
322 }
323
324 return si_code;
325 }
326
327 /* We used to write the destination register here, but DEC FORTRAN
328 requires that the result *always* be written... so we do the write
329 immediately after the operations above. */
330
331 return 0;
332
333 bad_insn:
334 printk(KERN_ERR "alpha_fp_emul: Invalid FP insn %#x at %#lx\n",
335 insn, pc);
336 return -1;
337 }
338
339 long
alpha_fp_emul_imprecise(struct pt_regs * regs,unsigned long write_mask)340 alpha_fp_emul_imprecise (struct pt_regs *regs, unsigned long write_mask)
341 {
342 unsigned long trigger_pc = regs->pc - 4;
343 unsigned long insn, opcode, rc, si_code = 0;
344
345 /*
346 * Turn off the bits corresponding to registers that are the
347 * target of instructions that set bits in the exception
348 * summary register. We have some slack doing this because a
349 * register that is the target of a trapping instruction can
350 * be written at most once in the trap shadow.
351 *
352 * Branches, jumps, TRAPBs, EXCBs and calls to PALcode all
353 * bound the trap shadow, so we need not look any further than
354 * up to the first occurrence of such an instruction.
355 */
356 while (write_mask) {
357 get_user(insn, (__u32 __user *)(trigger_pc));
358 opcode = insn >> 26;
359 rc = insn & 0x1f;
360
361 switch (opcode) {
362 case OPC_PAL:
363 case OPC_JSR:
364 case 0x30 ... 0x3f: /* branches */
365 goto egress;
366
367 case OPC_MISC:
368 switch (insn & 0xffff) {
369 case MISC_TRAPB:
370 case MISC_EXCB:
371 goto egress;
372
373 default:
374 break;
375 }
376 break;
377
378 case OPC_INTA:
379 case OPC_INTL:
380 case OPC_INTS:
381 case OPC_INTM:
382 write_mask &= ~(1UL << rc);
383 break;
384
385 case OPC_FLTC:
386 case OPC_FLTV:
387 case OPC_FLTI:
388 case OPC_FLTL:
389 write_mask &= ~(1UL << (rc + 32));
390 break;
391 }
392 if (!write_mask) {
393 /* Re-execute insns in the trap-shadow. */
394 regs->pc = trigger_pc + 4;
395 si_code = alpha_fp_emul(trigger_pc);
396 goto egress;
397 }
398 trigger_pc -= 4;
399 }
400
401 egress:
402 return si_code;
403 }
404
