1 // SPDX-License-Identifier: GPL-2.0+
2 /* comedi/drivers/amplc_dio200_pci.c
3 *
4 * Driver for Amplicon PCI215, PCI272, PCIe215, PCIe236, PCIe296.
5 *
6 * Copyright (C) 2005-2013 MEV Ltd. <https://www.mev.co.uk/>
7 *
8 * COMEDI - Linux Control and Measurement Device Interface
9 * Copyright (C) 1998,2000 David A. Schleef <ds@schleef.org>
10 */
11
12 /*
13 * Driver: amplc_dio200_pci
14 * Description: Amplicon 200 Series PCI Digital I/O
15 * Author: Ian Abbott <abbotti@mev.co.uk>
16 * Devices: [Amplicon] PCI215 (amplc_dio200_pci), PCIe215, PCIe236,
17 * PCI272, PCIe296
18 * Updated: Mon, 18 Mar 2013 15:03:50 +0000
19 * Status: works
20 *
21 * Configuration options:
22 * none
23 *
24 * Manual configuration of PCI(e) cards is not supported; they are configured
25 * automatically.
26 *
27 * SUBDEVICES
28 *
29 * PCI215 PCIe215 PCIe236
30 * ------------- ------------- -------------
31 * Subdevices 5 8 8
32 * 0 PPI-X PPI-X PPI-X
33 * 1 PPI-Y UNUSED UNUSED
34 * 2 CTR-Z1 PPI-Y UNUSED
35 * 3 CTR-Z2 UNUSED UNUSED
36 * 4 INTERRUPT CTR-Z1 CTR-Z1
37 * 5 CTR-Z2 CTR-Z2
38 * 6 TIMER TIMER
39 * 7 INTERRUPT INTERRUPT
40 *
41 *
42 * PCI272 PCIe296
43 * ------------- -------------
44 * Subdevices 4 8
45 * 0 PPI-X PPI-X1
46 * 1 PPI-Y PPI-X2
47 * 2 PPI-Z PPI-Y1
48 * 3 INTERRUPT PPI-Y2
49 * 4 CTR-Z1
50 * 5 CTR-Z2
51 * 6 TIMER
52 * 7 INTERRUPT
53 *
54 * Each PPI is a 8255 chip providing 24 DIO channels. The DIO channels
55 * are configurable as inputs or outputs in four groups:
56 *
57 * Port A - channels 0 to 7
58 * Port B - channels 8 to 15
59 * Port CL - channels 16 to 19
60 * Port CH - channels 20 to 23
61 *
62 * Only mode 0 of the 8255 chips is supported.
63 *
64 * Each CTR is a 8254 chip providing 3 16-bit counter channels. Each
65 * channel is configured individually with INSN_CONFIG instructions. The
66 * specific type of configuration instruction is specified in data[0].
67 * Some configuration instructions expect an additional parameter in
68 * data[1]; others return a value in data[1]. The following configuration
69 * instructions are supported:
70 *
71 * INSN_CONFIG_SET_COUNTER_MODE. Sets the counter channel's mode and
72 * BCD/binary setting specified in data[1].
73 *
74 * INSN_CONFIG_8254_READ_STATUS. Reads the status register value for the
75 * counter channel into data[1].
76 *
77 * INSN_CONFIG_SET_CLOCK_SRC. Sets the counter channel's clock source as
78 * specified in data[1] (this is a hardware-specific value). Not
79 * supported on PC214E. For the other boards, valid clock sources are
80 * 0 to 7 as follows:
81 *
82 * 0. CLK n, the counter channel's dedicated CLK input from the SK1
83 * connector. (N.B. for other values, the counter channel's CLKn
84 * pin on the SK1 connector is an output!)
85 * 1. Internal 10 MHz clock.
86 * 2. Internal 1 MHz clock.
87 * 3. Internal 100 kHz clock.
88 * 4. Internal 10 kHz clock.
89 * 5. Internal 1 kHz clock.
90 * 6. OUT n-1, the output of counter channel n-1 (see note 1 below).
91 * 7. Ext Clock, the counter chip's dedicated Ext Clock input from
92 * the SK1 connector. This pin is shared by all three counter
93 * channels on the chip.
94 *
95 * For the PCIe boards, clock sources in the range 0 to 31 are allowed
96 * and the following additional clock sources are defined:
97 *
98 * 8. HIGH logic level.
99 * 9. LOW logic level.
100 * 10. "Pattern present" signal.
101 * 11. Internal 20 MHz clock.
102 *
103 * INSN_CONFIG_GET_CLOCK_SRC. Returns the counter channel's current
104 * clock source in data[1]. For internal clock sources, data[2] is set
105 * to the period in ns.
106 *
107 * INSN_CONFIG_SET_GATE_SRC. Sets the counter channel's gate source as
108 * specified in data[2] (this is a hardware-specific value). Not
109 * supported on PC214E. For the other boards, valid gate sources are 0
110 * to 7 as follows:
111 *
112 * 0. VCC (internal +5V d.c.), i.e. gate permanently enabled.
113 * 1. GND (internal 0V d.c.), i.e. gate permanently disabled.
114 * 2. GAT n, the counter channel's dedicated GAT input from the SK1
115 * connector. (N.B. for other values, the counter channel's GATn
116 * pin on the SK1 connector is an output!)
117 * 3. /OUT n-2, the inverted output of counter channel n-2 (see note
118 * 2 below).
119 * 4. Reserved.
120 * 5. Reserved.
121 * 6. Reserved.
122 * 7. Reserved.
123 *
124 * For the PCIe boards, gate sources in the range 0 to 31 are allowed;
125 * the following additional clock sources and clock sources 6 and 7 are
126 * (re)defined:
127 *
128 * 6. /GAT n, negated version of the counter channel's dedicated
129 * GAT input (negated version of gate source 2).
130 * 7. OUT n-2, the non-inverted output of counter channel n-2
131 * (negated version of gate source 3).
132 * 8. "Pattern present" signal, HIGH while pattern present.
133 * 9. "Pattern occurred" latched signal, latches HIGH when pattern
134 * occurs.
135 * 10. "Pattern gone away" latched signal, latches LOW when pattern
136 * goes away after it occurred.
137 * 11. Negated "pattern present" signal, LOW while pattern present
138 * (negated version of gate source 8).
139 * 12. Negated "pattern occurred" latched signal, latches LOW when
140 * pattern occurs (negated version of gate source 9).
141 * 13. Negated "pattern gone away" latched signal, latches LOW when
142 * pattern goes away after it occurred (negated version of gate
143 * source 10).
144 *
145 * INSN_CONFIG_GET_GATE_SRC. Returns the counter channel's current gate
146 * source in data[2].
147 *
148 * Clock and gate interconnection notes:
149 *
150 * 1. Clock source OUT n-1 is the output of the preceding channel on the
151 * same counter subdevice if n > 0, or the output of channel 2 on the
152 * preceding counter subdevice (see note 3) if n = 0.
153 *
154 * 2. Gate source /OUT n-2 is the inverted output of channel 0 on the
155 * same counter subdevice if n = 2, or the inverted output of channel n+1
156 * on the preceding counter subdevice (see note 3) if n < 2.
157 *
158 * 3. The counter subdevices are connected in a ring, so the highest
159 * counter subdevice precedes the lowest.
160 *
161 * The 'TIMER' subdevice is a free-running 32-bit timer subdevice.
162 *
163 * The 'INTERRUPT' subdevice pretends to be a digital input subdevice. The
164 * digital inputs come from the interrupt status register. The number of
165 * channels matches the number of interrupt sources. The PC214E does not
166 * have an interrupt status register; see notes on 'INTERRUPT SOURCES'
167 * below.
168 *
169 * INTERRUPT SOURCES
170 *
171 * PCI215 PCIe215 PCIe236
172 * ------------- ------------- -------------
173 * Sources 6 6 6
174 * 0 PPI-X-C0 PPI-X-C0 PPI-X-C0
175 * 1 PPI-X-C3 PPI-X-C3 PPI-X-C3
176 * 2 PPI-Y-C0 PPI-Y-C0 unused
177 * 3 PPI-Y-C3 PPI-Y-C3 unused
178 * 4 CTR-Z1-OUT1 CTR-Z1-OUT1 CTR-Z1-OUT1
179 * 5 CTR-Z2-OUT1 CTR-Z2-OUT1 CTR-Z2-OUT1
180 *
181 * PCI272 PCIe296
182 * ------------- -------------
183 * Sources 6 6
184 * 0 PPI-X-C0 PPI-X1-C0
185 * 1 PPI-X-C3 PPI-X1-C3
186 * 2 PPI-Y-C0 PPI-Y1-C0
187 * 3 PPI-Y-C3 PPI-Y1-C3
188 * 4 PPI-Z-C0 CTR-Z1-OUT1
189 * 5 PPI-Z-C3 CTR-Z2-OUT1
190 *
191 * When an interrupt source is enabled in the interrupt source enable
192 * register, a rising edge on the source signal latches the corresponding
193 * bit to 1 in the interrupt status register.
194 *
195 * When the interrupt status register value as a whole (actually, just the
196 * 6 least significant bits) goes from zero to non-zero, the board will
197 * generate an interrupt. The interrupt will remain asserted until the
198 * interrupt status register is cleared to zero. To clear a bit to zero in
199 * the interrupt status register, the corresponding interrupt source must
200 * be disabled in the interrupt source enable register (there is no
201 * separate interrupt clear register).
202 *
203 * COMMANDS
204 *
205 * The driver supports a read streaming acquisition command on the
206 * 'INTERRUPT' subdevice. The channel list selects the interrupt sources
207 * to be enabled. All channels will be sampled together (convert_src ==
208 * TRIG_NOW). The scan begins a short time after the hardware interrupt
209 * occurs, subject to interrupt latencies (scan_begin_src == TRIG_EXT,
210 * scan_begin_arg == 0). The value read from the interrupt status register
211 * is packed into a short value, one bit per requested channel, in the
212 * order they appear in the channel list.
213 */
214
215 #include <linux/module.h>
216 #include <linux/interrupt.h>
217
218 #include "../comedi_pci.h"
219
220 #include "amplc_dio200.h"
221
222 /*
223 * Board descriptions.
224 */
225
226 enum dio200_pci_model {
227 pci215_model,
228 pci272_model,
229 pcie215_model,
230 pcie236_model,
231 pcie296_model
232 };
233
234 static const struct dio200_board dio200_pci_boards[] = {
235 [pci215_model] = {
236 .name = "pci215",
237 .mainbar = 2,
238 .n_subdevs = 5,
239 .sdtype = {
240 sd_8255, sd_8255, sd_8254, sd_8254, sd_intr
241 },
242 .sdinfo = { 0x00, 0x08, 0x10, 0x14, 0x3f },
243 .has_int_sce = true,
244 .has_clk_gat_sce = true,
245 },
246 [pci272_model] = {
247 .name = "pci272",
248 .mainbar = 2,
249 .n_subdevs = 4,
250 .sdtype = {
251 sd_8255, sd_8255, sd_8255, sd_intr
252 },
253 .sdinfo = { 0x00, 0x08, 0x10, 0x3f },
254 .has_int_sce = true,
255 },
256 [pcie215_model] = {
257 .name = "pcie215",
258 .mainbar = 1,
259 .n_subdevs = 8,
260 .sdtype = {
261 sd_8255, sd_none, sd_8255, sd_none,
262 sd_8254, sd_8254, sd_timer, sd_intr
263 },
264 .sdinfo = {
265 0x00, 0x00, 0x08, 0x00, 0x10, 0x14, 0x00, 0x3f
266 },
267 .has_int_sce = true,
268 .has_clk_gat_sce = true,
269 .is_pcie = true,
270 },
271 [pcie236_model] = {
272 .name = "pcie236",
273 .mainbar = 1,
274 .n_subdevs = 8,
275 .sdtype = {
276 sd_8255, sd_none, sd_none, sd_none,
277 sd_8254, sd_8254, sd_timer, sd_intr
278 },
279 .sdinfo = {
280 0x00, 0x00, 0x00, 0x00, 0x10, 0x14, 0x00, 0x3f
281 },
282 .has_int_sce = true,
283 .has_clk_gat_sce = true,
284 .is_pcie = true,
285 },
286 [pcie296_model] = {
287 .name = "pcie296",
288 .mainbar = 1,
289 .n_subdevs = 8,
290 .sdtype = {
291 sd_8255, sd_8255, sd_8255, sd_8255,
292 sd_8254, sd_8254, sd_timer, sd_intr
293 },
294 .sdinfo = {
295 0x00, 0x04, 0x08, 0x0c, 0x10, 0x14, 0x00, 0x3f
296 },
297 .has_int_sce = true,
298 .has_clk_gat_sce = true,
299 .is_pcie = true,
300 },
301 };
302
303 /*
304 * This function does some special set-up for the PCIe boards
305 * PCIe215, PCIe236, PCIe296.
306 */
dio200_pcie_board_setup(struct comedi_device * dev)307 static int dio200_pcie_board_setup(struct comedi_device *dev)
308 {
309 struct pci_dev *pcidev = comedi_to_pci_dev(dev);
310 void __iomem *brbase;
311
312 /*
313 * The board uses Altera Cyclone IV with PCI-Express hard IP.
314 * The FPGA configuration has the PCI-Express Avalon-MM Bridge
315 * Control registers in PCI BAR 0, offset 0, and the length of
316 * these registers is 0x4000.
317 *
318 * We need to write 0x80 to the "Avalon-MM to PCI-Express Interrupt
319 * Enable" register at offset 0x50 to allow generation of PCIe
320 * interrupts when RXmlrq_i is asserted in the SOPC Builder system.
321 */
322 if (pci_resource_len(pcidev, 0) < 0x4000) {
323 dev_err(dev->class_dev, "error! bad PCI region!\n");
324 return -EINVAL;
325 }
326 brbase = pci_ioremap_bar(pcidev, 0);
327 if (!brbase) {
328 dev_err(dev->class_dev, "error! failed to map registers!\n");
329 return -ENOMEM;
330 }
331 writel(0x80, brbase + 0x50);
332 iounmap(brbase);
333 /* Enable "enhanced" features of board. */
334 amplc_dio200_set_enhance(dev, 1);
335 return 0;
336 }
337
dio200_pci_auto_attach(struct comedi_device * dev,unsigned long context_model)338 static int dio200_pci_auto_attach(struct comedi_device *dev,
339 unsigned long context_model)
340 {
341 struct pci_dev *pci_dev = comedi_to_pci_dev(dev);
342 const struct dio200_board *board = NULL;
343 unsigned int bar;
344 int ret;
345
346 if (context_model < ARRAY_SIZE(dio200_pci_boards))
347 board = &dio200_pci_boards[context_model];
348 if (!board)
349 return -EINVAL;
350 dev->board_ptr = board;
351 dev->board_name = board->name;
352
353 dev_info(dev->class_dev, "%s: attach pci %s (%s)\n",
354 dev->driver->driver_name, pci_name(pci_dev), dev->board_name);
355
356 ret = comedi_pci_enable(dev);
357 if (ret)
358 return ret;
359
360 bar = board->mainbar;
361 if (pci_resource_flags(pci_dev, bar) & IORESOURCE_MEM) {
362 dev->mmio = pci_ioremap_bar(pci_dev, bar);
363 if (!dev->mmio) {
364 dev_err(dev->class_dev,
365 "error! cannot remap registers\n");
366 return -ENOMEM;
367 }
368 } else {
369 dev->iobase = pci_resource_start(pci_dev, bar);
370 }
371
372 if (board->is_pcie) {
373 ret = dio200_pcie_board_setup(dev);
374 if (ret < 0)
375 return ret;
376 }
377
378 return amplc_dio200_common_attach(dev, pci_dev->irq, IRQF_SHARED);
379 }
380
381 static struct comedi_driver dio200_pci_comedi_driver = {
382 .driver_name = "amplc_dio200_pci",
383 .module = THIS_MODULE,
384 .auto_attach = dio200_pci_auto_attach,
385 .detach = comedi_pci_detach,
386 };
387
388 static const struct pci_device_id dio200_pci_table[] = {
389 { PCI_VDEVICE(AMPLICON, 0x000b), pci215_model },
390 { PCI_VDEVICE(AMPLICON, 0x000a), pci272_model },
391 { PCI_VDEVICE(AMPLICON, 0x0011), pcie236_model },
392 { PCI_VDEVICE(AMPLICON, 0x0012), pcie215_model },
393 { PCI_VDEVICE(AMPLICON, 0x0014), pcie296_model },
394 {0}
395 };
396
397 MODULE_DEVICE_TABLE(pci, dio200_pci_table);
398
dio200_pci_probe(struct pci_dev * dev,const struct pci_device_id * id)399 static int dio200_pci_probe(struct pci_dev *dev, const struct pci_device_id *id)
400 {
401 return comedi_pci_auto_config(dev, &dio200_pci_comedi_driver,
402 id->driver_data);
403 }
404
405 static struct pci_driver dio200_pci_pci_driver = {
406 .name = "amplc_dio200_pci",
407 .id_table = dio200_pci_table,
408 .probe = dio200_pci_probe,
409 .remove = comedi_pci_auto_unconfig,
410 };
411 module_comedi_pci_driver(dio200_pci_comedi_driver, dio200_pci_pci_driver);
412
413 MODULE_AUTHOR("Comedi https://www.comedi.org");
414 MODULE_DESCRIPTION("Comedi driver for Amplicon 200 Series PCI(e) DIO boards");
415 MODULE_LICENSE("GPL");
416
