1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * Device Tree Source for AM33XX SoC 4 * 5 * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/ 6 */ 7 8#include <dt-bindings/bus/ti-sysc.h> 9#include <dt-bindings/gpio/gpio.h> 10#include <dt-bindings/pinctrl/am33xx.h> 11#include <dt-bindings/clock/am3.h> 12 13/ { 14 compatible = "ti,am33xx"; 15 interrupt-parent = <&intc>; 16 #address-cells = <1>; 17 #size-cells = <1>; 18 chosen { }; 19 20 aliases { 21 i2c0 = &i2c0; 22 i2c1 = &i2c1; 23 i2c2 = &i2c2; 24 serial0 = &uart0; 25 serial1 = &uart1; 26 serial2 = &uart2; 27 serial3 = &uart3; 28 serial4 = &uart4; 29 serial5 = &uart5; 30 d-can0 = &dcan0; 31 d-can1 = &dcan1; 32 usb0 = &usb0; 33 usb1 = &usb1; 34 phy0 = &usb0_phy; 35 phy1 = &usb1_phy; 36 ethernet0 = &cpsw_port1; 37 ethernet1 = &cpsw_port2; 38 spi0 = &spi0; 39 spi1 = &spi1; 40 mmc0 = &mmc1; 41 mmc1 = &mmc2; 42 mmc2 = &mmc3; 43 }; 44 45 cpus { 46 #address-cells = <1>; 47 #size-cells = <0>; 48 cpu@0 { 49 compatible = "arm,cortex-a8"; 50 enable-method = "ti,am3352"; 51 device_type = "cpu"; 52 reg = <0>; 53 54 operating-points-v2 = <&cpu0_opp_table>; 55 56 clocks = <&dpll_mpu_ck>; 57 clock-names = "cpu"; 58 59 clock-latency = <300000>; /* From omap-cpufreq driver */ 60 cpu-idle-states = <&mpu_gate>; 61 }; 62 63 idle-states { 64 mpu_gate: mpu_gate { 65 compatible = "arm,idle-state"; 66 entry-latency-us = <40>; 67 exit-latency-us = <90>; 68 min-residency-us = <300>; 69 ti,idle-wkup-m3; 70 }; 71 }; 72 }; 73 74 cpu0_opp_table: opp-table { 75 compatible = "operating-points-v2-ti-cpu"; 76 syscon = <&scm_conf>; 77 78 /* 79 * The three following nodes are marked with opp-suspend 80 * because the can not be enabled simultaneously on a 81 * single SoC. 82 */ 83 opp-50-300000000{ 84 /* OPP50 */ 85 opp-hz = /bits/ 64 <300000000>; 86 opp-microvolt = <950000 931000 969000>; 87 opp-supported-hw = <0x06 0x0010>; 88 opp-suspend; 89 }; 90 91 opp-100-275000000{ 92 /* OPP100-1 */ 93 opp-hz = /bits/ 64 <275000000>; 94 opp-microvolt = <1100000 1078000 1122000>; 95 opp-supported-hw = <0x01 0x00FF>; 96 opp-suspend; 97 }; 98 99 opp-100-300000000{ 100 /* OPP100-2 */ 101 opp-hz = /bits/ 64 <300000000>; 102 opp-microvolt = <1100000 1078000 1122000>; 103 opp-supported-hw = <0x06 0x0020>; 104 opp-suspend; 105 }; 106 107 opp-100-500000000{ 108 /* OPP100-3 */ 109 opp-hz = /bits/ 64 <500000000>; 110 opp-microvolt = <1100000 1078000 1122000>; 111 opp-supported-hw = <0x01 0xFFFF>; 112 }; 113 114 opp-100-600000000 { 115 /* OPP100-4 */ 116 opp-hz = /bits/ 64 <600000000>; 117 opp-microvolt = <1100000 1078000 1122000>; 118 opp-supported-hw = <0x06 0x0040>; 119 }; 120 121 opp-120-600000000 { 122 /* OPP120-1 */ 123 opp-hz = /bits/ 64 <600000000>; 124 opp-microvolt = <1200000 1176000 1224000>; 125 opp-supported-hw = <0x01 0xFFFF>; 126 }; 127 128 opp-120-720000000 { 129 /* OPP120-2 */ 130 opp-hz = /bits/ 64 <720000000>; 131 opp-microvolt = <1200000 1176000 1224000>; 132 opp-supported-hw = <0x06 0x0080>; 133 }; 134 135 opp-720000000 { 136 /* OPP Turbo-1 */ 137 opp-hz = /bits/ 64 <720000000>; 138 opp-microvolt = <1260000 1234800 1285200>; 139 opp-supported-hw = <0x01 0xFFFF>; 140 }; 141 142 opp-800000000 { 143 /* OPP Turbo-2 */ 144 opp-hz = /bits/ 64 <800000000>; 145 opp-microvolt = <1260000 1234800 1285200>; 146 opp-supported-hw = <0x06 0x0100>; 147 }; 148 149 opp-1000000000 { 150 /* OPP Nitro */ 151 opp-hz = /bits/ 64 <1000000000>; 152 opp-microvolt = <1325000 1298500 1351500>; 153 opp-supported-hw = <0x04 0x0200>; 154 }; 155 }; 156 157 target-module@4b000000 { 158 compatible = "ti,sysc-omap4-simple", "ti,sysc"; 159 clocks = <&l3_clkctrl AM3_L3_L3_INSTR_CLKCTRL 0>; 160 clock-names = "fck"; 161 ti,no-idle; 162 #address-cells = <1>; 163 #size-cells = <1>; 164 ranges = <0x0 0x4b000000 0x1000000>; 165 166 target-module@140000 { 167 compatible = "ti,sysc-omap4-simple", "ti,sysc"; 168 clocks = <&l3_aon_clkctrl AM3_L3_AON_DEBUGSS_CLKCTRL 0>; 169 clock-names = "fck"; 170 #address-cells = <1>; 171 #size-cells = <1>; 172 ranges = <0x0 0x140000 0xec0000>; 173 174 pmu@0 { 175 compatible = "arm,cortex-a8-pmu"; 176 interrupts = <3>; 177 }; 178 }; 179 }; 180 181 /* 182 * The soc node represents the soc top level view. It is used for IPs 183 * that are not memory mapped in the MPU view or for the MPU itself. 184 */ 185 soc { 186 compatible = "ti,omap-infra"; 187 }; 188 189 /* 190 * XXX: Use a flat representation of the AM33XX interconnect. 191 * The real AM33XX interconnect network is quite complex. Since 192 * it will not bring real advantage to represent that in DT 193 * for the moment, just use a fake OCP bus entry to represent 194 * the whole bus hierarchy. 195 */ 196 ocp: ocp { 197 compatible = "simple-pm-bus"; 198 power-domains = <&prm_per>; 199 clocks = <&l3_clkctrl AM3_L3_L3_MAIN_CLKCTRL 0>; 200 clock-names = "fck"; 201 #address-cells = <1>; 202 #size-cells = <1>; 203 ranges; 204 205 l4_wkup: interconnect@44c00000 { 206 }; 207 l4_per: interconnect@48000000 { 208 }; 209 l4_fw: interconnect@47c00000 { 210 }; 211 l4_fast: interconnect@4a000000 { 212 }; 213 l4_mpuss: interconnect@4b140000 { 214 }; 215 216 intc: interrupt-controller@48200000 { 217 compatible = "ti,am33xx-intc"; 218 interrupt-controller; 219 #interrupt-cells = <1>; 220 reg = <0x48200000 0x1000>; 221 }; 222 223 target-module@49000000 { 224 compatible = "ti,sysc-omap4", "ti,sysc"; 225 reg = <0x49000000 0x4>; 226 reg-names = "rev"; 227 clocks = <&l3_clkctrl AM3_L3_TPCC_CLKCTRL 0>; 228 clock-names = "fck"; 229 #address-cells = <1>; 230 #size-cells = <1>; 231 ranges = <0x0 0x49000000 0x10000>; 232 233 edma: dma@0 { 234 compatible = "ti,edma3-tpcc"; 235 reg = <0 0x10000>; 236 reg-names = "edma3_cc"; 237 interrupts = <12 13 14>; 238 interrupt-names = "edma3_ccint", "edma3_mperr", 239 "edma3_ccerrint"; 240 dma-requests = <64>; 241 #dma-cells = <2>; 242 243 ti,tptcs = <&edma_tptc0 7>, <&edma_tptc1 5>, 244 <&edma_tptc2 0>; 245 246 ti,edma-memcpy-channels = <20 21>; 247 }; 248 }; 249 250 target-module@49800000 { 251 compatible = "ti,sysc-omap4", "ti,sysc"; 252 reg = <0x49800000 0x4>, 253 <0x49800010 0x4>; 254 reg-names = "rev", "sysc"; 255 ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>; 256 ti,sysc-midle = <SYSC_IDLE_FORCE>; 257 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 258 <SYSC_IDLE_SMART>; 259 clocks = <&l3_clkctrl AM3_L3_TPTC0_CLKCTRL 0>; 260 clock-names = "fck"; 261 #address-cells = <1>; 262 #size-cells = <1>; 263 ranges = <0x0 0x49800000 0x100000>; 264 265 edma_tptc0: dma@0 { 266 compatible = "ti,edma3-tptc"; 267 reg = <0 0x100000>; 268 interrupts = <112>; 269 interrupt-names = "edma3_tcerrint"; 270 }; 271 }; 272 273 target-module@49900000 { 274 compatible = "ti,sysc-omap4", "ti,sysc"; 275 reg = <0x49900000 0x4>, 276 <0x49900010 0x4>; 277 reg-names = "rev", "sysc"; 278 ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>; 279 ti,sysc-midle = <SYSC_IDLE_FORCE>; 280 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 281 <SYSC_IDLE_SMART>; 282 clocks = <&l3_clkctrl AM3_L3_TPTC1_CLKCTRL 0>; 283 clock-names = "fck"; 284 #address-cells = <1>; 285 #size-cells = <1>; 286 ranges = <0x0 0x49900000 0x100000>; 287 288 edma_tptc1: dma@0 { 289 compatible = "ti,edma3-tptc"; 290 reg = <0 0x100000>; 291 interrupts = <113>; 292 interrupt-names = "edma3_tcerrint"; 293 }; 294 }; 295 296 target-module@49a00000 { 297 compatible = "ti,sysc-omap4", "ti,sysc"; 298 reg = <0x49a00000 0x4>, 299 <0x49a00010 0x4>; 300 reg-names = "rev", "sysc"; 301 ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>; 302 ti,sysc-midle = <SYSC_IDLE_FORCE>; 303 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 304 <SYSC_IDLE_SMART>; 305 clocks = <&l3_clkctrl AM3_L3_TPTC2_CLKCTRL 0>; 306 clock-names = "fck"; 307 #address-cells = <1>; 308 #size-cells = <1>; 309 ranges = <0x0 0x49a00000 0x100000>; 310 311 edma_tptc2: dma@0 { 312 compatible = "ti,edma3-tptc"; 313 reg = <0 0x100000>; 314 interrupts = <114>; 315 interrupt-names = "edma3_tcerrint"; 316 }; 317 }; 318 319 target-module@47810000 { 320 compatible = "ti,sysc-omap2", "ti,sysc"; 321 reg = <0x478102fc 0x4>, 322 <0x47810110 0x4>, 323 <0x47810114 0x4>; 324 reg-names = "rev", "sysc", "syss"; 325 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | 326 SYSC_OMAP2_ENAWAKEUP | 327 SYSC_OMAP2_SOFTRESET | 328 SYSC_OMAP2_AUTOIDLE)>; 329 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 330 <SYSC_IDLE_NO>, 331 <SYSC_IDLE_SMART>; 332 ti,syss-mask = <1>; 333 clocks = <&l3s_clkctrl AM3_L3S_MMC3_CLKCTRL 0>; 334 clock-names = "fck"; 335 #address-cells = <1>; 336 #size-cells = <1>; 337 ranges = <0x0 0x47810000 0x1000>; 338 339 mmc3: mmc@0 { 340 compatible = "ti,am335-sdhci"; 341 ti,needs-special-reset; 342 interrupts = <29>; 343 reg = <0x0 0x1000>; 344 status = "disabled"; 345 }; 346 }; 347 348 usb: target-module@47400000 { 349 compatible = "ti,sysc-omap4", "ti,sysc"; 350 reg = <0x47400000 0x4>, 351 <0x47400010 0x4>; 352 reg-names = "rev", "sysc"; 353 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | 354 SYSC_OMAP4_SOFTRESET)>; 355 ti,sysc-midle = <SYSC_IDLE_FORCE>, 356 <SYSC_IDLE_NO>, 357 <SYSC_IDLE_SMART>; 358 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 359 <SYSC_IDLE_NO>, 360 <SYSC_IDLE_SMART>, 361 <SYSC_IDLE_SMART_WKUP>; 362 clocks = <&l3s_clkctrl AM3_L3S_USB_OTG_HS_CLKCTRL 0>; 363 clock-names = "fck"; 364 #address-cells = <1>; 365 #size-cells = <1>; 366 ranges = <0x0 0x47400000 0x8000>; 367 368 usb0_phy: usb-phy@1300 { 369 compatible = "ti,am335x-usb-phy"; 370 reg = <0x1300 0x100>; 371 reg-names = "phy"; 372 ti,ctrl_mod = <&usb_ctrl_mod>; 373 #phy-cells = <0>; 374 }; 375 376 usb0: usb@1400 { 377 compatible = "ti,musb-am33xx"; 378 reg = <0x1400 0x400>, 379 <0x1000 0x200>; 380 reg-names = "mc", "control"; 381 382 interrupts = <18>; 383 interrupt-names = "mc"; 384 dr_mode = "otg"; 385 mentor,multipoint = <1>; 386 mentor,num-eps = <16>; 387 mentor,ram-bits = <12>; 388 mentor,power = <500>; 389 phys = <&usb0_phy>; 390 391 dmas = <&cppi41dma 0 0 &cppi41dma 1 0 392 &cppi41dma 2 0 &cppi41dma 3 0 393 &cppi41dma 4 0 &cppi41dma 5 0 394 &cppi41dma 6 0 &cppi41dma 7 0 395 &cppi41dma 8 0 &cppi41dma 9 0 396 &cppi41dma 10 0 &cppi41dma 11 0 397 &cppi41dma 12 0 &cppi41dma 13 0 398 &cppi41dma 14 0 &cppi41dma 0 1 399 &cppi41dma 1 1 &cppi41dma 2 1 400 &cppi41dma 3 1 &cppi41dma 4 1 401 &cppi41dma 5 1 &cppi41dma 6 1 402 &cppi41dma 7 1 &cppi41dma 8 1 403 &cppi41dma 9 1 &cppi41dma 10 1 404 &cppi41dma 11 1 &cppi41dma 12 1 405 &cppi41dma 13 1 &cppi41dma 14 1>; 406 dma-names = 407 "rx1", "rx2", "rx3", "rx4", "rx5", "rx6", "rx7", 408 "rx8", "rx9", "rx10", "rx11", "rx12", "rx13", 409 "rx14", "rx15", 410 "tx1", "tx2", "tx3", "tx4", "tx5", "tx6", "tx7", 411 "tx8", "tx9", "tx10", "tx11", "tx12", "tx13", 412 "tx14", "tx15"; 413 }; 414 415 usb1_phy: usb-phy@1b00 { 416 compatible = "ti,am335x-usb-phy"; 417 reg = <0x1b00 0x100>; 418 reg-names = "phy"; 419 ti,ctrl_mod = <&usb_ctrl_mod>; 420 #phy-cells = <0>; 421 }; 422 423 usb1: usb@1800 { 424 compatible = "ti,musb-am33xx"; 425 reg = <0x1c00 0x400>, 426 <0x1800 0x200>; 427 reg-names = "mc", "control"; 428 interrupts = <19>; 429 interrupt-names = "mc"; 430 dr_mode = "otg"; 431 mentor,multipoint = <1>; 432 mentor,num-eps = <16>; 433 mentor,ram-bits = <12>; 434 mentor,power = <500>; 435 phys = <&usb1_phy>; 436 437 dmas = <&cppi41dma 15 0 &cppi41dma 16 0 438 &cppi41dma 17 0 &cppi41dma 18 0 439 &cppi41dma 19 0 &cppi41dma 20 0 440 &cppi41dma 21 0 &cppi41dma 22 0 441 &cppi41dma 23 0 &cppi41dma 24 0 442 &cppi41dma 25 0 &cppi41dma 26 0 443 &cppi41dma 27 0 &cppi41dma 28 0 444 &cppi41dma 29 0 &cppi41dma 15 1 445 &cppi41dma 16 1 &cppi41dma 17 1 446 &cppi41dma 18 1 &cppi41dma 19 1 447 &cppi41dma 20 1 &cppi41dma 21 1 448 &cppi41dma 22 1 &cppi41dma 23 1 449 &cppi41dma 24 1 &cppi41dma 25 1 450 &cppi41dma 26 1 &cppi41dma 27 1 451 &cppi41dma 28 1 &cppi41dma 29 1>; 452 dma-names = 453 "rx1", "rx2", "rx3", "rx4", "rx5", "rx6", "rx7", 454 "rx8", "rx9", "rx10", "rx11", "rx12", "rx13", 455 "rx14", "rx15", 456 "tx1", "tx2", "tx3", "tx4", "tx5", "tx6", "tx7", 457 "tx8", "tx9", "tx10", "tx11", "tx12", "tx13", 458 "tx14", "tx15"; 459 }; 460 461 cppi41dma: dma-controller@2000 { 462 compatible = "ti,am3359-cppi41"; 463 reg = <0x0000 0x1000>, 464 <0x2000 0x1000>, 465 <0x3000 0x1000>, 466 <0x4000 0x4000>; 467 reg-names = "glue", "controller", "scheduler", "queuemgr"; 468 interrupts = <17>; 469 interrupt-names = "glue"; 470 #dma-cells = <2>; 471 /* For backwards compatibility: */ 472 #dma-channels = <30>; 473 dma-channels = <30>; 474 #dma-requests = <256>; 475 dma-requests = <256>; 476 }; 477 }; 478 479 target-module@40300000 { 480 compatible = "ti,sysc-omap4-simple", "ti,sysc"; 481 clocks = <&l3_clkctrl AM3_L3_OCMCRAM_CLKCTRL 0>; 482 clock-names = "fck"; 483 ti,no-idle; 484 #address-cells = <1>; 485 #size-cells = <1>; 486 ranges = <0 0x40300000 0x10000>; 487 488 ocmcram: sram@0 { 489 compatible = "mmio-sram"; 490 reg = <0 0x10000>; /* 64k */ 491 ranges = <0 0 0x10000>; 492 #address-cells = <1>; 493 #size-cells = <1>; 494 495 pm_sram_code: pm-code-sram@0 { 496 compatible = "ti,sram"; 497 reg = <0x0 0x1000>; 498 protect-exec; 499 }; 500 501 pm_sram_data: pm-data-sram@1000 { 502 compatible = "ti,sram"; 503 reg = <0x1000 0x1000>; 504 pool; 505 }; 506 }; 507 }; 508 509 target-module@4c000000 { 510 compatible = "ti,sysc-omap4-simple", "ti,sysc"; 511 reg = <0x4c000000 0x4>; 512 reg-names = "rev"; 513 clocks = <&l3_clkctrl AM3_L3_EMIF_CLKCTRL 0>; 514 clock-names = "fck"; 515 ti,no-idle; 516 #address-cells = <1>; 517 #size-cells = <1>; 518 ranges = <0x0 0x4c000000 0x1000000>; 519 520 emif: emif@0 { 521 compatible = "ti,emif-am3352"; 522 reg = <0 0x1000000>; 523 interrupts = <101>; 524 sram = <&pm_sram_code 525 &pm_sram_data>; 526 }; 527 }; 528 529 target-module@50000000 { 530 compatible = "ti,sysc-omap2", "ti,sysc"; 531 reg = <0x50000000 4>, 532 <0x50000010 4>, 533 <0x50000014 4>; 534 reg-names = "rev", "sysc", "syss"; 535 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 536 <SYSC_IDLE_NO>, 537 <SYSC_IDLE_SMART>; 538 ti,syss-mask = <1>; 539 clocks = <&l3s_clkctrl AM3_L3S_GPMC_CLKCTRL 0>; 540 clock-names = "fck"; 541 #address-cells = <1>; 542 #size-cells = <1>; 543 ranges = <0x50000000 0x50000000 0x00001000>, /* regs */ 544 <0x00000000 0x00000000 0x40000000>; /* data */ 545 546 gpmc: gpmc@50000000 { 547 compatible = "ti,am3352-gpmc"; 548 reg = <0x50000000 0x2000>; 549 interrupts = <100>; 550 dmas = <&edma 52 0>; 551 dma-names = "rxtx"; 552 gpmc,num-cs = <7>; 553 gpmc,num-waitpins = <2>; 554 #address-cells = <2>; 555 #size-cells = <1>; 556 interrupt-controller; 557 #interrupt-cells = <2>; 558 gpio-controller; 559 #gpio-cells = <2>; 560 status = "disabled"; 561 }; 562 }; 563 564 sham_target: target-module@53100000 { 565 compatible = "ti,sysc-omap3-sham", "ti,sysc"; 566 reg = <0x53100100 0x4>, 567 <0x53100110 0x4>, 568 <0x53100114 0x4>; 569 reg-names = "rev", "sysc", "syss"; 570 ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET | 571 SYSC_OMAP2_AUTOIDLE)>; 572 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 573 <SYSC_IDLE_NO>, 574 <SYSC_IDLE_SMART>; 575 ti,syss-mask = <1>; 576 /* Domains (P, C): per_pwrdm, l3_clkdm */ 577 clocks = <&l3_clkctrl AM3_L3_SHAM_CLKCTRL 0>; 578 clock-names = "fck"; 579 #address-cells = <1>; 580 #size-cells = <1>; 581 ranges = <0x0 0x53100000 0x1000>; 582 583 sham: sham@0 { 584 compatible = "ti,omap4-sham"; 585 reg = <0 0x200>; 586 interrupts = <109>; 587 dmas = <&edma 36 0>; 588 dma-names = "rx"; 589 }; 590 }; 591 592 aes_target: target-module@53500000 { 593 compatible = "ti,sysc-omap2", "ti,sysc"; 594 reg = <0x53500080 0x4>, 595 <0x53500084 0x4>, 596 <0x53500088 0x4>; 597 reg-names = "rev", "sysc", "syss"; 598 ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET | 599 SYSC_OMAP2_AUTOIDLE)>; 600 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 601 <SYSC_IDLE_NO>, 602 <SYSC_IDLE_SMART>, 603 <SYSC_IDLE_SMART_WKUP>; 604 ti,syss-mask = <1>; 605 /* Domains (P, C): per_pwrdm, l3_clkdm */ 606 clocks = <&l3_clkctrl AM3_L3_AES_CLKCTRL 0>; 607 clock-names = "fck"; 608 #address-cells = <1>; 609 #size-cells = <1>; 610 ranges = <0x0 0x53500000 0x1000>; 611 612 aes: aes@0 { 613 compatible = "ti,omap4-aes"; 614 reg = <0 0xa0>; 615 interrupts = <103>; 616 dmas = <&edma 6 0>, 617 <&edma 5 0>; 618 dma-names = "tx", "rx"; 619 }; 620 }; 621 622 target-module@56000000 { 623 compatible = "ti,sysc-omap4", "ti,sysc"; 624 reg = <0x5600fe00 0x4>, 625 <0x5600fe10 0x4>; 626 reg-names = "rev", "sysc"; 627 ti,sysc-midle = <SYSC_IDLE_FORCE>, 628 <SYSC_IDLE_NO>, 629 <SYSC_IDLE_SMART>; 630 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 631 <SYSC_IDLE_NO>, 632 <SYSC_IDLE_SMART>; 633 clocks = <&gfx_l3_clkctrl AM3_GFX_L3_GFX_CLKCTRL 0>; 634 clock-names = "fck"; 635 power-domains = <&prm_gfx>; 636 resets = <&prm_gfx 0>; 637 reset-names = "rstctrl"; 638 #address-cells = <1>; 639 #size-cells = <1>; 640 ranges = <0 0x56000000 0x1000000>; 641 642 /* 643 * Closed source PowerVR driver, no child device 644 * binding or driver in mainline 645 */ 646 }; 647 }; 648}; 649 650#include "am33xx-l4.dtsi" 651#include "am33xx-clocks.dtsi" 652 653&prcm { 654 prm_per: prm@c00 { 655 compatible = "ti,am3-prm-inst", "ti,omap-prm-inst"; 656 reg = <0xc00 0x100>; 657 #reset-cells = <1>; 658 #power-domain-cells = <0>; 659 }; 660 661 prm_wkup: prm@d00 { 662 compatible = "ti,am3-prm-inst", "ti,omap-prm-inst"; 663 reg = <0xd00 0x100>; 664 #reset-cells = <1>; 665 #power-domain-cells = <0>; 666 }; 667 668 prm_mpu: prm@e00 { 669 compatible = "ti,am3-prm-inst", "ti,omap-prm-inst"; 670 reg = <0xe00 0x100>; 671 #power-domain-cells = <0>; 672 }; 673 674 prm_device: prm@f00 { 675 compatible = "ti,am3-prm-inst", "ti,omap-prm-inst"; 676 reg = <0xf00 0x100>; 677 #reset-cells = <1>; 678 }; 679 680 prm_rtc: prm@1000 { 681 compatible = "ti,am3-prm-inst", "ti,omap-prm-inst"; 682 reg = <0x1000 0x100>; 683 #power-domain-cells = <0>; 684 }; 685 686 prm_gfx: prm@1100 { 687 compatible = "ti,am3-prm-inst", "ti,omap-prm-inst"; 688 reg = <0x1100 0x100>; 689 #power-domain-cells = <0>; 690 #reset-cells = <1>; 691 }; 692 693 prm_cefuse: prm@1200 { 694 compatible = "ti,am3-prm-inst", "ti,omap-prm-inst"; 695 reg = <0x1200 0x100>; 696 #power-domain-cells = <0>; 697 }; 698}; 699 700/* Preferred always-on timer for clocksource */ 701&timer1_target { 702 clocks = <&l4_wkup_clkctrl AM3_L4_WKUP_TIMER1_CLKCTRL 0>, 703 <&l4_wkup_clkctrl AM3_L4_WKUP_L4_WKUP_CLKCTRL 0>; 704 clock-names = "fck", "ick"; 705 ti,no-reset-on-init; 706 ti,no-idle; 707 timer@0 { 708 assigned-clocks = <&timer1_fck>; 709 assigned-clock-parents = <&sys_clkin_ck>; 710 }; 711}; 712 713/* Preferred timer for clockevent */ 714&timer2_target { 715 clocks = <&l4ls_clkctrl AM3_L4LS_TIMER2_CLKCTRL 0>, 716 <&l4ls_clkctrl AM3_L4LS_L4_LS_CLKCTRL 0>; 717 clock-names = "fck", "ick"; 718 ti,no-reset-on-init; 719 ti,no-idle; 720 timer@0 { 721 assigned-clocks = <&timer2_fck>; 722 assigned-clock-parents = <&sys_clkin_ck>; 723 }; 724}; 725
