1&l4_wkup { /* 0x44c00000 */ 2 compatible = "ti,am33xx-l4-wkup", "simple-bus"; 3 reg = <0x44c00000 0x800>, 4 <0x44c00800 0x800>, 5 <0x44c01000 0x400>, 6 <0x44c01400 0x400>; 7 reg-names = "ap", "la", "ia0", "ia1"; 8 #address-cells = <1>; 9 #size-cells = <1>; 10 ranges = <0x00000000 0x44c00000 0x100000>, /* segment 0 */ 11 <0x00100000 0x44d00000 0x100000>, /* segment 1 */ 12 <0x00200000 0x44e00000 0x100000>; /* segment 2 */ 13 14 segment@0 { /* 0x44c00000 */ 15 compatible = "simple-bus"; 16 #address-cells = <1>; 17 #size-cells = <1>; 18 ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */ 19 <0x00000800 0x00000800 0x000800>, /* ap 1 */ 20 <0x00001000 0x00001000 0x000400>, /* ap 2 */ 21 <0x00001400 0x00001400 0x000400>; /* ap 3 */ 22 }; 23 24 segment@100000 { /* 0x44d00000 */ 25 compatible = "simple-bus"; 26 #address-cells = <1>; 27 #size-cells = <1>; 28 ranges = <0x00000000 0x00100000 0x004000>, /* ap 4 */ 29 <0x00004000 0x00104000 0x001000>, /* ap 5 */ 30 <0x00080000 0x00180000 0x002000>, /* ap 6 */ 31 <0x00082000 0x00182000 0x001000>; /* ap 7 */ 32 33 target-module@0 { /* 0x44d00000, ap 4 28.0 */ 34 compatible = "ti,sysc-omap4", "ti,sysc"; 35 reg = <0x0 0x4>; 36 reg-names = "rev"; 37 #address-cells = <1>; 38 #size-cells = <1>; 39 ranges = <0x0 0x0 0x4000>; 40 status = "disabled"; 41 }; 42 43 target-module@80000 { /* 0x44d80000, ap 6 10.0 */ 44 compatible = "ti,sysc"; 45 status = "disabled"; 46 #address-cells = <1>; 47 #size-cells = <1>; 48 ranges = <0x0 0x80000 0x2000>; 49 }; 50 }; 51 52 segment@200000 { /* 0x44e00000 */ 53 compatible = "simple-bus"; 54 #address-cells = <1>; 55 #size-cells = <1>; 56 ranges = <0x00000000 0x00200000 0x002000>, /* ap 8 */ 57 <0x00002000 0x00202000 0x001000>, /* ap 9 */ 58 <0x00003000 0x00203000 0x001000>, /* ap 10 */ 59 <0x00004000 0x00204000 0x001000>, /* ap 11 */ 60 <0x00005000 0x00205000 0x001000>, /* ap 12 */ 61 <0x00006000 0x00206000 0x001000>, /* ap 13 */ 62 <0x00007000 0x00207000 0x001000>, /* ap 14 */ 63 <0x00008000 0x00208000 0x001000>, /* ap 15 */ 64 <0x00009000 0x00209000 0x001000>, /* ap 16 */ 65 <0x0000a000 0x0020a000 0x001000>, /* ap 17 */ 66 <0x0000b000 0x0020b000 0x001000>, /* ap 18 */ 67 <0x0000c000 0x0020c000 0x001000>, /* ap 19 */ 68 <0x0000d000 0x0020d000 0x001000>, /* ap 20 */ 69 <0x0000f000 0x0020f000 0x001000>, /* ap 21 */ 70 <0x00010000 0x00210000 0x010000>, /* ap 22 */ 71 <0x00020000 0x00220000 0x010000>, /* ap 23 */ 72 <0x00030000 0x00230000 0x001000>, /* ap 24 */ 73 <0x00031000 0x00231000 0x001000>, /* ap 25 */ 74 <0x00032000 0x00232000 0x001000>, /* ap 26 */ 75 <0x00033000 0x00233000 0x001000>, /* ap 27 */ 76 <0x00034000 0x00234000 0x001000>, /* ap 28 */ 77 <0x00035000 0x00235000 0x001000>, /* ap 29 */ 78 <0x00036000 0x00236000 0x001000>, /* ap 30 */ 79 <0x00037000 0x00237000 0x001000>, /* ap 31 */ 80 <0x00038000 0x00238000 0x001000>, /* ap 32 */ 81 <0x00039000 0x00239000 0x001000>, /* ap 33 */ 82 <0x0003a000 0x0023a000 0x001000>, /* ap 34 */ 83 <0x0003e000 0x0023e000 0x001000>, /* ap 35 */ 84 <0x0003f000 0x0023f000 0x001000>, /* ap 36 */ 85 <0x0000e000 0x0020e000 0x001000>, /* ap 37 */ 86 <0x00040000 0x00240000 0x040000>, /* ap 38 */ 87 <0x00080000 0x00280000 0x001000>; /* ap 39 */ 88 89 target-module@0 { /* 0x44e00000, ap 8 58.0 */ 90 compatible = "ti,sysc-omap4", "ti,sysc"; 91 reg = <0 0x4>; 92 reg-names = "rev"; 93 #address-cells = <1>; 94 #size-cells = <1>; 95 ranges = <0x0 0x0 0x2000>; 96 97 prcm: prcm@0 { 98 compatible = "ti,am3-prcm", "simple-bus"; 99 reg = <0 0x2000>; 100 #address-cells = <1>; 101 #size-cells = <1>; 102 ranges = <0 0 0x2000>; 103 104 prcm_clocks: clocks { 105 #address-cells = <1>; 106 #size-cells = <0>; 107 }; 108 109 prcm_clockdomains: clockdomains { 110 }; 111 }; 112 }; 113 114 target-module@3000 { /* 0x44e03000, ap 10 0a.0 */ 115 compatible = "ti,sysc"; 116 status = "disabled"; 117 #address-cells = <1>; 118 #size-cells = <1>; 119 ranges = <0x0 0x3000 0x1000>; 120 }; 121 122 target-module@5000 { /* 0x44e05000, ap 12 30.0 */ 123 compatible = "ti,sysc"; 124 status = "disabled"; 125 #address-cells = <1>; 126 #size-cells = <1>; 127 ranges = <0x0 0x5000 0x1000>; 128 }; 129 130 gpio0_target: target-module@7000 { /* 0x44e07000, ap 14 20.0 */ 131 compatible = "ti,sysc-omap2", "ti,sysc"; 132 ti,hwmods = "gpio1"; 133 reg = <0x7000 0x4>, 134 <0x7010 0x4>, 135 <0x7114 0x4>; 136 reg-names = "rev", "sysc", "syss"; 137 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | 138 SYSC_OMAP2_SOFTRESET | 139 SYSC_OMAP2_AUTOIDLE)>; 140 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 141 <SYSC_IDLE_NO>, 142 <SYSC_IDLE_SMART>, 143 <SYSC_IDLE_SMART_WKUP>; 144 ti,syss-mask = <1>; 145 /* Domains (P, C): wkup_pwrdm, l4_wkup_clkdm */ 146 clocks = <&l4_wkup_clkctrl AM3_L4_WKUP_GPIO1_CLKCTRL 0>, 147 <&l4_wkup_clkctrl AM3_L4_WKUP_GPIO1_CLKCTRL 18>; 148 clock-names = "fck", "dbclk"; 149 #address-cells = <1>; 150 #size-cells = <1>; 151 ranges = <0x0 0x7000 0x1000>; 152 153 gpio0: gpio@0 { 154 compatible = "ti,omap4-gpio"; 155 gpio-controller; 156 #gpio-cells = <2>; 157 interrupt-controller; 158 #interrupt-cells = <2>; 159 reg = <0x0 0x1000>; 160 interrupts = <96>; 161 }; 162 }; 163 164 target-module@9000 { /* 0x44e09000, ap 16 04.0 */ 165 compatible = "ti,sysc-omap2", "ti,sysc"; 166 ti,hwmods = "uart1"; 167 reg = <0x9050 0x4>, 168 <0x9054 0x4>, 169 <0x9058 0x4>; 170 reg-names = "rev", "sysc", "syss"; 171 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | 172 SYSC_OMAP2_SOFTRESET | 173 SYSC_OMAP2_AUTOIDLE)>; 174 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 175 <SYSC_IDLE_NO>, 176 <SYSC_IDLE_SMART>, 177 <SYSC_IDLE_SMART_WKUP>; 178 /* Domains (P, C): wkup_pwrdm, l4_wkup_clkdm */ 179 clocks = <&l4_wkup_clkctrl AM3_L4_WKUP_UART1_CLKCTRL 0>; 180 clock-names = "fck"; 181 #address-cells = <1>; 182 #size-cells = <1>; 183 ranges = <0x0 0x9000 0x1000>; 184 185 uart0: serial@0 { 186 compatible = "ti,am3352-uart", "ti,omap3-uart"; 187 clock-frequency = <48000000>; 188 reg = <0x0 0x1000>; 189 interrupts = <72>; 190 status = "disabled"; 191 dmas = <&edma 26 0>, <&edma 27 0>; 192 dma-names = "tx", "rx"; 193 }; 194 }; 195 196 target-module@b000 { /* 0x44e0b000, ap 18 48.0 */ 197 compatible = "ti,sysc-omap2", "ti,sysc"; 198 ti,hwmods = "i2c1"; 199 reg = <0xb000 0x8>, 200 <0xb010 0x8>, 201 <0xb090 0x8>; 202 reg-names = "rev", "sysc", "syss"; 203 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | 204 SYSC_OMAP2_ENAWAKEUP | 205 SYSC_OMAP2_SOFTRESET | 206 SYSC_OMAP2_AUTOIDLE)>; 207 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 208 <SYSC_IDLE_NO>, 209 <SYSC_IDLE_SMART>, 210 <SYSC_IDLE_SMART_WKUP>; 211 ti,syss-mask = <1>; 212 /* Domains (P, C): wkup_pwrdm, l4_wkup_clkdm */ 213 clocks = <&l4_wkup_clkctrl AM3_L4_WKUP_I2C1_CLKCTRL 0>; 214 clock-names = "fck"; 215 #address-cells = <1>; 216 #size-cells = <1>; 217 ranges = <0x0 0xb000 0x1000>; 218 219 i2c0: i2c@0 { 220 compatible = "ti,omap4-i2c"; 221 #address-cells = <1>; 222 #size-cells = <0>; 223 reg = <0x0 0x1000>; 224 interrupts = <70>; 225 status = "disabled"; 226 }; 227 }; 228 229 target-module@d000 { /* 0x44e0d000, ap 20 38.0 */ 230 compatible = "ti,sysc-omap4", "ti,sysc"; 231 ti,hwmods = "adc_tsc"; 232 reg = <0xd000 0x4>, 233 <0xd010 0x4>; 234 reg-names = "rev", "sysc"; 235 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 236 <SYSC_IDLE_NO>, 237 <SYSC_IDLE_SMART>, 238 <SYSC_IDLE_SMART_WKUP>; 239 /* Domains (P, C): wkup_pwrdm, l4_wkup_clkdm */ 240 clocks = <&l4_wkup_clkctrl AM3_L4_WKUP_ADC_TSC_CLKCTRL 0>; 241 clock-names = "fck"; 242 #address-cells = <1>; 243 #size-cells = <1>; 244 ranges = <0x00000000 0x0000d000 0x00001000>, 245 <0x00001000 0x0000e000 0x00001000>; 246 247 tscadc: tscadc@0 { 248 compatible = "ti,am3359-tscadc"; 249 reg = <0x0 0x1000>; 250 interrupts = <16>; 251 status = "disabled"; 252 dmas = <&edma 53 0>, <&edma 57 0>; 253 dma-names = "fifo0", "fifo1"; 254 255 tsc { 256 compatible = "ti,am3359-tsc"; 257 }; 258 am335x_adc: adc { 259 #io-channel-cells = <1>; 260 compatible = "ti,am3359-adc"; 261 }; 262 }; 263 }; 264 265 target-module@10000 { /* 0x44e10000, ap 22 0c.0 */ 266 compatible = "ti,sysc-omap4", "ti,sysc"; 267 reg = <0x10000 0x4>; 268 reg-names = "rev"; 269 #address-cells = <1>; 270 #size-cells = <1>; 271 ranges = <0x00000000 0x00010000 0x00010000>, 272 <0x00010000 0x00020000 0x00010000>; 273 274 scm: scm@0 { 275 compatible = "ti,am3-scm", "simple-bus"; 276 reg = <0x0 0x2000>; 277 #address-cells = <1>; 278 #size-cells = <1>; 279 #pinctrl-cells = <1>; 280 ranges = <0 0 0x2000>; 281 282 am33xx_pinmux: pinmux@800 { 283 compatible = "pinctrl-single"; 284 reg = <0x800 0x238>; 285 #pinctrl-cells = <1>; 286 pinctrl-single,register-width = <32>; 287 pinctrl-single,function-mask = <0x7f>; 288 }; 289 290 scm_conf: scm_conf@0 { 291 compatible = "syscon", "simple-bus"; 292 reg = <0x0 0x800>; 293 #address-cells = <1>; 294 #size-cells = <1>; 295 ranges = <0 0 0x800>; 296 297 phy_gmii_sel: phy-gmii-sel { 298 compatible = "ti,am3352-phy-gmii-sel"; 299 reg = <0x650 0x4>; 300 #phy-cells = <2>; 301 }; 302 303 scm_clocks: clocks { 304 #address-cells = <1>; 305 #size-cells = <0>; 306 }; 307 }; 308 309 wkup_m3_ipc: wkup_m3_ipc@1324 { 310 compatible = "ti,am3352-wkup-m3-ipc"; 311 reg = <0x1324 0x24>; 312 interrupts = <78>; 313 ti,rproc = <&wkup_m3>; 314 mboxes = <&mailbox &mbox_wkupm3>; 315 }; 316 317 edma_xbar: dma-router@f90 { 318 compatible = "ti,am335x-edma-crossbar"; 319 reg = <0xf90 0x40>; 320 #dma-cells = <3>; 321 dma-requests = <32>; 322 dma-masters = <&edma>; 323 }; 324 325 scm_clockdomains: clockdomains { 326 }; 327 }; 328 }; 329 330 target-module@31000 { /* 0x44e31000, ap 25 40.0 */ 331 compatible = "ti,sysc-omap2-timer", "ti,sysc"; 332 ti,hwmods = "timer1"; 333 reg = <0x31000 0x4>, 334 <0x31010 0x4>, 335 <0x31014 0x4>; 336 reg-names = "rev", "sysc", "syss"; 337 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | 338 SYSC_OMAP2_SOFTRESET | 339 SYSC_OMAP2_AUTOIDLE)>; 340 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 341 <SYSC_IDLE_NO>, 342 <SYSC_IDLE_SMART>; 343 ti,syss-mask = <1>; 344 /* Domains (P, C): wkup_pwrdm, l4_wkup_clkdm */ 345 clocks = <&l4_wkup_clkctrl AM3_L4_WKUP_TIMER1_CLKCTRL 0>; 346 clock-names = "fck"; 347 #address-cells = <1>; 348 #size-cells = <1>; 349 ranges = <0x0 0x31000 0x1000>; 350 351 timer1: timer@0 { 352 compatible = "ti,am335x-timer-1ms"; 353 reg = <0x0 0x400>; 354 interrupts = <67>; 355 ti,timer-alwon; 356 clocks = <&timer1_fck>; 357 clock-names = "fck"; 358 }; 359 }; 360 361 target-module@33000 { /* 0x44e33000, ap 27 18.0 */ 362 compatible = "ti,sysc"; 363 status = "disabled"; 364 #address-cells = <1>; 365 #size-cells = <1>; 366 ranges = <0x0 0x33000 0x1000>; 367 }; 368 369 target-module@35000 { /* 0x44e35000, ap 29 50.0 */ 370 compatible = "ti,sysc-omap2", "ti,sysc"; 371 ti,hwmods = "wd_timer2"; 372 reg = <0x35000 0x4>, 373 <0x35010 0x4>, 374 <0x35014 0x4>; 375 reg-names = "rev", "sysc", "syss"; 376 ti,sysc-mask = <(SYSC_OMAP2_EMUFREE | 377 SYSC_OMAP2_SOFTRESET)>; 378 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 379 <SYSC_IDLE_NO>, 380 <SYSC_IDLE_SMART>, 381 <SYSC_IDLE_SMART_WKUP>; 382 ti,syss-mask = <1>; 383 /* Domains (P, C): wkup_pwrdm, l4_wkup_clkdm */ 384 clocks = <&l4_wkup_clkctrl AM3_L4_WKUP_WD_TIMER2_CLKCTRL 0>; 385 clock-names = "fck"; 386 #address-cells = <1>; 387 #size-cells = <1>; 388 ranges = <0x0 0x35000 0x1000>; 389 390 wdt2: wdt@0 { 391 compatible = "ti,omap3-wdt"; 392 reg = <0x0 0x1000>; 393 interrupts = <91>; 394 }; 395 }; 396 397 target-module@37000 { /* 0x44e37000, ap 31 08.0 */ 398 compatible = "ti,sysc"; 399 status = "disabled"; 400 #address-cells = <1>; 401 #size-cells = <1>; 402 ranges = <0x0 0x37000 0x1000>; 403 }; 404 405 target-module@39000 { /* 0x44e39000, ap 33 02.0 */ 406 compatible = "ti,sysc"; 407 status = "disabled"; 408 #address-cells = <1>; 409 #size-cells = <1>; 410 ranges = <0x0 0x39000 0x1000>; 411 }; 412 413 target-module@3e000 { /* 0x44e3e000, ap 35 60.0 */ 414 compatible = "ti,sysc-omap4-simple", "ti,sysc"; 415 ti,hwmods = "rtc"; 416 reg = <0x3e074 0x4>, 417 <0x3e078 0x4>; 418 reg-names = "rev", "sysc"; 419 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 420 <SYSC_IDLE_NO>, 421 <SYSC_IDLE_SMART>, 422 <SYSC_IDLE_SMART_WKUP>; 423 /* Domains (P, C): rtc_pwrdm, l4_rtc_clkdm */ 424 clocks = <&l4_rtc_clkctrl AM3_L4_RTC_RTC_CLKCTRL 0>; 425 clock-names = "fck"; 426 #address-cells = <1>; 427 #size-cells = <1>; 428 ranges = <0x0 0x3e000 0x1000>; 429 430 rtc: rtc@0 { 431 compatible = "ti,am3352-rtc", "ti,da830-rtc"; 432 reg = <0x0 0x1000>; 433 interrupts = <75 434 76>; 435 }; 436 }; 437 438 target-module@40000 { /* 0x44e40000, ap 38 68.0 */ 439 compatible = "ti,sysc"; 440 status = "disabled"; 441 #address-cells = <1>; 442 #size-cells = <1>; 443 ranges = <0x0 0x40000 0x40000>; 444 }; 445 }; 446}; 447 448&l4_fw { /* 0x47c00000 */ 449 compatible = "ti,am33xx-l4-fw", "simple-bus"; 450 reg = <0x47c00000 0x800>, 451 <0x47c00800 0x800>, 452 <0x47c01000 0x400>; 453 reg-names = "ap", "la", "ia0"; 454 #address-cells = <1>; 455 #size-cells = <1>; 456 ranges = <0x00000000 0x47c00000 0x1000000>; /* segment 0 */ 457 458 segment@0 { /* 0x47c00000 */ 459 compatible = "simple-bus"; 460 #address-cells = <1>; 461 #size-cells = <1>; 462 ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */ 463 <0x00000800 0x00000800 0x000800>, /* ap 1 */ 464 <0x00001000 0x00001000 0x000400>, /* ap 2 */ 465 <0x0000c000 0x0000c000 0x001000>, /* ap 3 */ 466 <0x0000d000 0x0000d000 0x001000>, /* ap 4 */ 467 <0x0000e000 0x0000e000 0x001000>, /* ap 5 */ 468 <0x0000f000 0x0000f000 0x001000>, /* ap 6 */ 469 <0x00010000 0x00010000 0x001000>, /* ap 7 */ 470 <0x00011000 0x00011000 0x001000>, /* ap 8 */ 471 <0x0001a000 0x0001a000 0x001000>, /* ap 9 */ 472 <0x0001b000 0x0001b000 0x001000>, /* ap 10 */ 473 <0x00024000 0x00024000 0x001000>, /* ap 11 */ 474 <0x00025000 0x00025000 0x001000>, /* ap 12 */ 475 <0x00026000 0x00026000 0x001000>, /* ap 13 */ 476 <0x00027000 0x00027000 0x001000>, /* ap 14 */ 477 <0x00030000 0x00030000 0x001000>, /* ap 15 */ 478 <0x00031000 0x00031000 0x001000>, /* ap 16 */ 479 <0x00038000 0x00038000 0x001000>, /* ap 17 */ 480 <0x00039000 0x00039000 0x001000>, /* ap 18 */ 481 <0x0003a000 0x0003a000 0x001000>, /* ap 19 */ 482 <0x0003b000 0x0003b000 0x001000>, /* ap 20 */ 483 <0x0003e000 0x0003e000 0x001000>, /* ap 21 */ 484 <0x0003f000 0x0003f000 0x001000>, /* ap 22 */ 485 <0x0003c000 0x0003c000 0x001000>, /* ap 23 */ 486 <0x00040000 0x00040000 0x001000>, /* ap 24 */ 487 <0x00046000 0x00046000 0x001000>, /* ap 25 */ 488 <0x00047000 0x00047000 0x001000>, /* ap 26 */ 489 <0x00044000 0x00044000 0x001000>, /* ap 27 */ 490 <0x00045000 0x00045000 0x001000>, /* ap 28 */ 491 <0x00028000 0x00028000 0x001000>, /* ap 29 */ 492 <0x00029000 0x00029000 0x001000>, /* ap 30 */ 493 <0x00032000 0x00032000 0x001000>, /* ap 31 */ 494 <0x00033000 0x00033000 0x001000>, /* ap 32 */ 495 <0x0003d000 0x0003d000 0x001000>, /* ap 33 */ 496 <0x00041000 0x00041000 0x001000>, /* ap 34 */ 497 <0x00042000 0x00042000 0x001000>, /* ap 35 */ 498 <0x00043000 0x00043000 0x001000>, /* ap 36 */ 499 <0x00014000 0x00014000 0x001000>, /* ap 37 */ 500 <0x00015000 0x00015000 0x001000>; /* ap 38 */ 501 502 target-module@c000 { /* 0x47c0c000, ap 3 04.0 */ 503 compatible = "ti,sysc"; 504 status = "disabled"; 505 #address-cells = <1>; 506 #size-cells = <1>; 507 ranges = <0x0 0xc000 0x1000>; 508 }; 509 510 target-module@e000 { /* 0x47c0e000, ap 5 0c.0 */ 511 compatible = "ti,sysc"; 512 status = "disabled"; 513 #address-cells = <1>; 514 #size-cells = <1>; 515 ranges = <0x0 0xe000 0x1000>; 516 }; 517 518 target-module@10000 { /* 0x47c10000, ap 7 20.0 */ 519 compatible = "ti,sysc"; 520 status = "disabled"; 521 #address-cells = <1>; 522 #size-cells = <1>; 523 ranges = <0x0 0x10000 0x1000>; 524 }; 525 526 target-module@14000 { /* 0x47c14000, ap 37 3c.0 */ 527 compatible = "ti,sysc"; 528 status = "disabled"; 529 #address-cells = <1>; 530 #size-cells = <1>; 531 ranges = <0x0 0x14000 0x1000>; 532 }; 533 534 target-module@1a000 { /* 0x47c1a000, ap 9 08.0 */ 535 compatible = "ti,sysc"; 536 status = "disabled"; 537 #address-cells = <1>; 538 #size-cells = <1>; 539 ranges = <0x0 0x1a000 0x1000>; 540 }; 541 542 target-module@24000 { /* 0x47c24000, ap 11 28.0 */ 543 compatible = "ti,sysc"; 544 status = "disabled"; 545 #address-cells = <1>; 546 #size-cells = <1>; 547 ranges = <0x0 0x24000 0x1000>; 548 }; 549 550 target-module@26000 { /* 0x47c26000, ap 13 30.0 */ 551 compatible = "ti,sysc"; 552 status = "disabled"; 553 #address-cells = <1>; 554 #size-cells = <1>; 555 ranges = <0x0 0x26000 0x1000>; 556 }; 557 558 target-module@28000 { /* 0x47c28000, ap 29 40.0 */ 559 compatible = "ti,sysc"; 560 status = "disabled"; 561 #address-cells = <1>; 562 #size-cells = <1>; 563 ranges = <0x0 0x28000 0x1000>; 564 }; 565 566 target-module@30000 { /* 0x47c30000, ap 15 14.0 */ 567 compatible = "ti,sysc"; 568 status = "disabled"; 569 #address-cells = <1>; 570 #size-cells = <1>; 571 ranges = <0x0 0x30000 0x1000>; 572 }; 573 574 target-module@32000 { /* 0x47c32000, ap 31 06.0 */ 575 compatible = "ti,sysc"; 576 status = "disabled"; 577 #address-cells = <1>; 578 #size-cells = <1>; 579 ranges = <0x0 0x32000 0x1000>; 580 }; 581 582 target-module@38000 { /* 0x47c38000, ap 17 18.0 */ 583 compatible = "ti,sysc"; 584 status = "disabled"; 585 #address-cells = <1>; 586 #size-cells = <1>; 587 ranges = <0x0 0x38000 0x1000>; 588 }; 589 590 target-module@3a000 { /* 0x47c3a000, ap 19 1c.0 */ 591 compatible = "ti,sysc"; 592 status = "disabled"; 593 #address-cells = <1>; 594 #size-cells = <1>; 595 ranges = <0x0 0x3a000 0x1000>; 596 }; 597 598 target-module@3c000 { /* 0x47c3c000, ap 23 38.0 */ 599 compatible = "ti,sysc"; 600 status = "disabled"; 601 #address-cells = <1>; 602 #size-cells = <1>; 603 ranges = <0x0 0x3c000 0x1000>; 604 }; 605 606 target-module@3e000 { /* 0x47c3e000, ap 21 10.0 */ 607 compatible = "ti,sysc"; 608 status = "disabled"; 609 #address-cells = <1>; 610 #size-cells = <1>; 611 ranges = <0x0 0x3e000 0x1000>; 612 }; 613 614 target-module@40000 { /* 0x47c40000, ap 24 02.0 */ 615 compatible = "ti,sysc"; 616 status = "disabled"; 617 #address-cells = <1>; 618 #size-cells = <1>; 619 ranges = <0x0 0x40000 0x1000>; 620 }; 621 622 target-module@42000 { /* 0x47c42000, ap 35 34.0 */ 623 compatible = "ti,sysc"; 624 status = "disabled"; 625 #address-cells = <1>; 626 #size-cells = <1>; 627 ranges = <0x0 0x42000 0x1000>; 628 }; 629 630 target-module@44000 { /* 0x47c44000, ap 27 24.0 */ 631 compatible = "ti,sysc"; 632 status = "disabled"; 633 #address-cells = <1>; 634 #size-cells = <1>; 635 ranges = <0x0 0x44000 0x1000>; 636 }; 637 638 target-module@46000 { /* 0x47c46000, ap 25 2c.0 */ 639 compatible = "ti,sysc"; 640 status = "disabled"; 641 #address-cells = <1>; 642 #size-cells = <1>; 643 ranges = <0x0 0x46000 0x1000>; 644 }; 645 }; 646}; 647 648&l4_fast { /* 0x4a000000 */ 649 compatible = "ti,am33xx-l4-fast", "simple-bus"; 650 reg = <0x4a000000 0x800>, 651 <0x4a000800 0x800>, 652 <0x4a001000 0x400>; 653 reg-names = "ap", "la", "ia0"; 654 #address-cells = <1>; 655 #size-cells = <1>; 656 ranges = <0x00000000 0x4a000000 0x1000000>; /* segment 0 */ 657 658 segment@0 { /* 0x4a000000 */ 659 compatible = "simple-bus"; 660 #address-cells = <1>; 661 #size-cells = <1>; 662 ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */ 663 <0x00000800 0x00000800 0x000800>, /* ap 1 */ 664 <0x00001000 0x00001000 0x000400>, /* ap 2 */ 665 <0x00100000 0x00100000 0x008000>, /* ap 3 */ 666 <0x00108000 0x00108000 0x001000>, /* ap 4 */ 667 <0x00180000 0x00180000 0x020000>, /* ap 5 */ 668 <0x001a0000 0x001a0000 0x001000>, /* ap 6 */ 669 <0x00200000 0x00200000 0x080000>, /* ap 7 */ 670 <0x00280000 0x00280000 0x001000>, /* ap 8 */ 671 <0x00300000 0x00300000 0x080000>, /* ap 9 */ 672 <0x00380000 0x00380000 0x001000>; /* ap 10 */ 673 674 target-module@100000 { /* 0x4a100000, ap 3 08.0 */ 675 compatible = "ti,sysc-omap4-simple", "ti,sysc"; 676 reg = <0x101200 0x4>, 677 <0x101208 0x4>, 678 <0x101204 0x4>; 679 reg-names = "rev", "sysc", "syss"; 680 ti,sysc-mask = <0>; 681 ti,sysc-midle = <SYSC_IDLE_FORCE>, 682 <SYSC_IDLE_NO>; 683 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 684 <SYSC_IDLE_NO>; 685 ti,syss-mask = <1>; 686 clocks = <&cpsw_125mhz_clkctrl AM3_CPSW_125MHZ_CPGMAC0_CLKCTRL 0>; 687 clock-names = "fck"; 688 #address-cells = <1>; 689 #size-cells = <1>; 690 ranges = <0x0 0x100000 0x8000>; 691 692 mac: ethernet@0 { 693 compatible = "ti,am335x-cpsw","ti,cpsw"; 694 clocks = <&cpsw_125mhz_gclk>, <&cpsw_cpts_rft_clk>; 695 clock-names = "fck", "cpts"; 696 cpdma_channels = <8>; 697 ale_entries = <1024>; 698 bd_ram_size = <0x2000>; 699 mac_control = <0x20>; 700 slaves = <2>; 701 active_slave = <0>; 702 cpts_clock_mult = <0x80000000>; 703 cpts_clock_shift = <29>; 704 reg = <0x0 0x800 705 0x1200 0x100>; 706 #address-cells = <1>; 707 #size-cells = <1>; 708 /* 709 * c0_rx_thresh_pend 710 * c0_rx_pend 711 * c0_tx_pend 712 * c0_misc_pend 713 */ 714 interrupts = <40 41 42 43>; 715 ranges = <0 0 0x8000>; 716 syscon = <&scm_conf>; 717 status = "disabled"; 718 719 davinci_mdio: mdio@1000 { 720 compatible = "ti,cpsw-mdio","ti,davinci_mdio"; 721 clocks = <&cpsw_125mhz_clkctrl AM3_CPSW_125MHZ_CPGMAC0_CLKCTRL 0>; 722 clock-names = "fck"; 723 #address-cells = <1>; 724 #size-cells = <0>; 725 bus_freq = <1000000>; 726 reg = <0x1000 0x100>; 727 status = "disabled"; 728 }; 729 730 cpsw_emac0: slave@200 { 731 /* Filled in by U-Boot */ 732 mac-address = [ 00 00 00 00 00 00 ]; 733 phys = <&phy_gmii_sel 1 1>; 734 }; 735 736 cpsw_emac1: slave@300 { 737 /* Filled in by U-Boot */ 738 mac-address = [ 00 00 00 00 00 00 ]; 739 phys = <&phy_gmii_sel 2 1>; 740 }; 741 }; 742 }; 743 744 target-module@180000 { /* 0x4a180000, ap 5 10.0 */ 745 compatible = "ti,sysc"; 746 status = "disabled"; 747 #address-cells = <1>; 748 #size-cells = <1>; 749 ranges = <0x0 0x180000 0x20000>; 750 }; 751 752 target-module@200000 { /* 0x4a200000, ap 7 02.0 */ 753 compatible = "ti,sysc"; 754 status = "disabled"; 755 #address-cells = <1>; 756 #size-cells = <1>; 757 ranges = <0x0 0x200000 0x80000>; 758 }; 759 760 target-module@300000 { /* 0x4a300000, ap 9 04.0 */ 761 compatible = "ti,sysc"; 762 status = "disabled"; 763 #address-cells = <1>; 764 #size-cells = <1>; 765 ranges = <0x0 0x300000 0x80000>; 766 }; 767 }; 768}; 769 770&l4_mpuss { /* 0x4b140000 */ 771 compatible = "ti,am33xx-l4-mpuss", "simple-bus"; 772 reg = <0x4b144400 0x100>, 773 <0x4b144800 0x400>; 774 reg-names = "la", "ap"; 775 #address-cells = <1>; 776 #size-cells = <1>; 777 ranges = <0x00000000 0x4b140000 0x008000>; /* segment 0 */ 778 779 segment@0 { /* 0x4b140000 */ 780 compatible = "simple-bus"; 781 #address-cells = <1>; 782 #size-cells = <1>; 783 ranges = <0x00004800 0x00004800 0x000400>, /* ap 0 */ 784 <0x00001000 0x00001000 0x001000>, /* ap 1 */ 785 <0x00002000 0x00002000 0x001000>, /* ap 2 */ 786 <0x00004000 0x00004000 0x000400>, /* ap 3 */ 787 <0x00005000 0x00005000 0x000400>, /* ap 4 */ 788 <0x00000000 0x00000000 0x001000>, /* ap 5 */ 789 <0x00003000 0x00003000 0x001000>, /* ap 6 */ 790 <0x00000800 0x00000800 0x000800>; /* ap 7 */ 791 792 target-module@0 { /* 0x4b140000, ap 5 02.2 */ 793 compatible = "ti,sysc"; 794 status = "disabled"; 795 #address-cells = <1>; 796 #size-cells = <1>; 797 ranges = <0x00000000 0x00000000 0x00001000>, 798 <0x00001000 0x00001000 0x00001000>, 799 <0x00002000 0x00002000 0x00001000>; 800 }; 801 802 target-module@3000 { /* 0x4b143000, ap 6 04.0 */ 803 compatible = "ti,sysc"; 804 status = "disabled"; 805 #address-cells = <1>; 806 #size-cells = <1>; 807 ranges = <0x0 0x3000 0x1000>; 808 }; 809 }; 810}; 811 812&l4_per { /* 0x48000000 */ 813 compatible = "ti,am33xx-l4-per", "simple-bus"; 814 reg = <0x48000000 0x800>, 815 <0x48000800 0x800>, 816 <0x48001000 0x400>, 817 <0x48001400 0x400>, 818 <0x48001800 0x400>, 819 <0x48001c00 0x400>; 820 reg-names = "ap", "la", "ia0", "ia1", "ia2", "ia3"; 821 #address-cells = <1>; 822 #size-cells = <1>; 823 ranges = <0x00000000 0x48000000 0x100000>, /* segment 0 */ 824 <0x00100000 0x48100000 0x100000>, /* segment 1 */ 825 <0x00200000 0x48200000 0x100000>, /* segment 2 */ 826 <0x00300000 0x48300000 0x100000>, /* segment 3 */ 827 <0x46000000 0x46000000 0x400000>, /* l3 data port */ 828 <0x46400000 0x46400000 0x400000>; /* l3 data port */ 829 830 segment@0 { /* 0x48000000 */ 831 compatible = "simple-bus"; 832 #address-cells = <1>; 833 #size-cells = <1>; 834 ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */ 835 <0x00000800 0x00000800 0x000800>, /* ap 1 */ 836 <0x00001000 0x00001000 0x000400>, /* ap 2 */ 837 <0x00001400 0x00001400 0x000400>, /* ap 3 */ 838 <0x00001800 0x00001800 0x000400>, /* ap 4 */ 839 <0x00001c00 0x00001c00 0x000400>, /* ap 5 */ 840 <0x00008000 0x00008000 0x001000>, /* ap 6 */ 841 <0x00009000 0x00009000 0x001000>, /* ap 7 */ 842 <0x00016000 0x00016000 0x001000>, /* ap 8 */ 843 <0x00017000 0x00017000 0x001000>, /* ap 9 */ 844 <0x00022000 0x00022000 0x001000>, /* ap 10 */ 845 <0x00023000 0x00023000 0x001000>, /* ap 11 */ 846 <0x00024000 0x00024000 0x001000>, /* ap 12 */ 847 <0x00025000 0x00025000 0x001000>, /* ap 13 */ 848 <0x0002a000 0x0002a000 0x001000>, /* ap 14 */ 849 <0x0002b000 0x0002b000 0x001000>, /* ap 15 */ 850 <0x00038000 0x00038000 0x002000>, /* ap 16 */ 851 <0x0003a000 0x0003a000 0x001000>, /* ap 17 */ 852 <0x00014000 0x00014000 0x001000>, /* ap 18 */ 853 <0x00015000 0x00015000 0x001000>, /* ap 19 */ 854 <0x0003c000 0x0003c000 0x002000>, /* ap 20 */ 855 <0x0003e000 0x0003e000 0x001000>, /* ap 21 */ 856 <0x00040000 0x00040000 0x001000>, /* ap 22 */ 857 <0x00041000 0x00041000 0x001000>, /* ap 23 */ 858 <0x00042000 0x00042000 0x001000>, /* ap 24 */ 859 <0x00043000 0x00043000 0x001000>, /* ap 25 */ 860 <0x00044000 0x00044000 0x001000>, /* ap 26 */ 861 <0x00045000 0x00045000 0x001000>, /* ap 27 */ 862 <0x00046000 0x00046000 0x001000>, /* ap 28 */ 863 <0x00047000 0x00047000 0x001000>, /* ap 29 */ 864 <0x00048000 0x00048000 0x001000>, /* ap 30 */ 865 <0x00049000 0x00049000 0x001000>, /* ap 31 */ 866 <0x0004c000 0x0004c000 0x001000>, /* ap 32 */ 867 <0x0004d000 0x0004d000 0x001000>, /* ap 33 */ 868 <0x00050000 0x00050000 0x002000>, /* ap 34 */ 869 <0x00052000 0x00052000 0x001000>, /* ap 35 */ 870 <0x00060000 0x00060000 0x001000>, /* ap 36 */ 871 <0x00061000 0x00061000 0x001000>, /* ap 37 */ 872 <0x00080000 0x00080000 0x010000>, /* ap 38 */ 873 <0x00090000 0x00090000 0x001000>, /* ap 39 */ 874 <0x000a0000 0x000a0000 0x010000>, /* ap 40 */ 875 <0x000b0000 0x000b0000 0x001000>, /* ap 41 */ 876 <0x00030000 0x00030000 0x001000>, /* ap 77 */ 877 <0x00031000 0x00031000 0x001000>, /* ap 78 */ 878 <0x0004a000 0x0004a000 0x001000>, /* ap 85 */ 879 <0x0004b000 0x0004b000 0x001000>, /* ap 86 */ 880 <0x000c8000 0x000c8000 0x001000>, /* ap 87 */ 881 <0x000c9000 0x000c9000 0x001000>, /* ap 88 */ 882 <0x000cc000 0x000cc000 0x001000>, /* ap 89 */ 883 <0x000cd000 0x000cd000 0x001000>, /* ap 90 */ 884 <0x000ca000 0x000ca000 0x001000>, /* ap 91 */ 885 <0x000cb000 0x000cb000 0x001000>, /* ap 92 */ 886 <0x46000000 0x46000000 0x400000>, /* l3 data port */ 887 <0x46400000 0x46400000 0x400000>; /* l3 data port */ 888 889 target-module@8000 { /* 0x48008000, ap 6 10.0 */ 890 compatible = "ti,sysc"; 891 status = "disabled"; 892 #address-cells = <1>; 893 #size-cells = <1>; 894 ranges = <0x0 0x8000 0x1000>; 895 }; 896 897 target-module@14000 { /* 0x48014000, ap 18 58.0 */ 898 compatible = "ti,sysc"; 899 status = "disabled"; 900 #address-cells = <1>; 901 #size-cells = <1>; 902 ranges = <0x0 0x14000 0x1000>; 903 }; 904 905 target-module@16000 { /* 0x48016000, ap 8 3c.0 */ 906 compatible = "ti,sysc"; 907 status = "disabled"; 908 #address-cells = <1>; 909 #size-cells = <1>; 910 ranges = <0x0 0x16000 0x1000>; 911 }; 912 913 target-module@22000 { /* 0x48022000, ap 10 12.0 */ 914 compatible = "ti,sysc-omap2", "ti,sysc"; 915 ti,hwmods = "uart2"; 916 reg = <0x22050 0x4>, 917 <0x22054 0x4>, 918 <0x22058 0x4>; 919 reg-names = "rev", "sysc", "syss"; 920 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | 921 SYSC_OMAP2_SOFTRESET | 922 SYSC_OMAP2_AUTOIDLE)>; 923 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 924 <SYSC_IDLE_NO>, 925 <SYSC_IDLE_SMART>, 926 <SYSC_IDLE_SMART_WKUP>; 927 /* Domains (P, C): per_pwrdm, l4ls_clkdm */ 928 clocks = <&l4ls_clkctrl AM3_L4LS_UART2_CLKCTRL 0>; 929 clock-names = "fck"; 930 #address-cells = <1>; 931 #size-cells = <1>; 932 ranges = <0x0 0x22000 0x1000>; 933 934 uart1: serial@0 { 935 compatible = "ti,am3352-uart", "ti,omap3-uart"; 936 clock-frequency = <48000000>; 937 reg = <0x0 0x1000>; 938 interrupts = <73>; 939 status = "disabled"; 940 dmas = <&edma 28 0>, <&edma 29 0>; 941 dma-names = "tx", "rx"; 942 }; 943 }; 944 945 target-module@24000 { /* 0x48024000, ap 12 14.0 */ 946 compatible = "ti,sysc-omap2", "ti,sysc"; 947 ti,hwmods = "uart3"; 948 reg = <0x24050 0x4>, 949 <0x24054 0x4>, 950 <0x24058 0x4>; 951 reg-names = "rev", "sysc", "syss"; 952 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | 953 SYSC_OMAP2_SOFTRESET | 954 SYSC_OMAP2_AUTOIDLE)>; 955 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 956 <SYSC_IDLE_NO>, 957 <SYSC_IDLE_SMART>, 958 <SYSC_IDLE_SMART_WKUP>; 959 /* Domains (P, C): per_pwrdm, l4ls_clkdm */ 960 clocks = <&l4ls_clkctrl AM3_L4LS_UART3_CLKCTRL 0>; 961 clock-names = "fck"; 962 #address-cells = <1>; 963 #size-cells = <1>; 964 ranges = <0x0 0x24000 0x1000>; 965 966 uart2: serial@0 { 967 compatible = "ti,am3352-uart", "ti,omap3-uart"; 968 clock-frequency = <48000000>; 969 reg = <0x0 0x1000>; 970 interrupts = <74>; 971 status = "disabled"; 972 dmas = <&edma 30 0>, <&edma 31 0>; 973 dma-names = "tx", "rx"; 974 }; 975 }; 976 977 target-module@2a000 { /* 0x4802a000, ap 14 2a.0 */ 978 compatible = "ti,sysc-omap2", "ti,sysc"; 979 ti,hwmods = "i2c2"; 980 reg = <0x2a000 0x8>, 981 <0x2a010 0x8>, 982 <0x2a090 0x8>; 983 reg-names = "rev", "sysc", "syss"; 984 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | 985 SYSC_OMAP2_ENAWAKEUP | 986 SYSC_OMAP2_SOFTRESET | 987 SYSC_OMAP2_AUTOIDLE)>; 988 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 989 <SYSC_IDLE_NO>, 990 <SYSC_IDLE_SMART>, 991 <SYSC_IDLE_SMART_WKUP>; 992 ti,syss-mask = <1>; 993 /* Domains (P, C): per_pwrdm, l4ls_clkdm */ 994 clocks = <&l4ls_clkctrl AM3_L4LS_I2C2_CLKCTRL 0>; 995 clock-names = "fck"; 996 #address-cells = <1>; 997 #size-cells = <1>; 998 ranges = <0x0 0x2a000 0x1000>; 999 1000 i2c1: i2c@0 { 1001 compatible = "ti,omap4-i2c"; 1002 #address-cells = <1>; 1003 #size-cells = <0>; 1004 reg = <0x0 0x1000>; 1005 interrupts = <71>; 1006 status = "disabled"; 1007 }; 1008 }; 1009 1010 target-module@30000 { /* 0x48030000, ap 77 08.0 */ 1011 compatible = "ti,sysc-omap2", "ti,sysc"; 1012 ti,hwmods = "spi0"; 1013 reg = <0x30000 0x4>, 1014 <0x30110 0x4>, 1015 <0x30114 0x4>; 1016 reg-names = "rev", "sysc", "syss"; 1017 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | 1018 SYSC_OMAP2_SOFTRESET | 1019 SYSC_OMAP2_AUTOIDLE)>; 1020 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1021 <SYSC_IDLE_NO>, 1022 <SYSC_IDLE_SMART>; 1023 ti,syss-mask = <1>; 1024 /* Domains (P, C): per_pwrdm, l4ls_clkdm */ 1025 clocks = <&l4ls_clkctrl AM3_L4LS_SPI0_CLKCTRL 0>; 1026 clock-names = "fck"; 1027 #address-cells = <1>; 1028 #size-cells = <1>; 1029 ranges = <0x0 0x30000 0x1000>; 1030 1031 spi0: spi@0 { 1032 compatible = "ti,omap4-mcspi"; 1033 #address-cells = <1>; 1034 #size-cells = <0>; 1035 reg = <0x0 0x400>; 1036 interrupts = <65>; 1037 ti,spi-num-cs = <2>; 1038 dmas = <&edma 16 0 1039 &edma 17 0 1040 &edma 18 0 1041 &edma 19 0>; 1042 dma-names = "tx0", "rx0", "tx1", "rx1"; 1043 status = "disabled"; 1044 }; 1045 }; 1046 1047 target-module@38000 { /* 0x48038000, ap 16 02.0 */ 1048 compatible = "ti,sysc-omap4-simple", "ti,sysc"; 1049 ti,hwmods = "mcasp0"; 1050 reg = <0x38000 0x4>, 1051 <0x38004 0x4>; 1052 reg-names = "rev", "sysc"; 1053 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1054 <SYSC_IDLE_NO>, 1055 <SYSC_IDLE_SMART>; 1056 /* Domains (P, C): per_pwrdm, l3s_clkdm */ 1057 clocks = <&l3s_clkctrl AM3_L3S_MCASP0_CLKCTRL 0>; 1058 clock-names = "fck"; 1059 #address-cells = <1>; 1060 #size-cells = <1>; 1061 ranges = <0x0 0x38000 0x2000>, 1062 <0x46000000 0x46000000 0x400000>; 1063 1064 mcasp0: mcasp@0 { 1065 compatible = "ti,am33xx-mcasp-audio"; 1066 reg = <0x0 0x2000>, 1067 <0x46000000 0x400000>; 1068 reg-names = "mpu", "dat"; 1069 interrupts = <80>, <81>; 1070 interrupt-names = "tx", "rx"; 1071 status = "disabled"; 1072 dmas = <&edma 8 2>, 1073 <&edma 9 2>; 1074 dma-names = "tx", "rx"; 1075 }; 1076 }; 1077 1078 target-module@3c000 { /* 0x4803c000, ap 20 32.0 */ 1079 compatible = "ti,sysc-omap4-simple", "ti,sysc"; 1080 ti,hwmods = "mcasp1"; 1081 reg = <0x3c000 0x4>, 1082 <0x3c004 0x4>; 1083 reg-names = "rev", "sysc"; 1084 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1085 <SYSC_IDLE_NO>, 1086 <SYSC_IDLE_SMART>; 1087 /* Domains (P, C): per_pwrdm, l3s_clkdm */ 1088 clocks = <&l3s_clkctrl AM3_L3S_MCASP1_CLKCTRL 0>; 1089 clock-names = "fck"; 1090 #address-cells = <1>; 1091 #size-cells = <1>; 1092 ranges = <0x0 0x3c000 0x2000>, 1093 <0x46400000 0x46400000 0x400000>; 1094 1095 mcasp1: mcasp@0 { 1096 compatible = "ti,am33xx-mcasp-audio"; 1097 reg = <0x0 0x2000>, 1098 <0x46400000 0x400000>; 1099 reg-names = "mpu", "dat"; 1100 interrupts = <82>, <83>; 1101 interrupt-names = "tx", "rx"; 1102 status = "disabled"; 1103 dmas = <&edma 10 2>, 1104 <&edma 11 2>; 1105 dma-names = "tx", "rx"; 1106 }; 1107 }; 1108 1109 target-module@40000 { /* 0x48040000, ap 22 1e.0 */ 1110 compatible = "ti,sysc-omap4-timer", "ti,sysc"; 1111 ti,hwmods = "timer2"; 1112 reg = <0x40000 0x4>, 1113 <0x40010 0x4>, 1114 <0x40014 0x4>; 1115 reg-names = "rev", "sysc", "syss"; 1116 ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>; 1117 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1118 <SYSC_IDLE_NO>, 1119 <SYSC_IDLE_SMART>, 1120 <SYSC_IDLE_SMART_WKUP>; 1121 /* Domains (P, C): per_pwrdm, l4ls_clkdm */ 1122 clocks = <&l4ls_clkctrl AM3_L4LS_TIMER2_CLKCTRL 0>; 1123 clock-names = "fck"; 1124 #address-cells = <1>; 1125 #size-cells = <1>; 1126 ranges = <0x0 0x40000 0x1000>; 1127 1128 timer2: timer@0 { 1129 compatible = "ti,am335x-timer"; 1130 reg = <0x0 0x400>; 1131 interrupts = <68>; 1132 clocks = <&timer2_fck>; 1133 clock-names = "fck"; 1134 }; 1135 }; 1136 1137 target-module@42000 { /* 0x48042000, ap 24 1c.0 */ 1138 compatible = "ti,sysc-omap4-timer", "ti,sysc"; 1139 ti,hwmods = "timer3"; 1140 reg = <0x42000 0x4>, 1141 <0x42010 0x4>, 1142 <0x42014 0x4>; 1143 reg-names = "rev", "sysc", "syss"; 1144 ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>; 1145 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1146 <SYSC_IDLE_NO>, 1147 <SYSC_IDLE_SMART>, 1148 <SYSC_IDLE_SMART_WKUP>; 1149 /* Domains (P, C): per_pwrdm, l4ls_clkdm */ 1150 clocks = <&l4ls_clkctrl AM3_L4LS_TIMER3_CLKCTRL 0>; 1151 clock-names = "fck"; 1152 #address-cells = <1>; 1153 #size-cells = <1>; 1154 ranges = <0x0 0x42000 0x1000>; 1155 1156 timer3: timer@0 { 1157 compatible = "ti,am335x-timer"; 1158 reg = <0x0 0x400>; 1159 interrupts = <69>; 1160 }; 1161 }; 1162 1163 target-module@44000 { /* 0x48044000, ap 26 26.0 */ 1164 compatible = "ti,sysc-omap4-timer", "ti,sysc"; 1165 ti,hwmods = "timer4"; 1166 reg = <0x44000 0x4>, 1167 <0x44010 0x4>, 1168 <0x44014 0x4>; 1169 reg-names = "rev", "sysc", "syss"; 1170 ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>; 1171 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1172 <SYSC_IDLE_NO>, 1173 <SYSC_IDLE_SMART>, 1174 <SYSC_IDLE_SMART_WKUP>; 1175 /* Domains (P, C): per_pwrdm, l4ls_clkdm */ 1176 clocks = <&l4ls_clkctrl AM3_L4LS_TIMER4_CLKCTRL 0>; 1177 clock-names = "fck"; 1178 #address-cells = <1>; 1179 #size-cells = <1>; 1180 ranges = <0x0 0x44000 0x1000>; 1181 1182 timer4: timer@0 { 1183 compatible = "ti,am335x-timer"; 1184 reg = <0x0 0x400>; 1185 interrupts = <92>; 1186 ti,timer-pwm; 1187 }; 1188 }; 1189 1190 target-module@46000 { /* 0x48046000, ap 28 28.0 */ 1191 compatible = "ti,sysc-omap4-timer", "ti,sysc"; 1192 ti,hwmods = "timer5"; 1193 reg = <0x46000 0x4>, 1194 <0x46010 0x4>, 1195 <0x46014 0x4>; 1196 reg-names = "rev", "sysc", "syss"; 1197 ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>; 1198 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1199 <SYSC_IDLE_NO>, 1200 <SYSC_IDLE_SMART>, 1201 <SYSC_IDLE_SMART_WKUP>; 1202 /* Domains (P, C): per_pwrdm, l4ls_clkdm */ 1203 clocks = <&l4ls_clkctrl AM3_L4LS_TIMER5_CLKCTRL 0>; 1204 clock-names = "fck"; 1205 #address-cells = <1>; 1206 #size-cells = <1>; 1207 ranges = <0x0 0x46000 0x1000>; 1208 1209 timer5: timer@0 { 1210 compatible = "ti,am335x-timer"; 1211 reg = <0x0 0x400>; 1212 interrupts = <93>; 1213 ti,timer-pwm; 1214 }; 1215 }; 1216 1217 target-module@48000 { /* 0x48048000, ap 30 22.0 */ 1218 compatible = "ti,sysc-omap4-timer", "ti,sysc"; 1219 ti,hwmods = "timer6"; 1220 reg = <0x48000 0x4>, 1221 <0x48010 0x4>, 1222 <0x48014 0x4>; 1223 reg-names = "rev", "sysc", "syss"; 1224 ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>; 1225 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1226 <SYSC_IDLE_NO>, 1227 <SYSC_IDLE_SMART>, 1228 <SYSC_IDLE_SMART_WKUP>; 1229 /* Domains (P, C): per_pwrdm, l4ls_clkdm */ 1230 clocks = <&l4ls_clkctrl AM3_L4LS_TIMER6_CLKCTRL 0>; 1231 clock-names = "fck"; 1232 #address-cells = <1>; 1233 #size-cells = <1>; 1234 ranges = <0x0 0x48000 0x1000>; 1235 1236 timer6: timer@0 { 1237 compatible = "ti,am335x-timer"; 1238 reg = <0x0 0x400>; 1239 interrupts = <94>; 1240 ti,timer-pwm; 1241 }; 1242 }; 1243 1244 target-module@4a000 { /* 0x4804a000, ap 85 60.0 */ 1245 compatible = "ti,sysc-omap4-timer", "ti,sysc"; 1246 ti,hwmods = "timer7"; 1247 reg = <0x4a000 0x4>, 1248 <0x4a010 0x4>, 1249 <0x4a014 0x4>; 1250 reg-names = "rev", "sysc", "syss"; 1251 ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>; 1252 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1253 <SYSC_IDLE_NO>, 1254 <SYSC_IDLE_SMART>, 1255 <SYSC_IDLE_SMART_WKUP>; 1256 /* Domains (P, C): per_pwrdm, l4ls_clkdm */ 1257 clocks = <&l4ls_clkctrl AM3_L4LS_TIMER7_CLKCTRL 0>; 1258 clock-names = "fck"; 1259 #address-cells = <1>; 1260 #size-cells = <1>; 1261 ranges = <0x0 0x4a000 0x1000>; 1262 1263 timer7: timer@0 { 1264 compatible = "ti,am335x-timer"; 1265 reg = <0x0 0x400>; 1266 interrupts = <95>; 1267 ti,timer-pwm; 1268 }; 1269 }; 1270 1271 target-module@4c000 { /* 0x4804c000, ap 32 36.0 */ 1272 compatible = "ti,sysc-omap2", "ti,sysc"; 1273 ti,hwmods = "gpio2"; 1274 reg = <0x4c000 0x4>, 1275 <0x4c010 0x4>, 1276 <0x4c114 0x4>; 1277 reg-names = "rev", "sysc", "syss"; 1278 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | 1279 SYSC_OMAP2_SOFTRESET | 1280 SYSC_OMAP2_AUTOIDLE)>; 1281 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1282 <SYSC_IDLE_NO>, 1283 <SYSC_IDLE_SMART>, 1284 <SYSC_IDLE_SMART_WKUP>; 1285 ti,syss-mask = <1>; 1286 /* Domains (P, C): per_pwrdm, l4ls_clkdm */ 1287 clocks = <&l4ls_clkctrl AM3_L4LS_GPIO2_CLKCTRL 0>, 1288 <&l4ls_clkctrl AM3_L4LS_GPIO2_CLKCTRL 18>; 1289 clock-names = "fck", "dbclk"; 1290 #address-cells = <1>; 1291 #size-cells = <1>; 1292 ranges = <0x0 0x4c000 0x1000>; 1293 1294 gpio1: gpio@0 { 1295 compatible = "ti,omap4-gpio"; 1296 gpio-controller; 1297 #gpio-cells = <2>; 1298 interrupt-controller; 1299 #interrupt-cells = <2>; 1300 reg = <0x0 0x1000>; 1301 interrupts = <98>; 1302 }; 1303 }; 1304 1305 target-module@50000 { /* 0x48050000, ap 34 2c.0 */ 1306 compatible = "ti,sysc"; 1307 status = "disabled"; 1308 #address-cells = <1>; 1309 #size-cells = <1>; 1310 ranges = <0x0 0x50000 0x2000>; 1311 }; 1312 1313 target-module@60000 { /* 0x48060000, ap 36 0c.0 */ 1314 compatible = "ti,sysc-omap2", "ti,sysc"; 1315 ti,hwmods = "mmc1"; 1316 reg = <0x602fc 0x4>, 1317 <0x60110 0x4>, 1318 <0x60114 0x4>; 1319 reg-names = "rev", "sysc", "syss"; 1320 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | 1321 SYSC_OMAP2_ENAWAKEUP | 1322 SYSC_OMAP2_SOFTRESET | 1323 SYSC_OMAP2_AUTOIDLE)>; 1324 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1325 <SYSC_IDLE_NO>, 1326 <SYSC_IDLE_SMART>; 1327 ti,syss-mask = <1>; 1328 /* Domains (P, C): per_pwrdm, l4ls_clkdm */ 1329 clocks = <&l4ls_clkctrl AM3_L4LS_MMC1_CLKCTRL 0>; 1330 clock-names = "fck"; 1331 #address-cells = <1>; 1332 #size-cells = <1>; 1333 ranges = <0x0 0x60000 0x1000>; 1334 1335 mmc1: mmc@0 { 1336 compatible = "ti,omap4-hsmmc"; 1337 ti,dual-volt; 1338 ti,needs-special-reset; 1339 ti,needs-special-hs-handling; 1340 dmas = <&edma_xbar 24 0 0 1341 &edma_xbar 25 0 0>; 1342 dma-names = "tx", "rx"; 1343 interrupts = <64>; 1344 reg = <0x0 0x1000>; 1345 status = "disabled"; 1346 }; 1347 }; 1348 1349 target-module@80000 { /* 0x48080000, ap 38 18.0 */ 1350 compatible = "ti,sysc-omap2", "ti,sysc"; 1351 ti,hwmods = "elm"; 1352 reg = <0x80000 0x4>, 1353 <0x80010 0x4>, 1354 <0x80014 0x4>; 1355 reg-names = "rev", "sysc", "syss"; 1356 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | 1357 SYSC_OMAP2_SOFTRESET | 1358 SYSC_OMAP2_AUTOIDLE)>; 1359 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1360 <SYSC_IDLE_NO>, 1361 <SYSC_IDLE_SMART>; 1362 ti,syss-mask = <1>; 1363 /* Domains (P, C): per_pwrdm, l4ls_clkdm */ 1364 clocks = <&l4ls_clkctrl AM3_L4LS_ELM_CLKCTRL 0>; 1365 clock-names = "fck"; 1366 #address-cells = <1>; 1367 #size-cells = <1>; 1368 ranges = <0x0 0x80000 0x10000>; 1369 1370 elm: elm@0 { 1371 compatible = "ti,am3352-elm"; 1372 reg = <0x0 0x2000>; 1373 interrupts = <4>; 1374 status = "disabled"; 1375 }; 1376 }; 1377 1378 target-module@a0000 { /* 0x480a0000, ap 40 5e.0 */ 1379 compatible = "ti,sysc"; 1380 status = "disabled"; 1381 #address-cells = <1>; 1382 #size-cells = <1>; 1383 ranges = <0x0 0xa0000 0x10000>; 1384 }; 1385 1386 target-module@c8000 { /* 0x480c8000, ap 87 06.0 */ 1387 compatible = "ti,sysc-omap4", "ti,sysc"; 1388 ti,hwmods = "mailbox"; 1389 reg = <0xc8000 0x4>, 1390 <0xc8010 0x4>; 1391 reg-names = "rev", "sysc"; 1392 ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>; 1393 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1394 <SYSC_IDLE_NO>, 1395 <SYSC_IDLE_SMART>; 1396 /* Domains (P, C): per_pwrdm, l4ls_clkdm */ 1397 clocks = <&l4ls_clkctrl AM3_L4LS_MAILBOX_CLKCTRL 0>; 1398 clock-names = "fck"; 1399 #address-cells = <1>; 1400 #size-cells = <1>; 1401 ranges = <0x0 0xc8000 0x1000>; 1402 1403 mailbox: mailbox@0 { 1404 compatible = "ti,omap4-mailbox"; 1405 reg = <0x0 0x200>; 1406 interrupts = <77>; 1407 #mbox-cells = <1>; 1408 ti,mbox-num-users = <4>; 1409 ti,mbox-num-fifos = <8>; 1410 mbox_wkupm3: wkup_m3 { 1411 ti,mbox-send-noirq; 1412 ti,mbox-tx = <0 0 0>; 1413 ti,mbox-rx = <0 0 3>; 1414 }; 1415 }; 1416 }; 1417 1418 target-module@ca000 { /* 0x480ca000, ap 91 40.0 */ 1419 compatible = "ti,sysc-omap2", "ti,sysc"; 1420 ti,hwmods = "spinlock"; 1421 reg = <0xca000 0x4>, 1422 <0xca010 0x4>, 1423 <0xca014 0x4>; 1424 reg-names = "rev", "sysc", "syss"; 1425 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | 1426 SYSC_OMAP2_ENAWAKEUP | 1427 SYSC_OMAP2_SOFTRESET | 1428 SYSC_OMAP2_AUTOIDLE)>; 1429 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1430 <SYSC_IDLE_NO>, 1431 <SYSC_IDLE_SMART>; 1432 ti,syss-mask = <1>; 1433 /* Domains (P, C): per_pwrdm, l4ls_clkdm */ 1434 clocks = <&l4ls_clkctrl AM3_L4LS_SPINLOCK_CLKCTRL 0>; 1435 clock-names = "fck"; 1436 #address-cells = <1>; 1437 #size-cells = <1>; 1438 ranges = <0x0 0xca000 0x1000>; 1439 1440 hwspinlock: spinlock@0 { 1441 compatible = "ti,omap4-hwspinlock"; 1442 reg = <0x0 0x1000>; 1443 #hwlock-cells = <1>; 1444 }; 1445 }; 1446 1447 target-module@cc000 { /* 0x480cc000, ap 89 0e.0 */ 1448 compatible = "ti,sysc"; 1449 status = "disabled"; 1450 #address-cells = <1>; 1451 #size-cells = <1>; 1452 ranges = <0x0 0xcc000 0x1000>; 1453 }; 1454 }; 1455 1456 segment@100000 { /* 0x48100000 */ 1457 compatible = "simple-bus"; 1458 #address-cells = <1>; 1459 #size-cells = <1>; 1460 ranges = <0x0008c000 0x0018c000 0x001000>, /* ap 42 */ 1461 <0x0008d000 0x0018d000 0x001000>, /* ap 43 */ 1462 <0x0008e000 0x0018e000 0x001000>, /* ap 44 */ 1463 <0x0008f000 0x0018f000 0x001000>, /* ap 45 */ 1464 <0x0009c000 0x0019c000 0x001000>, /* ap 46 */ 1465 <0x0009d000 0x0019d000 0x001000>, /* ap 47 */ 1466 <0x000a6000 0x001a6000 0x001000>, /* ap 48 */ 1467 <0x000a7000 0x001a7000 0x001000>, /* ap 49 */ 1468 <0x000a8000 0x001a8000 0x001000>, /* ap 50 */ 1469 <0x000a9000 0x001a9000 0x001000>, /* ap 51 */ 1470 <0x000aa000 0x001aa000 0x001000>, /* ap 52 */ 1471 <0x000ab000 0x001ab000 0x001000>, /* ap 53 */ 1472 <0x000ac000 0x001ac000 0x001000>, /* ap 54 */ 1473 <0x000ad000 0x001ad000 0x001000>, /* ap 55 */ 1474 <0x000ae000 0x001ae000 0x001000>, /* ap 56 */ 1475 <0x000af000 0x001af000 0x001000>, /* ap 57 */ 1476 <0x000b0000 0x001b0000 0x010000>, /* ap 58 */ 1477 <0x000c0000 0x001c0000 0x001000>, /* ap 59 */ 1478 <0x000cc000 0x001cc000 0x002000>, /* ap 60 */ 1479 <0x000ce000 0x001ce000 0x002000>, /* ap 61 */ 1480 <0x000d0000 0x001d0000 0x002000>, /* ap 62 */ 1481 <0x000d2000 0x001d2000 0x002000>, /* ap 63 */ 1482 <0x000d8000 0x001d8000 0x001000>, /* ap 64 */ 1483 <0x000d9000 0x001d9000 0x001000>, /* ap 65 */ 1484 <0x000a0000 0x001a0000 0x001000>, /* ap 79 */ 1485 <0x000a1000 0x001a1000 0x001000>, /* ap 80 */ 1486 <0x000a2000 0x001a2000 0x001000>, /* ap 81 */ 1487 <0x000a3000 0x001a3000 0x001000>, /* ap 82 */ 1488 <0x000a4000 0x001a4000 0x001000>, /* ap 83 */ 1489 <0x000a5000 0x001a5000 0x001000>; /* ap 84 */ 1490 1491 target-module@8c000 { /* 0x4818c000, ap 42 04.0 */ 1492 compatible = "ti,sysc"; 1493 status = "disabled"; 1494 #address-cells = <1>; 1495 #size-cells = <1>; 1496 ranges = <0x0 0x8c000 0x1000>; 1497 }; 1498 1499 target-module@8e000 { /* 0x4818e000, ap 44 0a.0 */ 1500 compatible = "ti,sysc"; 1501 status = "disabled"; 1502 #address-cells = <1>; 1503 #size-cells = <1>; 1504 ranges = <0x0 0x8e000 0x1000>; 1505 }; 1506 1507 target-module@9c000 { /* 0x4819c000, ap 46 5a.0 */ 1508 compatible = "ti,sysc-omap2", "ti,sysc"; 1509 ti,hwmods = "i2c3"; 1510 reg = <0x9c000 0x8>, 1511 <0x9c010 0x8>, 1512 <0x9c090 0x8>; 1513 reg-names = "rev", "sysc", "syss"; 1514 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | 1515 SYSC_OMAP2_ENAWAKEUP | 1516 SYSC_OMAP2_SOFTRESET | 1517 SYSC_OMAP2_AUTOIDLE)>; 1518 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1519 <SYSC_IDLE_NO>, 1520 <SYSC_IDLE_SMART>, 1521 <SYSC_IDLE_SMART_WKUP>; 1522 ti,syss-mask = <1>; 1523 /* Domains (P, C): per_pwrdm, l4ls_clkdm */ 1524 clocks = <&l4ls_clkctrl AM3_L4LS_I2C3_CLKCTRL 0>; 1525 clock-names = "fck"; 1526 #address-cells = <1>; 1527 #size-cells = <1>; 1528 ranges = <0x0 0x9c000 0x1000>; 1529 1530 i2c2: i2c@0 { 1531 compatible = "ti,omap4-i2c"; 1532 #address-cells = <1>; 1533 #size-cells = <0>; 1534 reg = <0x0 0x1000>; 1535 interrupts = <30>; 1536 status = "disabled"; 1537 }; 1538 }; 1539 1540 target-module@a0000 { /* 0x481a0000, ap 79 24.0 */ 1541 compatible = "ti,sysc-omap2", "ti,sysc"; 1542 ti,hwmods = "spi1"; 1543 reg = <0xa0000 0x4>, 1544 <0xa0110 0x4>, 1545 <0xa0114 0x4>; 1546 reg-names = "rev", "sysc", "syss"; 1547 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | 1548 SYSC_OMAP2_SOFTRESET | 1549 SYSC_OMAP2_AUTOIDLE)>; 1550 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1551 <SYSC_IDLE_NO>, 1552 <SYSC_IDLE_SMART>; 1553 ti,syss-mask = <1>; 1554 /* Domains (P, C): per_pwrdm, l4ls_clkdm */ 1555 clocks = <&l4ls_clkctrl AM3_L4LS_SPI1_CLKCTRL 0>; 1556 clock-names = "fck"; 1557 #address-cells = <1>; 1558 #size-cells = <1>; 1559 ranges = <0x0 0xa0000 0x1000>; 1560 1561 spi1: spi@0 { 1562 compatible = "ti,omap4-mcspi"; 1563 #address-cells = <1>; 1564 #size-cells = <0>; 1565 reg = <0x0 0x400>; 1566 interrupts = <125>; 1567 ti,spi-num-cs = <2>; 1568 dmas = <&edma 42 0 1569 &edma 43 0 1570 &edma 44 0 1571 &edma 45 0>; 1572 dma-names = "tx0", "rx0", "tx1", "rx1"; 1573 status = "disabled"; 1574 }; 1575 }; 1576 1577 target-module@a2000 { /* 0x481a2000, ap 81 2e.0 */ 1578 compatible = "ti,sysc"; 1579 status = "disabled"; 1580 #address-cells = <1>; 1581 #size-cells = <1>; 1582 ranges = <0x0 0xa2000 0x1000>; 1583 }; 1584 1585 target-module@a4000 { /* 0x481a4000, ap 83 30.0 */ 1586 compatible = "ti,sysc"; 1587 status = "disabled"; 1588 #address-cells = <1>; 1589 #size-cells = <1>; 1590 ranges = <0x0 0xa4000 0x1000>; 1591 }; 1592 1593 target-module@a6000 { /* 0x481a6000, ap 48 16.0 */ 1594 compatible = "ti,sysc-omap2", "ti,sysc"; 1595 ti,hwmods = "uart4"; 1596 reg = <0xa6050 0x4>, 1597 <0xa6054 0x4>, 1598 <0xa6058 0x4>; 1599 reg-names = "rev", "sysc", "syss"; 1600 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | 1601 SYSC_OMAP2_SOFTRESET | 1602 SYSC_OMAP2_AUTOIDLE)>; 1603 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1604 <SYSC_IDLE_NO>, 1605 <SYSC_IDLE_SMART>, 1606 <SYSC_IDLE_SMART_WKUP>; 1607 /* Domains (P, C): per_pwrdm, l4ls_clkdm */ 1608 clocks = <&l4ls_clkctrl AM3_L4LS_UART4_CLKCTRL 0>; 1609 clock-names = "fck"; 1610 #address-cells = <1>; 1611 #size-cells = <1>; 1612 ranges = <0x0 0xa6000 0x1000>; 1613 1614 uart3: serial@0 { 1615 compatible = "ti,am3352-uart", "ti,omap3-uart"; 1616 clock-frequency = <48000000>; 1617 reg = <0x0 0x1000>; 1618 interrupts = <44>; 1619 status = "disabled"; 1620 }; 1621 }; 1622 1623 target-module@a8000 { /* 0x481a8000, ap 50 20.0 */ 1624 compatible = "ti,sysc-omap2", "ti,sysc"; 1625 ti,hwmods = "uart5"; 1626 reg = <0xa8050 0x4>, 1627 <0xa8054 0x4>, 1628 <0xa8058 0x4>; 1629 reg-names = "rev", "sysc", "syss"; 1630 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | 1631 SYSC_OMAP2_SOFTRESET | 1632 SYSC_OMAP2_AUTOIDLE)>; 1633 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1634 <SYSC_IDLE_NO>, 1635 <SYSC_IDLE_SMART>, 1636 <SYSC_IDLE_SMART_WKUP>; 1637 /* Domains (P, C): per_pwrdm, l4ls_clkdm */ 1638 clocks = <&l4ls_clkctrl AM3_L4LS_UART5_CLKCTRL 0>; 1639 clock-names = "fck"; 1640 #address-cells = <1>; 1641 #size-cells = <1>; 1642 ranges = <0x0 0xa8000 0x1000>; 1643 1644 uart4: serial@0 { 1645 compatible = "ti,am3352-uart", "ti,omap3-uart"; 1646 clock-frequency = <48000000>; 1647 reg = <0x0 0x1000>; 1648 interrupts = <45>; 1649 status = "disabled"; 1650 }; 1651 }; 1652 1653 target-module@aa000 { /* 0x481aa000, ap 52 1a.0 */ 1654 compatible = "ti,sysc-omap2", "ti,sysc"; 1655 ti,hwmods = "uart6"; 1656 reg = <0xaa050 0x4>, 1657 <0xaa054 0x4>, 1658 <0xaa058 0x4>; 1659 reg-names = "rev", "sysc", "syss"; 1660 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | 1661 SYSC_OMAP2_SOFTRESET | 1662 SYSC_OMAP2_AUTOIDLE)>; 1663 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1664 <SYSC_IDLE_NO>, 1665 <SYSC_IDLE_SMART>, 1666 <SYSC_IDLE_SMART_WKUP>; 1667 /* Domains (P, C): per_pwrdm, l4ls_clkdm */ 1668 clocks = <&l4ls_clkctrl AM3_L4LS_UART6_CLKCTRL 0>; 1669 clock-names = "fck"; 1670 #address-cells = <1>; 1671 #size-cells = <1>; 1672 ranges = <0x0 0xaa000 0x1000>; 1673 1674 uart5: serial@0 { 1675 compatible = "ti,am3352-uart", "ti,omap3-uart"; 1676 clock-frequency = <48000000>; 1677 reg = <0x0 0x1000>; 1678 interrupts = <46>; 1679 status = "disabled"; 1680 }; 1681 }; 1682 1683 target-module@ac000 { /* 0x481ac000, ap 54 38.0 */ 1684 compatible = "ti,sysc-omap2", "ti,sysc"; 1685 ti,hwmods = "gpio3"; 1686 reg = <0xac000 0x4>, 1687 <0xac010 0x4>, 1688 <0xac114 0x4>; 1689 reg-names = "rev", "sysc", "syss"; 1690 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | 1691 SYSC_OMAP2_SOFTRESET | 1692 SYSC_OMAP2_AUTOIDLE)>; 1693 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1694 <SYSC_IDLE_NO>, 1695 <SYSC_IDLE_SMART>, 1696 <SYSC_IDLE_SMART_WKUP>; 1697 ti,syss-mask = <1>; 1698 /* Domains (P, C): per_pwrdm, l4ls_clkdm */ 1699 clocks = <&l4ls_clkctrl AM3_L4LS_GPIO3_CLKCTRL 0>, 1700 <&l4ls_clkctrl AM3_L4LS_GPIO3_CLKCTRL 18>; 1701 clock-names = "fck", "dbclk"; 1702 #address-cells = <1>; 1703 #size-cells = <1>; 1704 ranges = <0x0 0xac000 0x1000>; 1705 1706 gpio2: gpio@0 { 1707 compatible = "ti,omap4-gpio"; 1708 gpio-controller; 1709 #gpio-cells = <2>; 1710 interrupt-controller; 1711 #interrupt-cells = <2>; 1712 reg = <0x0 0x1000>; 1713 interrupts = <32>; 1714 }; 1715 }; 1716 1717 target-module@ae000 { /* 0x481ae000, ap 56 3a.0 */ 1718 compatible = "ti,sysc-omap2", "ti,sysc"; 1719 ti,hwmods = "gpio4"; 1720 reg = <0xae000 0x4>, 1721 <0xae010 0x4>, 1722 <0xae114 0x4>; 1723 reg-names = "rev", "sysc", "syss"; 1724 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | 1725 SYSC_OMAP2_SOFTRESET | 1726 SYSC_OMAP2_AUTOIDLE)>; 1727 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1728 <SYSC_IDLE_NO>, 1729 <SYSC_IDLE_SMART>, 1730 <SYSC_IDLE_SMART_WKUP>; 1731 ti,syss-mask = <1>; 1732 /* Domains (P, C): per_pwrdm, l4ls_clkdm */ 1733 clocks = <&l4ls_clkctrl AM3_L4LS_GPIO4_CLKCTRL 0>, 1734 <&l4ls_clkctrl AM3_L4LS_GPIO4_CLKCTRL 18>; 1735 clock-names = "fck", "dbclk"; 1736 #address-cells = <1>; 1737 #size-cells = <1>; 1738 ranges = <0x0 0xae000 0x1000>; 1739 1740 gpio3: gpio@0 { 1741 compatible = "ti,omap4-gpio"; 1742 gpio-controller; 1743 #gpio-cells = <2>; 1744 interrupt-controller; 1745 #interrupt-cells = <2>; 1746 reg = <0x0 0x1000>; 1747 interrupts = <62>; 1748 }; 1749 }; 1750 1751 target-module@b0000 { /* 0x481b0000, ap 58 50.0 */ 1752 compatible = "ti,sysc"; 1753 status = "disabled"; 1754 #address-cells = <1>; 1755 #size-cells = <1>; 1756 ranges = <0x0 0xb0000 0x10000>; 1757 }; 1758 1759 target-module@cc000 { /* 0x481cc000, ap 60 46.0 */ 1760 compatible = "ti,sysc-omap4", "ti,sysc"; 1761 reg = <0xcc020 0x4>; 1762 reg-names = "rev"; 1763 ti,hwmods = "d_can0"; 1764 /* Domains (P, C): per_pwrdm, l4ls_clkdm */ 1765 clocks = <&l4ls_clkctrl AM3_L4LS_D_CAN0_CLKCTRL 0>, 1766 <&dcan0_fck>; 1767 clock-names = "fck", "osc"; 1768 #address-cells = <1>; 1769 #size-cells = <1>; 1770 ranges = <0x0 0xcc000 0x2000>; 1771 1772 dcan0: can@0 { 1773 compatible = "ti,am3352-d_can"; 1774 reg = <0x0 0x2000>; 1775 clocks = <&dcan0_fck>; 1776 clock-names = "fck"; 1777 syscon-raminit = <&scm_conf 0x644 0>; 1778 interrupts = <52>; 1779 status = "disabled"; 1780 }; 1781 }; 1782 1783 target-module@d0000 { /* 0x481d0000, ap 62 42.0 */ 1784 compatible = "ti,sysc-omap4", "ti,sysc"; 1785 reg = <0xd0020 0x4>; 1786 reg-names = "rev"; 1787 ti,hwmods = "d_can1"; 1788 /* Domains (P, C): per_pwrdm, l4ls_clkdm */ 1789 clocks = <&l4ls_clkctrl AM3_L4LS_D_CAN1_CLKCTRL 0>, 1790 <&dcan1_fck>; 1791 clock-names = "fck", "osc"; 1792 #address-cells = <1>; 1793 #size-cells = <1>; 1794 ranges = <0x0 0xd0000 0x2000>; 1795 1796 dcan1: can@0 { 1797 compatible = "ti,am3352-d_can"; 1798 reg = <0x0 0x2000>; 1799 clocks = <&dcan1_fck>; 1800 clock-names = "fck"; 1801 syscon-raminit = <&scm_conf 0x644 1>; 1802 interrupts = <55>; 1803 status = "disabled"; 1804 }; 1805 }; 1806 1807 target-module@d8000 { /* 0x481d8000, ap 64 66.0 */ 1808 compatible = "ti,sysc-omap2", "ti,sysc"; 1809 ti,hwmods = "mmc2"; 1810 reg = <0xd82fc 0x4>, 1811 <0xd8110 0x4>, 1812 <0xd8114 0x4>; 1813 reg-names = "rev", "sysc", "syss"; 1814 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | 1815 SYSC_OMAP2_ENAWAKEUP | 1816 SYSC_OMAP2_SOFTRESET | 1817 SYSC_OMAP2_AUTOIDLE)>; 1818 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1819 <SYSC_IDLE_NO>, 1820 <SYSC_IDLE_SMART>; 1821 ti,syss-mask = <1>; 1822 /* Domains (P, C): per_pwrdm, l4ls_clkdm */ 1823 clocks = <&l4ls_clkctrl AM3_L4LS_MMC2_CLKCTRL 0>; 1824 clock-names = "fck"; 1825 #address-cells = <1>; 1826 #size-cells = <1>; 1827 ranges = <0x0 0xd8000 0x1000>; 1828 1829 mmc2: mmc@0 { 1830 compatible = "ti,omap4-hsmmc"; 1831 ti,needs-special-reset; 1832 dmas = <&edma 2 0 1833 &edma 3 0>; 1834 dma-names = "tx", "rx"; 1835 interrupts = <28>; 1836 reg = <0x0 0x1000>; 1837 status = "disabled"; 1838 }; 1839 }; 1840 }; 1841 1842 segment@200000 { /* 0x48200000 */ 1843 compatible = "simple-bus"; 1844 #address-cells = <1>; 1845 #size-cells = <1>; 1846 }; 1847 1848 segment@300000 { /* 0x48300000 */ 1849 compatible = "simple-bus"; 1850 #address-cells = <1>; 1851 #size-cells = <1>; 1852 ranges = <0x00000000 0x00300000 0x001000>, /* ap 66 */ 1853 <0x00001000 0x00301000 0x001000>, /* ap 67 */ 1854 <0x00002000 0x00302000 0x001000>, /* ap 68 */ 1855 <0x00003000 0x00303000 0x001000>, /* ap 69 */ 1856 <0x00004000 0x00304000 0x001000>, /* ap 70 */ 1857 <0x00005000 0x00305000 0x001000>, /* ap 71 */ 1858 <0x0000e000 0x0030e000 0x001000>, /* ap 72 */ 1859 <0x0000f000 0x0030f000 0x001000>, /* ap 73 */ 1860 <0x00018000 0x00318000 0x004000>, /* ap 74 */ 1861 <0x0001c000 0x0031c000 0x001000>, /* ap 75 */ 1862 <0x00010000 0x00310000 0x002000>, /* ap 76 */ 1863 <0x00012000 0x00312000 0x001000>, /* ap 93 */ 1864 <0x00015000 0x00315000 0x001000>, /* ap 94 */ 1865 <0x00016000 0x00316000 0x001000>, /* ap 95 */ 1866 <0x00017000 0x00317000 0x001000>, /* ap 96 */ 1867 <0x00013000 0x00313000 0x001000>, /* ap 97 */ 1868 <0x00014000 0x00314000 0x001000>, /* ap 98 */ 1869 <0x00020000 0x00320000 0x001000>, /* ap 99 */ 1870 <0x00021000 0x00321000 0x001000>, /* ap 100 */ 1871 <0x00022000 0x00322000 0x001000>, /* ap 101 */ 1872 <0x00023000 0x00323000 0x001000>, /* ap 102 */ 1873 <0x00024000 0x00324000 0x001000>, /* ap 103 */ 1874 <0x00025000 0x00325000 0x001000>; /* ap 104 */ 1875 1876 target-module@0 { /* 0x48300000, ap 66 48.0 */ 1877 compatible = "ti,sysc-omap4", "ti,sysc"; 1878 ti,hwmods = "epwmss0"; 1879 reg = <0x0 0x4>, 1880 <0x4 0x4>; 1881 reg-names = "rev", "sysc"; 1882 ti,sysc-midle = <SYSC_IDLE_FORCE>, 1883 <SYSC_IDLE_NO>, 1884 <SYSC_IDLE_SMART>, 1885 <SYSC_IDLE_SMART_WKUP>; 1886 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1887 <SYSC_IDLE_NO>, 1888 <SYSC_IDLE_SMART>, 1889 <SYSC_IDLE_SMART_WKUP>; 1890 /* Domains (P, C): per_pwrdm, l4ls_clkdm */ 1891 clocks = <&l4ls_clkctrl AM3_L4LS_EPWMSS0_CLKCTRL 0>; 1892 clock-names = "fck"; 1893 #address-cells = <1>; 1894 #size-cells = <1>; 1895 ranges = <0x0 0x0 0x1000>; 1896 1897 epwmss0: epwmss@0 { 1898 compatible = "ti,am33xx-pwmss"; 1899 reg = <0x0 0x10>; 1900 #address-cells = <1>; 1901 #size-cells = <1>; 1902 status = "disabled"; 1903 ranges = <0 0 0x1000>; 1904 1905 ecap0: ecap@100 { 1906 compatible = "ti,am3352-ecap", 1907 "ti,am33xx-ecap"; 1908 #pwm-cells = <3>; 1909 reg = <0x100 0x80>; 1910 clocks = <&l4ls_gclk>; 1911 clock-names = "fck"; 1912 interrupts = <31>; 1913 interrupt-names = "ecap0"; 1914 status = "disabled"; 1915 }; 1916 1917 ehrpwm0: pwm@200 { 1918 compatible = "ti,am3352-ehrpwm", 1919 "ti,am33xx-ehrpwm"; 1920 #pwm-cells = <3>; 1921 reg = <0x200 0x80>; 1922 clocks = <&ehrpwm0_tbclk>, <&l4ls_gclk>; 1923 clock-names = "tbclk", "fck"; 1924 status = "disabled"; 1925 }; 1926 }; 1927 }; 1928 1929 target-module@2000 { /* 0x48302000, ap 68 52.0 */ 1930 compatible = "ti,sysc-omap4", "ti,sysc"; 1931 ti,hwmods = "epwmss1"; 1932 reg = <0x2000 0x4>, 1933 <0x2004 0x4>; 1934 reg-names = "rev", "sysc"; 1935 ti,sysc-midle = <SYSC_IDLE_FORCE>, 1936 <SYSC_IDLE_NO>, 1937 <SYSC_IDLE_SMART>, 1938 <SYSC_IDLE_SMART_WKUP>; 1939 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1940 <SYSC_IDLE_NO>, 1941 <SYSC_IDLE_SMART>, 1942 <SYSC_IDLE_SMART_WKUP>; 1943 /* Domains (P, C): per_pwrdm, l4ls_clkdm */ 1944 clocks = <&l4ls_clkctrl AM3_L4LS_EPWMSS1_CLKCTRL 0>; 1945 clock-names = "fck"; 1946 #address-cells = <1>; 1947 #size-cells = <1>; 1948 ranges = <0x0 0x2000 0x1000>; 1949 1950 epwmss1: epwmss@0 { 1951 compatible = "ti,am33xx-pwmss"; 1952 reg = <0x0 0x10>; 1953 #address-cells = <1>; 1954 #size-cells = <1>; 1955 status = "disabled"; 1956 ranges = <0 0 0x1000>; 1957 1958 ecap1: ecap@100 { 1959 compatible = "ti,am3352-ecap", 1960 "ti,am33xx-ecap"; 1961 #pwm-cells = <3>; 1962 reg = <0x100 0x80>; 1963 clocks = <&l4ls_gclk>; 1964 clock-names = "fck"; 1965 interrupts = <47>; 1966 interrupt-names = "ecap1"; 1967 status = "disabled"; 1968 }; 1969 1970 ehrpwm1: pwm@200 { 1971 compatible = "ti,am3352-ehrpwm", 1972 "ti,am33xx-ehrpwm"; 1973 #pwm-cells = <3>; 1974 reg = <0x200 0x80>; 1975 clocks = <&ehrpwm1_tbclk>, <&l4ls_gclk>; 1976 clock-names = "tbclk", "fck"; 1977 status = "disabled"; 1978 }; 1979 }; 1980 }; 1981 1982 target-module@4000 { /* 0x48304000, ap 70 44.0 */ 1983 compatible = "ti,sysc-omap4", "ti,sysc"; 1984 ti,hwmods = "epwmss2"; 1985 reg = <0x4000 0x4>, 1986 <0x4004 0x4>; 1987 reg-names = "rev", "sysc"; 1988 ti,sysc-midle = <SYSC_IDLE_FORCE>, 1989 <SYSC_IDLE_NO>, 1990 <SYSC_IDLE_SMART>, 1991 <SYSC_IDLE_SMART_WKUP>; 1992 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1993 <SYSC_IDLE_NO>, 1994 <SYSC_IDLE_SMART>, 1995 <SYSC_IDLE_SMART_WKUP>; 1996 /* Domains (P, C): per_pwrdm, l4ls_clkdm */ 1997 clocks = <&l4ls_clkctrl AM3_L4LS_EPWMSS2_CLKCTRL 0>; 1998 clock-names = "fck"; 1999 #address-cells = <1>; 2000 #size-cells = <1>; 2001 ranges = <0x0 0x4000 0x1000>; 2002 2003 epwmss2: epwmss@0 { 2004 compatible = "ti,am33xx-pwmss"; 2005 reg = <0x0 0x10>; 2006 #address-cells = <1>; 2007 #size-cells = <1>; 2008 status = "disabled"; 2009 ranges = <0 0 0x1000>; 2010 2011 ecap2: ecap@100 { 2012 compatible = "ti,am3352-ecap", 2013 "ti,am33xx-ecap"; 2014 #pwm-cells = <3>; 2015 reg = <0x100 0x80>; 2016 clocks = <&l4ls_gclk>; 2017 clock-names = "fck"; 2018 interrupts = <61>; 2019 interrupt-names = "ecap2"; 2020 status = "disabled"; 2021 }; 2022 2023 ehrpwm2: pwm@200 { 2024 compatible = "ti,am3352-ehrpwm", 2025 "ti,am33xx-ehrpwm"; 2026 #pwm-cells = <3>; 2027 reg = <0x200 0x80>; 2028 clocks = <&ehrpwm2_tbclk>, <&l4ls_gclk>; 2029 clock-names = "tbclk", "fck"; 2030 status = "disabled"; 2031 }; 2032 }; 2033 }; 2034 2035 target-module@e000 { /* 0x4830e000, ap 72 4a.0 */ 2036 compatible = "ti,sysc-omap4", "ti,sysc"; 2037 ti,hwmods = "lcdc"; 2038 reg = <0xe000 0x4>, 2039 <0xe054 0x4>; 2040 reg-names = "rev", "sysc"; 2041 ti,sysc-midle = <SYSC_IDLE_FORCE>, 2042 <SYSC_IDLE_NO>, 2043 <SYSC_IDLE_SMART>; 2044 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 2045 <SYSC_IDLE_NO>, 2046 <SYSC_IDLE_SMART>; 2047 /* Domains (P, C): per_pwrdm, lcdc_clkdm */ 2048 clocks = <&lcdc_clkctrl AM3_LCDC_LCDC_CLKCTRL 0>; 2049 clock-names = "fck"; 2050 #address-cells = <1>; 2051 #size-cells = <1>; 2052 ranges = <0x0 0xe000 0x1000>; 2053 2054 lcdc: lcdc@0 { 2055 compatible = "ti,am33xx-tilcdc"; 2056 reg = <0x0 0x1000>; 2057 interrupts = <36>; 2058 status = "disabled"; 2059 }; 2060 }; 2061 2062 target-module@10000 { /* 0x48310000, ap 76 4e.1 */ 2063 compatible = "ti,sysc-omap2", "ti,sysc"; 2064 ti,hwmods = "rng"; 2065 reg = <0x11fe0 0x4>, 2066 <0x11fe4 0x4>; 2067 reg-names = "rev", "sysc"; 2068 ti,sysc-mask = <SYSC_OMAP2_AUTOIDLE>; 2069 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 2070 <SYSC_IDLE_NO>; 2071 /* Domains (P, C): per_pwrdm, l4ls_clkdm */ 2072 clocks = <&l4ls_clkctrl AM3_L4LS_RNG_CLKCTRL 0>; 2073 clock-names = "fck"; 2074 #address-cells = <1>; 2075 #size-cells = <1>; 2076 ranges = <0x0 0x10000 0x2000>; 2077 2078 rng: rng@0 { 2079 compatible = "ti,omap4-rng"; 2080 reg = <0x0 0x2000>; 2081 interrupts = <111>; 2082 }; 2083 }; 2084 2085 target-module@13000 { /* 0x48313000, ap 97 62.0 */ 2086 compatible = "ti,sysc"; 2087 status = "disabled"; 2088 #address-cells = <1>; 2089 #size-cells = <1>; 2090 ranges = <0x0 0x13000 0x1000>; 2091 }; 2092 2093 target-module@15000 { /* 0x48315000, ap 94 56.0 */ 2094 compatible = "ti,sysc"; 2095 status = "disabled"; 2096 #address-cells = <1>; 2097 #size-cells = <1>; 2098 ranges = <0x00000000 0x00015000 0x00001000>, 2099 <0x00001000 0x00016000 0x00001000>; 2100 }; 2101 2102 target-module@18000 { /* 0x48318000, ap 74 4c.0 */ 2103 compatible = "ti,sysc"; 2104 status = "disabled"; 2105 #address-cells = <1>; 2106 #size-cells = <1>; 2107 ranges = <0x0 0x18000 0x4000>; 2108 }; 2109 2110 target-module@20000 { /* 0x48320000, ap 99 34.0 */ 2111 compatible = "ti,sysc"; 2112 status = "disabled"; 2113 #address-cells = <1>; 2114 #size-cells = <1>; 2115 ranges = <0x0 0x20000 0x1000>; 2116 }; 2117 2118 target-module@22000 { /* 0x48322000, ap 101 3e.0 */ 2119 compatible = "ti,sysc"; 2120 status = "disabled"; 2121 #address-cells = <1>; 2122 #size-cells = <1>; 2123 ranges = <0x0 0x22000 0x1000>; 2124 }; 2125 2126 target-module@24000 { /* 0x48324000, ap 103 68.0 */ 2127 compatible = "ti,sysc"; 2128 status = "disabled"; 2129 #address-cells = <1>; 2130 #size-cells = <1>; 2131 ranges = <0x0 0x24000 0x1000>; 2132 }; 2133 }; 2134}; 2135 2136
