1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * ahci.c - AHCI SATA support
4 *
5 * Maintained by: Tejun Heo <tj@kernel.org>
6 * Please ALWAYS copy linux-ide@vger.kernel.org
7 * on emails.
8 *
9 * Copyright 2004-2005 Red Hat, Inc.
10 *
11 * libata documentation is available via 'make {ps|pdf}docs',
12 * as Documentation/driver-api/libata.rst
13 *
14 * AHCI hardware documentation:
15 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
16 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
17 */
18
19 #include <linux/kernel.h>
20 #include <linux/module.h>
21 #include <linux/pci.h>
22 #include <linux/blkdev.h>
23 #include <linux/delay.h>
24 #include <linux/interrupt.h>
25 #include <linux/dma-mapping.h>
26 #include <linux/device.h>
27 #include <linux/dmi.h>
28 #include <linux/gfp.h>
29 #include <scsi/scsi_host.h>
30 #include <scsi/scsi_cmnd.h>
31 #include <linux/libata.h>
32 #include <linux/ahci-remap.h>
33 #include <linux/io-64-nonatomic-lo-hi.h>
34 #include "ahci.h"
35
36 #define DRV_NAME "ahci"
37 #define DRV_VERSION "3.0"
38
39 enum {
40 AHCI_PCI_BAR_STA2X11 = 0,
41 AHCI_PCI_BAR_CAVIUM = 0,
42 AHCI_PCI_BAR_LOONGSON = 0,
43 AHCI_PCI_BAR_ENMOTUS = 2,
44 AHCI_PCI_BAR_CAVIUM_GEN5 = 4,
45 AHCI_PCI_BAR_STANDARD = 5,
46 };
47
48 enum board_ids {
49 /* board IDs by feature in alphabetical order */
50 board_ahci,
51 board_ahci_ign_iferr,
52 board_ahci_low_power,
53 board_ahci_no_debounce_delay,
54 board_ahci_nomsi,
55 board_ahci_noncq,
56 board_ahci_nosntf,
57 board_ahci_yes_fbs,
58
59 /* board IDs for specific chipsets in alphabetical order */
60 board_ahci_al,
61 board_ahci_avn,
62 board_ahci_mcp65,
63 board_ahci_mcp77,
64 board_ahci_mcp89,
65 board_ahci_mv,
66 board_ahci_sb600,
67 board_ahci_sb700, /* for SB700 and SB800 */
68 board_ahci_vt8251,
69
70 /*
71 * board IDs for Intel chipsets that support more than 6 ports
72 * *and* end up needing the PCS quirk.
73 */
74 board_ahci_pcs7,
75
76 /* aliases */
77 board_ahci_mcp_linux = board_ahci_mcp65,
78 board_ahci_mcp67 = board_ahci_mcp65,
79 board_ahci_mcp73 = board_ahci_mcp65,
80 board_ahci_mcp79 = board_ahci_mcp77,
81 };
82
83 static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
84 static void ahci_remove_one(struct pci_dev *dev);
85 static void ahci_shutdown_one(struct pci_dev *dev);
86 static void ahci_intel_pcs_quirk(struct pci_dev *pdev, struct ahci_host_priv *hpriv);
87 static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
88 unsigned long deadline);
89 static int ahci_avn_hardreset(struct ata_link *link, unsigned int *class,
90 unsigned long deadline);
91 static void ahci_mcp89_apple_enable(struct pci_dev *pdev);
92 static bool is_mcp89_apple(struct pci_dev *pdev);
93 static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
94 unsigned long deadline);
95 #ifdef CONFIG_PM
96 static int ahci_pci_device_runtime_suspend(struct device *dev);
97 static int ahci_pci_device_runtime_resume(struct device *dev);
98 #ifdef CONFIG_PM_SLEEP
99 static int ahci_pci_device_suspend(struct device *dev);
100 static int ahci_pci_device_resume(struct device *dev);
101 #endif
102 #endif /* CONFIG_PM */
103
104 static const struct scsi_host_template ahci_sht = {
105 AHCI_SHT("ahci"),
106 };
107
108 static struct ata_port_operations ahci_vt8251_ops = {
109 .inherits = &ahci_ops,
110 .hardreset = ahci_vt8251_hardreset,
111 };
112
113 static struct ata_port_operations ahci_p5wdh_ops = {
114 .inherits = &ahci_ops,
115 .hardreset = ahci_p5wdh_hardreset,
116 };
117
118 static struct ata_port_operations ahci_avn_ops = {
119 .inherits = &ahci_ops,
120 .hardreset = ahci_avn_hardreset,
121 };
122
123 static const struct ata_port_info ahci_port_info[] = {
124 /* by features */
125 [board_ahci] = {
126 .flags = AHCI_FLAG_COMMON,
127 .pio_mask = ATA_PIO4,
128 .udma_mask = ATA_UDMA6,
129 .port_ops = &ahci_ops,
130 },
131 [board_ahci_ign_iferr] = {
132 AHCI_HFLAGS (AHCI_HFLAG_IGN_IRQ_IF_ERR),
133 .flags = AHCI_FLAG_COMMON,
134 .pio_mask = ATA_PIO4,
135 .udma_mask = ATA_UDMA6,
136 .port_ops = &ahci_ops,
137 },
138 [board_ahci_low_power] = {
139 AHCI_HFLAGS (AHCI_HFLAG_USE_LPM_POLICY),
140 .flags = AHCI_FLAG_COMMON,
141 .pio_mask = ATA_PIO4,
142 .udma_mask = ATA_UDMA6,
143 .port_ops = &ahci_ops,
144 },
145 [board_ahci_no_debounce_delay] = {
146 .flags = AHCI_FLAG_COMMON,
147 .link_flags = ATA_LFLAG_NO_DEBOUNCE_DELAY,
148 .pio_mask = ATA_PIO4,
149 .udma_mask = ATA_UDMA6,
150 .port_ops = &ahci_ops,
151 },
152 [board_ahci_nomsi] = {
153 AHCI_HFLAGS (AHCI_HFLAG_NO_MSI),
154 .flags = AHCI_FLAG_COMMON,
155 .pio_mask = ATA_PIO4,
156 .udma_mask = ATA_UDMA6,
157 .port_ops = &ahci_ops,
158 },
159 [board_ahci_noncq] = {
160 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ),
161 .flags = AHCI_FLAG_COMMON,
162 .pio_mask = ATA_PIO4,
163 .udma_mask = ATA_UDMA6,
164 .port_ops = &ahci_ops,
165 },
166 [board_ahci_nosntf] = {
167 AHCI_HFLAGS (AHCI_HFLAG_NO_SNTF),
168 .flags = AHCI_FLAG_COMMON,
169 .pio_mask = ATA_PIO4,
170 .udma_mask = ATA_UDMA6,
171 .port_ops = &ahci_ops,
172 },
173 [board_ahci_yes_fbs] = {
174 AHCI_HFLAGS (AHCI_HFLAG_YES_FBS),
175 .flags = AHCI_FLAG_COMMON,
176 .pio_mask = ATA_PIO4,
177 .udma_mask = ATA_UDMA6,
178 .port_ops = &ahci_ops,
179 },
180 /* by chipsets */
181 [board_ahci_al] = {
182 AHCI_HFLAGS (AHCI_HFLAG_NO_PMP | AHCI_HFLAG_NO_MSI),
183 .flags = AHCI_FLAG_COMMON,
184 .pio_mask = ATA_PIO4,
185 .udma_mask = ATA_UDMA6,
186 .port_ops = &ahci_ops,
187 },
188 [board_ahci_avn] = {
189 .flags = AHCI_FLAG_COMMON,
190 .pio_mask = ATA_PIO4,
191 .udma_mask = ATA_UDMA6,
192 .port_ops = &ahci_avn_ops,
193 },
194 [board_ahci_mcp65] = {
195 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP |
196 AHCI_HFLAG_YES_NCQ),
197 .flags = AHCI_FLAG_COMMON | ATA_FLAG_NO_DIPM,
198 .pio_mask = ATA_PIO4,
199 .udma_mask = ATA_UDMA6,
200 .port_ops = &ahci_ops,
201 },
202 [board_ahci_mcp77] = {
203 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP),
204 .flags = AHCI_FLAG_COMMON,
205 .pio_mask = ATA_PIO4,
206 .udma_mask = ATA_UDMA6,
207 .port_ops = &ahci_ops,
208 },
209 [board_ahci_mcp89] = {
210 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA),
211 .flags = AHCI_FLAG_COMMON,
212 .pio_mask = ATA_PIO4,
213 .udma_mask = ATA_UDMA6,
214 .port_ops = &ahci_ops,
215 },
216 [board_ahci_mv] = {
217 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_MSI |
218 AHCI_HFLAG_MV_PATA | AHCI_HFLAG_NO_PMP),
219 .flags = ATA_FLAG_SATA | ATA_FLAG_PIO_DMA,
220 .pio_mask = ATA_PIO4,
221 .udma_mask = ATA_UDMA6,
222 .port_ops = &ahci_ops,
223 },
224 [board_ahci_sb600] = {
225 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL |
226 AHCI_HFLAG_NO_MSI | AHCI_HFLAG_SECT255 |
227 AHCI_HFLAG_32BIT_ONLY),
228 .flags = AHCI_FLAG_COMMON,
229 .pio_mask = ATA_PIO4,
230 .udma_mask = ATA_UDMA6,
231 .port_ops = &ahci_pmp_retry_srst_ops,
232 },
233 [board_ahci_sb700] = { /* for SB700 and SB800 */
234 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL),
235 .flags = AHCI_FLAG_COMMON,
236 .pio_mask = ATA_PIO4,
237 .udma_mask = ATA_UDMA6,
238 .port_ops = &ahci_pmp_retry_srst_ops,
239 },
240 [board_ahci_vt8251] = {
241 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_PMP),
242 .flags = AHCI_FLAG_COMMON,
243 .pio_mask = ATA_PIO4,
244 .udma_mask = ATA_UDMA6,
245 .port_ops = &ahci_vt8251_ops,
246 },
247 [board_ahci_pcs7] = {
248 .flags = AHCI_FLAG_COMMON,
249 .pio_mask = ATA_PIO4,
250 .udma_mask = ATA_UDMA6,
251 .port_ops = &ahci_ops,
252 },
253 };
254
255 static const struct pci_device_id ahci_pci_tbl[] = {
256 /* Intel */
257 { PCI_VDEVICE(INTEL, 0x06d6), board_ahci }, /* Comet Lake PCH-H RAID */
258 { PCI_VDEVICE(INTEL, 0x2652), board_ahci }, /* ICH6 */
259 { PCI_VDEVICE(INTEL, 0x2653), board_ahci }, /* ICH6M */
260 { PCI_VDEVICE(INTEL, 0x27c1), board_ahci }, /* ICH7 */
261 { PCI_VDEVICE(INTEL, 0x27c5), board_ahci }, /* ICH7M */
262 { PCI_VDEVICE(INTEL, 0x27c3), board_ahci }, /* ICH7R */
263 { PCI_VDEVICE(AL, 0x5288), board_ahci_ign_iferr }, /* ULi M5288 */
264 { PCI_VDEVICE(INTEL, 0x2681), board_ahci }, /* ESB2 */
265 { PCI_VDEVICE(INTEL, 0x2682), board_ahci }, /* ESB2 */
266 { PCI_VDEVICE(INTEL, 0x2683), board_ahci }, /* ESB2 */
267 { PCI_VDEVICE(INTEL, 0x27c6), board_ahci }, /* ICH7-M DH */
268 { PCI_VDEVICE(INTEL, 0x2821), board_ahci }, /* ICH8 */
269 { PCI_VDEVICE(INTEL, 0x2822), board_ahci_nosntf }, /* ICH8/Lewisburg RAID*/
270 { PCI_VDEVICE(INTEL, 0x2824), board_ahci }, /* ICH8 */
271 { PCI_VDEVICE(INTEL, 0x2829), board_ahci }, /* ICH8M */
272 { PCI_VDEVICE(INTEL, 0x282a), board_ahci }, /* ICH8M */
273 { PCI_VDEVICE(INTEL, 0x2922), board_ahci }, /* ICH9 */
274 { PCI_VDEVICE(INTEL, 0x2923), board_ahci }, /* ICH9 */
275 { PCI_VDEVICE(INTEL, 0x2924), board_ahci }, /* ICH9 */
276 { PCI_VDEVICE(INTEL, 0x2925), board_ahci }, /* ICH9 */
277 { PCI_VDEVICE(INTEL, 0x2927), board_ahci }, /* ICH9 */
278 { PCI_VDEVICE(INTEL, 0x2929), board_ahci_low_power }, /* ICH9M */
279 { PCI_VDEVICE(INTEL, 0x292a), board_ahci_low_power }, /* ICH9M */
280 { PCI_VDEVICE(INTEL, 0x292b), board_ahci_low_power }, /* ICH9M */
281 { PCI_VDEVICE(INTEL, 0x292c), board_ahci_low_power }, /* ICH9M */
282 { PCI_VDEVICE(INTEL, 0x292f), board_ahci_low_power }, /* ICH9M */
283 { PCI_VDEVICE(INTEL, 0x294d), board_ahci }, /* ICH9 */
284 { PCI_VDEVICE(INTEL, 0x294e), board_ahci_low_power }, /* ICH9M */
285 { PCI_VDEVICE(INTEL, 0x502a), board_ahci }, /* Tolapai */
286 { PCI_VDEVICE(INTEL, 0x502b), board_ahci }, /* Tolapai */
287 { PCI_VDEVICE(INTEL, 0x3a05), board_ahci }, /* ICH10 */
288 { PCI_VDEVICE(INTEL, 0x3a22), board_ahci }, /* ICH10 */
289 { PCI_VDEVICE(INTEL, 0x3a25), board_ahci }, /* ICH10 */
290 { PCI_VDEVICE(INTEL, 0x3b22), board_ahci }, /* PCH AHCI */
291 { PCI_VDEVICE(INTEL, 0x3b23), board_ahci }, /* PCH AHCI */
292 { PCI_VDEVICE(INTEL, 0x3b24), board_ahci }, /* PCH RAID */
293 { PCI_VDEVICE(INTEL, 0x3b25), board_ahci }, /* PCH RAID */
294 { PCI_VDEVICE(INTEL, 0x3b29), board_ahci_low_power }, /* PCH M AHCI */
295 { PCI_VDEVICE(INTEL, 0x3b2b), board_ahci }, /* PCH RAID */
296 { PCI_VDEVICE(INTEL, 0x3b2c), board_ahci_low_power }, /* PCH M RAID */
297 { PCI_VDEVICE(INTEL, 0x3b2f), board_ahci }, /* PCH AHCI */
298 { PCI_VDEVICE(INTEL, 0x19b0), board_ahci_pcs7 }, /* DNV AHCI */
299 { PCI_VDEVICE(INTEL, 0x19b1), board_ahci_pcs7 }, /* DNV AHCI */
300 { PCI_VDEVICE(INTEL, 0x19b2), board_ahci_pcs7 }, /* DNV AHCI */
301 { PCI_VDEVICE(INTEL, 0x19b3), board_ahci_pcs7 }, /* DNV AHCI */
302 { PCI_VDEVICE(INTEL, 0x19b4), board_ahci_pcs7 }, /* DNV AHCI */
303 { PCI_VDEVICE(INTEL, 0x19b5), board_ahci_pcs7 }, /* DNV AHCI */
304 { PCI_VDEVICE(INTEL, 0x19b6), board_ahci_pcs7 }, /* DNV AHCI */
305 { PCI_VDEVICE(INTEL, 0x19b7), board_ahci_pcs7 }, /* DNV AHCI */
306 { PCI_VDEVICE(INTEL, 0x19bE), board_ahci_pcs7 }, /* DNV AHCI */
307 { PCI_VDEVICE(INTEL, 0x19bF), board_ahci_pcs7 }, /* DNV AHCI */
308 { PCI_VDEVICE(INTEL, 0x19c0), board_ahci_pcs7 }, /* DNV AHCI */
309 { PCI_VDEVICE(INTEL, 0x19c1), board_ahci_pcs7 }, /* DNV AHCI */
310 { PCI_VDEVICE(INTEL, 0x19c2), board_ahci_pcs7 }, /* DNV AHCI */
311 { PCI_VDEVICE(INTEL, 0x19c3), board_ahci_pcs7 }, /* DNV AHCI */
312 { PCI_VDEVICE(INTEL, 0x19c4), board_ahci_pcs7 }, /* DNV AHCI */
313 { PCI_VDEVICE(INTEL, 0x19c5), board_ahci_pcs7 }, /* DNV AHCI */
314 { PCI_VDEVICE(INTEL, 0x19c6), board_ahci_pcs7 }, /* DNV AHCI */
315 { PCI_VDEVICE(INTEL, 0x19c7), board_ahci_pcs7 }, /* DNV AHCI */
316 { PCI_VDEVICE(INTEL, 0x19cE), board_ahci_pcs7 }, /* DNV AHCI */
317 { PCI_VDEVICE(INTEL, 0x19cF), board_ahci_pcs7 }, /* DNV AHCI */
318 { PCI_VDEVICE(INTEL, 0x1c02), board_ahci }, /* CPT AHCI */
319 { PCI_VDEVICE(INTEL, 0x1c03), board_ahci_low_power }, /* CPT M AHCI */
320 { PCI_VDEVICE(INTEL, 0x1c04), board_ahci }, /* CPT RAID */
321 { PCI_VDEVICE(INTEL, 0x1c05), board_ahci_low_power }, /* CPT M RAID */
322 { PCI_VDEVICE(INTEL, 0x1c06), board_ahci }, /* CPT RAID */
323 { PCI_VDEVICE(INTEL, 0x1c07), board_ahci }, /* CPT RAID */
324 { PCI_VDEVICE(INTEL, 0x1d02), board_ahci }, /* PBG AHCI */
325 { PCI_VDEVICE(INTEL, 0x1d04), board_ahci }, /* PBG RAID */
326 { PCI_VDEVICE(INTEL, 0x1d06), board_ahci }, /* PBG RAID */
327 { PCI_VDEVICE(INTEL, 0x2323), board_ahci }, /* DH89xxCC AHCI */
328 { PCI_VDEVICE(INTEL, 0x1e02), board_ahci }, /* Panther Point AHCI */
329 { PCI_VDEVICE(INTEL, 0x1e03), board_ahci_low_power }, /* Panther M AHCI */
330 { PCI_VDEVICE(INTEL, 0x1e04), board_ahci }, /* Panther Point RAID */
331 { PCI_VDEVICE(INTEL, 0x1e05), board_ahci }, /* Panther Point RAID */
332 { PCI_VDEVICE(INTEL, 0x1e06), board_ahci }, /* Panther Point RAID */
333 { PCI_VDEVICE(INTEL, 0x1e07), board_ahci_low_power }, /* Panther M RAID */
334 { PCI_VDEVICE(INTEL, 0x1e0e), board_ahci }, /* Panther Point RAID */
335 { PCI_VDEVICE(INTEL, 0x8c02), board_ahci }, /* Lynx Point AHCI */
336 { PCI_VDEVICE(INTEL, 0x8c03), board_ahci_low_power }, /* Lynx M AHCI */
337 { PCI_VDEVICE(INTEL, 0x8c04), board_ahci }, /* Lynx Point RAID */
338 { PCI_VDEVICE(INTEL, 0x8c05), board_ahci_low_power }, /* Lynx M RAID */
339 { PCI_VDEVICE(INTEL, 0x8c06), board_ahci }, /* Lynx Point RAID */
340 { PCI_VDEVICE(INTEL, 0x8c07), board_ahci_low_power }, /* Lynx M RAID */
341 { PCI_VDEVICE(INTEL, 0x8c0e), board_ahci }, /* Lynx Point RAID */
342 { PCI_VDEVICE(INTEL, 0x8c0f), board_ahci_low_power }, /* Lynx M RAID */
343 { PCI_VDEVICE(INTEL, 0x9c02), board_ahci_low_power }, /* Lynx LP AHCI */
344 { PCI_VDEVICE(INTEL, 0x9c03), board_ahci_low_power }, /* Lynx LP AHCI */
345 { PCI_VDEVICE(INTEL, 0x9c04), board_ahci_low_power }, /* Lynx LP RAID */
346 { PCI_VDEVICE(INTEL, 0x9c05), board_ahci_low_power }, /* Lynx LP RAID */
347 { PCI_VDEVICE(INTEL, 0x9c06), board_ahci_low_power }, /* Lynx LP RAID */
348 { PCI_VDEVICE(INTEL, 0x9c07), board_ahci_low_power }, /* Lynx LP RAID */
349 { PCI_VDEVICE(INTEL, 0x9c0e), board_ahci_low_power }, /* Lynx LP RAID */
350 { PCI_VDEVICE(INTEL, 0x9c0f), board_ahci_low_power }, /* Lynx LP RAID */
351 { PCI_VDEVICE(INTEL, 0x9dd3), board_ahci_low_power }, /* Cannon Lake PCH-LP AHCI */
352 { PCI_VDEVICE(INTEL, 0x1f22), board_ahci }, /* Avoton AHCI */
353 { PCI_VDEVICE(INTEL, 0x1f23), board_ahci }, /* Avoton AHCI */
354 { PCI_VDEVICE(INTEL, 0x1f24), board_ahci }, /* Avoton RAID */
355 { PCI_VDEVICE(INTEL, 0x1f25), board_ahci }, /* Avoton RAID */
356 { PCI_VDEVICE(INTEL, 0x1f26), board_ahci }, /* Avoton RAID */
357 { PCI_VDEVICE(INTEL, 0x1f27), board_ahci }, /* Avoton RAID */
358 { PCI_VDEVICE(INTEL, 0x1f2e), board_ahci }, /* Avoton RAID */
359 { PCI_VDEVICE(INTEL, 0x1f2f), board_ahci }, /* Avoton RAID */
360 { PCI_VDEVICE(INTEL, 0x1f32), board_ahci_avn }, /* Avoton AHCI */
361 { PCI_VDEVICE(INTEL, 0x1f33), board_ahci_avn }, /* Avoton AHCI */
362 { PCI_VDEVICE(INTEL, 0x1f34), board_ahci_avn }, /* Avoton RAID */
363 { PCI_VDEVICE(INTEL, 0x1f35), board_ahci_avn }, /* Avoton RAID */
364 { PCI_VDEVICE(INTEL, 0x1f36), board_ahci_avn }, /* Avoton RAID */
365 { PCI_VDEVICE(INTEL, 0x1f37), board_ahci_avn }, /* Avoton RAID */
366 { PCI_VDEVICE(INTEL, 0x1f3e), board_ahci_avn }, /* Avoton RAID */
367 { PCI_VDEVICE(INTEL, 0x1f3f), board_ahci_avn }, /* Avoton RAID */
368 { PCI_VDEVICE(INTEL, 0x2823), board_ahci }, /* Wellsburg/Lewisburg AHCI*/
369 { PCI_VDEVICE(INTEL, 0x2826), board_ahci }, /* *burg SATA0 'RAID' */
370 { PCI_VDEVICE(INTEL, 0x2827), board_ahci }, /* *burg SATA1 'RAID' */
371 { PCI_VDEVICE(INTEL, 0x282f), board_ahci }, /* *burg SATA2 'RAID' */
372 { PCI_VDEVICE(INTEL, 0x43d4), board_ahci }, /* Rocket Lake PCH-H RAID */
373 { PCI_VDEVICE(INTEL, 0x43d5), board_ahci }, /* Rocket Lake PCH-H RAID */
374 { PCI_VDEVICE(INTEL, 0x43d6), board_ahci }, /* Rocket Lake PCH-H RAID */
375 { PCI_VDEVICE(INTEL, 0x43d7), board_ahci }, /* Rocket Lake PCH-H RAID */
376 { PCI_VDEVICE(INTEL, 0x8d02), board_ahci }, /* Wellsburg AHCI */
377 { PCI_VDEVICE(INTEL, 0x8d04), board_ahci }, /* Wellsburg RAID */
378 { PCI_VDEVICE(INTEL, 0x8d06), board_ahci }, /* Wellsburg RAID */
379 { PCI_VDEVICE(INTEL, 0x8d0e), board_ahci }, /* Wellsburg RAID */
380 { PCI_VDEVICE(INTEL, 0x8d62), board_ahci }, /* Wellsburg AHCI */
381 { PCI_VDEVICE(INTEL, 0x8d64), board_ahci }, /* Wellsburg RAID */
382 { PCI_VDEVICE(INTEL, 0x8d66), board_ahci }, /* Wellsburg RAID */
383 { PCI_VDEVICE(INTEL, 0x8d6e), board_ahci }, /* Wellsburg RAID */
384 { PCI_VDEVICE(INTEL, 0x23a3), board_ahci }, /* Coleto Creek AHCI */
385 { PCI_VDEVICE(INTEL, 0x9c83), board_ahci_low_power }, /* Wildcat LP AHCI */
386 { PCI_VDEVICE(INTEL, 0x9c85), board_ahci_low_power }, /* Wildcat LP RAID */
387 { PCI_VDEVICE(INTEL, 0x9c87), board_ahci_low_power }, /* Wildcat LP RAID */
388 { PCI_VDEVICE(INTEL, 0x9c8f), board_ahci_low_power }, /* Wildcat LP RAID */
389 { PCI_VDEVICE(INTEL, 0x8c82), board_ahci }, /* 9 Series AHCI */
390 { PCI_VDEVICE(INTEL, 0x8c83), board_ahci_low_power }, /* 9 Series M AHCI */
391 { PCI_VDEVICE(INTEL, 0x8c84), board_ahci }, /* 9 Series RAID */
392 { PCI_VDEVICE(INTEL, 0x8c85), board_ahci_low_power }, /* 9 Series M RAID */
393 { PCI_VDEVICE(INTEL, 0x8c86), board_ahci }, /* 9 Series RAID */
394 { PCI_VDEVICE(INTEL, 0x8c87), board_ahci_low_power }, /* 9 Series M RAID */
395 { PCI_VDEVICE(INTEL, 0x8c8e), board_ahci }, /* 9 Series RAID */
396 { PCI_VDEVICE(INTEL, 0x8c8f), board_ahci_low_power }, /* 9 Series M RAID */
397 { PCI_VDEVICE(INTEL, 0x9d03), board_ahci_low_power }, /* Sunrise LP AHCI */
398 { PCI_VDEVICE(INTEL, 0x9d05), board_ahci_low_power }, /* Sunrise LP RAID */
399 { PCI_VDEVICE(INTEL, 0x9d07), board_ahci_low_power }, /* Sunrise LP RAID */
400 { PCI_VDEVICE(INTEL, 0xa102), board_ahci }, /* Sunrise Point-H AHCI */
401 { PCI_VDEVICE(INTEL, 0xa103), board_ahci_low_power }, /* Sunrise M AHCI */
402 { PCI_VDEVICE(INTEL, 0xa105), board_ahci }, /* Sunrise Point-H RAID */
403 { PCI_VDEVICE(INTEL, 0xa106), board_ahci }, /* Sunrise Point-H RAID */
404 { PCI_VDEVICE(INTEL, 0xa107), board_ahci_low_power }, /* Sunrise M RAID */
405 { PCI_VDEVICE(INTEL, 0xa10f), board_ahci }, /* Sunrise Point-H RAID */
406 { PCI_VDEVICE(INTEL, 0xa182), board_ahci }, /* Lewisburg AHCI*/
407 { PCI_VDEVICE(INTEL, 0xa186), board_ahci }, /* Lewisburg RAID*/
408 { PCI_VDEVICE(INTEL, 0xa1d2), board_ahci }, /* Lewisburg RAID*/
409 { PCI_VDEVICE(INTEL, 0xa1d6), board_ahci }, /* Lewisburg RAID*/
410 { PCI_VDEVICE(INTEL, 0xa202), board_ahci }, /* Lewisburg AHCI*/
411 { PCI_VDEVICE(INTEL, 0xa206), board_ahci }, /* Lewisburg RAID*/
412 { PCI_VDEVICE(INTEL, 0xa252), board_ahci }, /* Lewisburg RAID*/
413 { PCI_VDEVICE(INTEL, 0xa256), board_ahci }, /* Lewisburg RAID*/
414 { PCI_VDEVICE(INTEL, 0xa356), board_ahci }, /* Cannon Lake PCH-H RAID */
415 { PCI_VDEVICE(INTEL, 0x06d7), board_ahci }, /* Comet Lake-H RAID */
416 { PCI_VDEVICE(INTEL, 0xa386), board_ahci }, /* Comet Lake PCH-V RAID */
417 { PCI_VDEVICE(INTEL, 0x0f22), board_ahci_low_power }, /* Bay Trail AHCI */
418 { PCI_VDEVICE(INTEL, 0x0f23), board_ahci_low_power }, /* Bay Trail AHCI */
419 { PCI_VDEVICE(INTEL, 0x22a3), board_ahci_low_power }, /* Cherry Tr. AHCI */
420 { PCI_VDEVICE(INTEL, 0x5ae3), board_ahci_low_power }, /* ApolloLake AHCI */
421 { PCI_VDEVICE(INTEL, 0x34d3), board_ahci_low_power }, /* Ice Lake LP AHCI */
422 { PCI_VDEVICE(INTEL, 0x02d3), board_ahci_low_power }, /* Comet Lake PCH-U AHCI */
423 { PCI_VDEVICE(INTEL, 0x02d7), board_ahci_low_power }, /* Comet Lake PCH RAID */
424 /* Elkhart Lake IDs 0x4b60 & 0x4b62 https://sata-io.org/product/8803 not tested yet */
425 { PCI_VDEVICE(INTEL, 0x4b63), board_ahci_low_power }, /* Elkhart Lake AHCI */
426
427 /* JMicron 360/1/3/5/6, match class to avoid IDE function */
428 { PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
429 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci_ign_iferr },
430 /* JMicron 362B and 362C have an AHCI function with IDE class code */
431 { PCI_VDEVICE(JMICRON, 0x2362), board_ahci_ign_iferr },
432 { PCI_VDEVICE(JMICRON, 0x236f), board_ahci_ign_iferr },
433 /* May need to update quirk_jmicron_async_suspend() for additions */
434
435 /* ATI */
436 { PCI_VDEVICE(ATI, 0x4380), board_ahci_sb600 }, /* ATI SB600 */
437 { PCI_VDEVICE(ATI, 0x4390), board_ahci_sb700 }, /* ATI SB700/800 */
438 { PCI_VDEVICE(ATI, 0x4391), board_ahci_sb700 }, /* ATI SB700/800 */
439 { PCI_VDEVICE(ATI, 0x4392), board_ahci_sb700 }, /* ATI SB700/800 */
440 { PCI_VDEVICE(ATI, 0x4393), board_ahci_sb700 }, /* ATI SB700/800 */
441 { PCI_VDEVICE(ATI, 0x4394), board_ahci_sb700 }, /* ATI SB700/800 */
442 { PCI_VDEVICE(ATI, 0x4395), board_ahci_sb700 }, /* ATI SB700/800 */
443
444 /* Amazon's Annapurna Labs support */
445 { PCI_DEVICE(PCI_VENDOR_ID_AMAZON_ANNAPURNA_LABS, 0x0031),
446 .class = PCI_CLASS_STORAGE_SATA_AHCI,
447 .class_mask = 0xffffff,
448 board_ahci_al },
449 /* AMD */
450 { PCI_VDEVICE(AMD, 0x7800), board_ahci }, /* AMD Hudson-2 */
451 { PCI_VDEVICE(AMD, 0x7801), board_ahci_no_debounce_delay }, /* AMD Hudson-2 (AHCI mode) */
452 { PCI_VDEVICE(AMD, 0x7900), board_ahci }, /* AMD CZ */
453 { PCI_VDEVICE(AMD, 0x7901), board_ahci_low_power }, /* AMD Green Sardine */
454 /* AMD is using RAID class only for ahci controllers */
455 { PCI_VENDOR_ID_AMD, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
456 PCI_CLASS_STORAGE_RAID << 8, 0xffffff, board_ahci },
457
458 /* Dell S140/S150 */
459 { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, PCI_SUBVENDOR_ID_DELL, PCI_ANY_ID,
460 PCI_CLASS_STORAGE_RAID << 8, 0xffffff, board_ahci },
461
462 /* VIA */
463 { PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251 }, /* VIA VT8251 */
464 { PCI_VDEVICE(VIA, 0x6287), board_ahci_vt8251 }, /* VIA VT8251 */
465
466 /* NVIDIA */
467 { PCI_VDEVICE(NVIDIA, 0x044c), board_ahci_mcp65 }, /* MCP65 */
468 { PCI_VDEVICE(NVIDIA, 0x044d), board_ahci_mcp65 }, /* MCP65 */
469 { PCI_VDEVICE(NVIDIA, 0x044e), board_ahci_mcp65 }, /* MCP65 */
470 { PCI_VDEVICE(NVIDIA, 0x044f), board_ahci_mcp65 }, /* MCP65 */
471 { PCI_VDEVICE(NVIDIA, 0x045c), board_ahci_mcp65 }, /* MCP65 */
472 { PCI_VDEVICE(NVIDIA, 0x045d), board_ahci_mcp65 }, /* MCP65 */
473 { PCI_VDEVICE(NVIDIA, 0x045e), board_ahci_mcp65 }, /* MCP65 */
474 { PCI_VDEVICE(NVIDIA, 0x045f), board_ahci_mcp65 }, /* MCP65 */
475 { PCI_VDEVICE(NVIDIA, 0x0550), board_ahci_mcp67 }, /* MCP67 */
476 { PCI_VDEVICE(NVIDIA, 0x0551), board_ahci_mcp67 }, /* MCP67 */
477 { PCI_VDEVICE(NVIDIA, 0x0552), board_ahci_mcp67 }, /* MCP67 */
478 { PCI_VDEVICE(NVIDIA, 0x0553), board_ahci_mcp67 }, /* MCP67 */
479 { PCI_VDEVICE(NVIDIA, 0x0554), board_ahci_mcp67 }, /* MCP67 */
480 { PCI_VDEVICE(NVIDIA, 0x0555), board_ahci_mcp67 }, /* MCP67 */
481 { PCI_VDEVICE(NVIDIA, 0x0556), board_ahci_mcp67 }, /* MCP67 */
482 { PCI_VDEVICE(NVIDIA, 0x0557), board_ahci_mcp67 }, /* MCP67 */
483 { PCI_VDEVICE(NVIDIA, 0x0558), board_ahci_mcp67 }, /* MCP67 */
484 { PCI_VDEVICE(NVIDIA, 0x0559), board_ahci_mcp67 }, /* MCP67 */
485 { PCI_VDEVICE(NVIDIA, 0x055a), board_ahci_mcp67 }, /* MCP67 */
486 { PCI_VDEVICE(NVIDIA, 0x055b), board_ahci_mcp67 }, /* MCP67 */
487 { PCI_VDEVICE(NVIDIA, 0x0580), board_ahci_mcp_linux }, /* Linux ID */
488 { PCI_VDEVICE(NVIDIA, 0x0581), board_ahci_mcp_linux }, /* Linux ID */
489 { PCI_VDEVICE(NVIDIA, 0x0582), board_ahci_mcp_linux }, /* Linux ID */
490 { PCI_VDEVICE(NVIDIA, 0x0583), board_ahci_mcp_linux }, /* Linux ID */
491 { PCI_VDEVICE(NVIDIA, 0x0584), board_ahci_mcp_linux }, /* Linux ID */
492 { PCI_VDEVICE(NVIDIA, 0x0585), board_ahci_mcp_linux }, /* Linux ID */
493 { PCI_VDEVICE(NVIDIA, 0x0586), board_ahci_mcp_linux }, /* Linux ID */
494 { PCI_VDEVICE(NVIDIA, 0x0587), board_ahci_mcp_linux }, /* Linux ID */
495 { PCI_VDEVICE(NVIDIA, 0x0588), board_ahci_mcp_linux }, /* Linux ID */
496 { PCI_VDEVICE(NVIDIA, 0x0589), board_ahci_mcp_linux }, /* Linux ID */
497 { PCI_VDEVICE(NVIDIA, 0x058a), board_ahci_mcp_linux }, /* Linux ID */
498 { PCI_VDEVICE(NVIDIA, 0x058b), board_ahci_mcp_linux }, /* Linux ID */
499 { PCI_VDEVICE(NVIDIA, 0x058c), board_ahci_mcp_linux }, /* Linux ID */
500 { PCI_VDEVICE(NVIDIA, 0x058d), board_ahci_mcp_linux }, /* Linux ID */
501 { PCI_VDEVICE(NVIDIA, 0x058e), board_ahci_mcp_linux }, /* Linux ID */
502 { PCI_VDEVICE(NVIDIA, 0x058f), board_ahci_mcp_linux }, /* Linux ID */
503 { PCI_VDEVICE(NVIDIA, 0x07f0), board_ahci_mcp73 }, /* MCP73 */
504 { PCI_VDEVICE(NVIDIA, 0x07f1), board_ahci_mcp73 }, /* MCP73 */
505 { PCI_VDEVICE(NVIDIA, 0x07f2), board_ahci_mcp73 }, /* MCP73 */
506 { PCI_VDEVICE(NVIDIA, 0x07f3), board_ahci_mcp73 }, /* MCP73 */
507 { PCI_VDEVICE(NVIDIA, 0x07f4), board_ahci_mcp73 }, /* MCP73 */
508 { PCI_VDEVICE(NVIDIA, 0x07f5), board_ahci_mcp73 }, /* MCP73 */
509 { PCI_VDEVICE(NVIDIA, 0x07f6), board_ahci_mcp73 }, /* MCP73 */
510 { PCI_VDEVICE(NVIDIA, 0x07f7), board_ahci_mcp73 }, /* MCP73 */
511 { PCI_VDEVICE(NVIDIA, 0x07f8), board_ahci_mcp73 }, /* MCP73 */
512 { PCI_VDEVICE(NVIDIA, 0x07f9), board_ahci_mcp73 }, /* MCP73 */
513 { PCI_VDEVICE(NVIDIA, 0x07fa), board_ahci_mcp73 }, /* MCP73 */
514 { PCI_VDEVICE(NVIDIA, 0x07fb), board_ahci_mcp73 }, /* MCP73 */
515 { PCI_VDEVICE(NVIDIA, 0x0ad0), board_ahci_mcp77 }, /* MCP77 */
516 { PCI_VDEVICE(NVIDIA, 0x0ad1), board_ahci_mcp77 }, /* MCP77 */
517 { PCI_VDEVICE(NVIDIA, 0x0ad2), board_ahci_mcp77 }, /* MCP77 */
518 { PCI_VDEVICE(NVIDIA, 0x0ad3), board_ahci_mcp77 }, /* MCP77 */
519 { PCI_VDEVICE(NVIDIA, 0x0ad4), board_ahci_mcp77 }, /* MCP77 */
520 { PCI_VDEVICE(NVIDIA, 0x0ad5), board_ahci_mcp77 }, /* MCP77 */
521 { PCI_VDEVICE(NVIDIA, 0x0ad6), board_ahci_mcp77 }, /* MCP77 */
522 { PCI_VDEVICE(NVIDIA, 0x0ad7), board_ahci_mcp77 }, /* MCP77 */
523 { PCI_VDEVICE(NVIDIA, 0x0ad8), board_ahci_mcp77 }, /* MCP77 */
524 { PCI_VDEVICE(NVIDIA, 0x0ad9), board_ahci_mcp77 }, /* MCP77 */
525 { PCI_VDEVICE(NVIDIA, 0x0ada), board_ahci_mcp77 }, /* MCP77 */
526 { PCI_VDEVICE(NVIDIA, 0x0adb), board_ahci_mcp77 }, /* MCP77 */
527 { PCI_VDEVICE(NVIDIA, 0x0ab4), board_ahci_mcp79 }, /* MCP79 */
528 { PCI_VDEVICE(NVIDIA, 0x0ab5), board_ahci_mcp79 }, /* MCP79 */
529 { PCI_VDEVICE(NVIDIA, 0x0ab6), board_ahci_mcp79 }, /* MCP79 */
530 { PCI_VDEVICE(NVIDIA, 0x0ab7), board_ahci_mcp79 }, /* MCP79 */
531 { PCI_VDEVICE(NVIDIA, 0x0ab8), board_ahci_mcp79 }, /* MCP79 */
532 { PCI_VDEVICE(NVIDIA, 0x0ab9), board_ahci_mcp79 }, /* MCP79 */
533 { PCI_VDEVICE(NVIDIA, 0x0aba), board_ahci_mcp79 }, /* MCP79 */
534 { PCI_VDEVICE(NVIDIA, 0x0abb), board_ahci_mcp79 }, /* MCP79 */
535 { PCI_VDEVICE(NVIDIA, 0x0abc), board_ahci_mcp79 }, /* MCP79 */
536 { PCI_VDEVICE(NVIDIA, 0x0abd), board_ahci_mcp79 }, /* MCP79 */
537 { PCI_VDEVICE(NVIDIA, 0x0abe), board_ahci_mcp79 }, /* MCP79 */
538 { PCI_VDEVICE(NVIDIA, 0x0abf), board_ahci_mcp79 }, /* MCP79 */
539 { PCI_VDEVICE(NVIDIA, 0x0d84), board_ahci_mcp89 }, /* MCP89 */
540 { PCI_VDEVICE(NVIDIA, 0x0d85), board_ahci_mcp89 }, /* MCP89 */
541 { PCI_VDEVICE(NVIDIA, 0x0d86), board_ahci_mcp89 }, /* MCP89 */
542 { PCI_VDEVICE(NVIDIA, 0x0d87), board_ahci_mcp89 }, /* MCP89 */
543 { PCI_VDEVICE(NVIDIA, 0x0d88), board_ahci_mcp89 }, /* MCP89 */
544 { PCI_VDEVICE(NVIDIA, 0x0d89), board_ahci_mcp89 }, /* MCP89 */
545 { PCI_VDEVICE(NVIDIA, 0x0d8a), board_ahci_mcp89 }, /* MCP89 */
546 { PCI_VDEVICE(NVIDIA, 0x0d8b), board_ahci_mcp89 }, /* MCP89 */
547 { PCI_VDEVICE(NVIDIA, 0x0d8c), board_ahci_mcp89 }, /* MCP89 */
548 { PCI_VDEVICE(NVIDIA, 0x0d8d), board_ahci_mcp89 }, /* MCP89 */
549 { PCI_VDEVICE(NVIDIA, 0x0d8e), board_ahci_mcp89 }, /* MCP89 */
550 { PCI_VDEVICE(NVIDIA, 0x0d8f), board_ahci_mcp89 }, /* MCP89 */
551
552 /* SiS */
553 { PCI_VDEVICE(SI, 0x1184), board_ahci }, /* SiS 966 */
554 { PCI_VDEVICE(SI, 0x1185), board_ahci }, /* SiS 968 */
555 { PCI_VDEVICE(SI, 0x0186), board_ahci }, /* SiS 968 */
556
557 /* ST Microelectronics */
558 { PCI_VDEVICE(STMICRO, 0xCC06), board_ahci }, /* ST ConneXt */
559
560 /* Marvell */
561 { PCI_VDEVICE(MARVELL, 0x6145), board_ahci_mv }, /* 6145 */
562 { PCI_VDEVICE(MARVELL, 0x6121), board_ahci_mv }, /* 6121 */
563 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9123),
564 .class = PCI_CLASS_STORAGE_SATA_AHCI,
565 .class_mask = 0xffffff,
566 .driver_data = board_ahci_yes_fbs }, /* 88se9128 */
567 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9125),
568 .driver_data = board_ahci_yes_fbs }, /* 88se9125 */
569 { PCI_DEVICE_SUB(PCI_VENDOR_ID_MARVELL_EXT, 0x9178,
570 PCI_VENDOR_ID_MARVELL_EXT, 0x9170),
571 .driver_data = board_ahci_yes_fbs }, /* 88se9170 */
572 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x917a),
573 .driver_data = board_ahci_yes_fbs }, /* 88se9172 */
574 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9172),
575 .driver_data = board_ahci_yes_fbs }, /* 88se9182 */
576 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9182),
577 .driver_data = board_ahci_yes_fbs }, /* 88se9172 */
578 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9192),
579 .driver_data = board_ahci_yes_fbs }, /* 88se9172 on some Gigabyte */
580 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a0),
581 .driver_data = board_ahci_yes_fbs },
582 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a2), /* 88se91a2 */
583 .driver_data = board_ahci_yes_fbs },
584 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a3),
585 .driver_data = board_ahci_yes_fbs },
586 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9230),
587 .driver_data = board_ahci_yes_fbs },
588 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9235),
589 .driver_data = board_ahci_no_debounce_delay },
590 { PCI_DEVICE(PCI_VENDOR_ID_TTI, 0x0642), /* highpoint rocketraid 642L */
591 .driver_data = board_ahci_yes_fbs },
592 { PCI_DEVICE(PCI_VENDOR_ID_TTI, 0x0645), /* highpoint rocketraid 644L */
593 .driver_data = board_ahci_yes_fbs },
594
595 /* Promise */
596 { PCI_VDEVICE(PROMISE, 0x3f20), board_ahci }, /* PDC42819 */
597 { PCI_VDEVICE(PROMISE, 0x3781), board_ahci }, /* FastTrak TX8660 ahci-mode */
598
599 /* Asmedia */
600 { PCI_VDEVICE(ASMEDIA, 0x0601), board_ahci }, /* ASM1060 */
601 { PCI_VDEVICE(ASMEDIA, 0x0602), board_ahci }, /* ASM1060 */
602 { PCI_VDEVICE(ASMEDIA, 0x0611), board_ahci }, /* ASM1061 */
603 { PCI_VDEVICE(ASMEDIA, 0x0612), board_ahci }, /* ASM1062 */
604 { PCI_VDEVICE(ASMEDIA, 0x0621), board_ahci }, /* ASM1061R */
605 { PCI_VDEVICE(ASMEDIA, 0x0622), board_ahci }, /* ASM1062R */
606 { PCI_VDEVICE(ASMEDIA, 0x0624), board_ahci }, /* ASM1062+JMB575 */
607
608 /*
609 * Samsung SSDs found on some macbooks. NCQ times out if MSI is
610 * enabled. https://bugzilla.kernel.org/show_bug.cgi?id=60731
611 */
612 { PCI_VDEVICE(SAMSUNG, 0x1600), board_ahci_nomsi },
613 { PCI_VDEVICE(SAMSUNG, 0xa800), board_ahci_nomsi },
614
615 /* Enmotus */
616 { PCI_DEVICE(0x1c44, 0x8000), board_ahci },
617
618 /* Loongson */
619 { PCI_VDEVICE(LOONGSON, 0x7a08), board_ahci },
620
621 /* Generic, PCI class code for AHCI */
622 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
623 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci },
624
625 { } /* terminate list */
626 };
627
628 static const struct dev_pm_ops ahci_pci_pm_ops = {
629 SET_SYSTEM_SLEEP_PM_OPS(ahci_pci_device_suspend, ahci_pci_device_resume)
630 SET_RUNTIME_PM_OPS(ahci_pci_device_runtime_suspend,
631 ahci_pci_device_runtime_resume, NULL)
632 };
633
634 static struct pci_driver ahci_pci_driver = {
635 .name = DRV_NAME,
636 .id_table = ahci_pci_tbl,
637 .probe = ahci_init_one,
638 .remove = ahci_remove_one,
639 .shutdown = ahci_shutdown_one,
640 .driver = {
641 .pm = &ahci_pci_pm_ops,
642 },
643 };
644
645 #if IS_ENABLED(CONFIG_PATA_MARVELL)
646 static int marvell_enable;
647 #else
648 static int marvell_enable = 1;
649 #endif
650 module_param(marvell_enable, int, 0644);
651 MODULE_PARM_DESC(marvell_enable, "Marvell SATA via AHCI (1 = enabled)");
652
653 static int mobile_lpm_policy = -1;
654 module_param(mobile_lpm_policy, int, 0644);
655 MODULE_PARM_DESC(mobile_lpm_policy, "Default LPM policy for mobile chipsets");
656
ahci_pci_save_initial_config(struct pci_dev * pdev,struct ahci_host_priv * hpriv)657 static void ahci_pci_save_initial_config(struct pci_dev *pdev,
658 struct ahci_host_priv *hpriv)
659 {
660 if (pdev->vendor == PCI_VENDOR_ID_JMICRON && pdev->device == 0x2361) {
661 dev_info(&pdev->dev, "JMB361 has only one port\n");
662 hpriv->saved_port_map = 1;
663 }
664
665 /*
666 * Temporary Marvell 6145 hack: PATA port presence
667 * is asserted through the standard AHCI port
668 * presence register, as bit 4 (counting from 0)
669 */
670 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
671 if (pdev->device == 0x6121)
672 hpriv->mask_port_map = 0x3;
673 else
674 hpriv->mask_port_map = 0xf;
675 dev_info(&pdev->dev,
676 "Disabling your PATA port. Use the boot option 'ahci.marvell_enable=0' to avoid this.\n");
677 }
678
679 ahci_save_initial_config(&pdev->dev, hpriv);
680 }
681
ahci_pci_reset_controller(struct ata_host * host)682 static int ahci_pci_reset_controller(struct ata_host *host)
683 {
684 struct pci_dev *pdev = to_pci_dev(host->dev);
685 struct ahci_host_priv *hpriv = host->private_data;
686 int rc;
687
688 rc = ahci_reset_controller(host);
689 if (rc)
690 return rc;
691
692 /*
693 * If platform firmware failed to enable ports, try to enable
694 * them here.
695 */
696 ahci_intel_pcs_quirk(pdev, hpriv);
697
698 return 0;
699 }
700
ahci_pci_init_controller(struct ata_host * host)701 static void ahci_pci_init_controller(struct ata_host *host)
702 {
703 struct ahci_host_priv *hpriv = host->private_data;
704 struct pci_dev *pdev = to_pci_dev(host->dev);
705 void __iomem *port_mmio;
706 u32 tmp;
707 int mv;
708
709 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
710 if (pdev->device == 0x6121)
711 mv = 2;
712 else
713 mv = 4;
714 port_mmio = __ahci_port_base(hpriv, mv);
715
716 writel(0, port_mmio + PORT_IRQ_MASK);
717
718 /* clear port IRQ */
719 tmp = readl(port_mmio + PORT_IRQ_STAT);
720 dev_dbg(&pdev->dev, "PORT_IRQ_STAT 0x%x\n", tmp);
721 if (tmp)
722 writel(tmp, port_mmio + PORT_IRQ_STAT);
723 }
724
725 ahci_init_controller(host);
726 }
727
ahci_vt8251_hardreset(struct ata_link * link,unsigned int * class,unsigned long deadline)728 static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
729 unsigned long deadline)
730 {
731 struct ata_port *ap = link->ap;
732 struct ahci_host_priv *hpriv = ap->host->private_data;
733 bool online;
734 int rc;
735
736 hpriv->stop_engine(ap);
737
738 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
739 deadline, &online, NULL);
740
741 hpriv->start_engine(ap);
742
743 /* vt8251 doesn't clear BSY on signature FIS reception,
744 * request follow-up softreset.
745 */
746 return online ? -EAGAIN : rc;
747 }
748
ahci_p5wdh_hardreset(struct ata_link * link,unsigned int * class,unsigned long deadline)749 static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
750 unsigned long deadline)
751 {
752 struct ata_port *ap = link->ap;
753 struct ahci_port_priv *pp = ap->private_data;
754 struct ahci_host_priv *hpriv = ap->host->private_data;
755 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
756 struct ata_taskfile tf;
757 bool online;
758 int rc;
759
760 hpriv->stop_engine(ap);
761
762 /* clear D2H reception area to properly wait for D2H FIS */
763 ata_tf_init(link->device, &tf);
764 tf.status = ATA_BUSY;
765 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
766
767 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
768 deadline, &online, NULL);
769
770 hpriv->start_engine(ap);
771
772 /* The pseudo configuration device on SIMG4726 attached to
773 * ASUS P5W-DH Deluxe doesn't send signature FIS after
774 * hardreset if no device is attached to the first downstream
775 * port && the pseudo device locks up on SRST w/ PMP==0. To
776 * work around this, wait for !BSY only briefly. If BSY isn't
777 * cleared, perform CLO and proceed to IDENTIFY (achieved by
778 * ATA_LFLAG_NO_SRST and ATA_LFLAG_ASSUME_ATA).
779 *
780 * Wait for two seconds. Devices attached to downstream port
781 * which can't process the following IDENTIFY after this will
782 * have to be reset again. For most cases, this should
783 * suffice while making probing snappish enough.
784 */
785 if (online) {
786 rc = ata_wait_after_reset(link, jiffies + 2 * HZ,
787 ahci_check_ready);
788 if (rc)
789 ahci_kick_engine(ap);
790 }
791 return rc;
792 }
793
794 /*
795 * ahci_avn_hardreset - attempt more aggressive recovery of Avoton ports.
796 *
797 * It has been observed with some SSDs that the timing of events in the
798 * link synchronization phase can leave the port in a state that can not
799 * be recovered by a SATA-hard-reset alone. The failing signature is
800 * SStatus.DET stuck at 1 ("Device presence detected but Phy
801 * communication not established"). It was found that unloading and
802 * reloading the driver when this problem occurs allows the drive
803 * connection to be recovered (DET advanced to 0x3). The critical
804 * component of reloading the driver is that the port state machines are
805 * reset by bouncing "port enable" in the AHCI PCS configuration
806 * register. So, reproduce that effect by bouncing a port whenever we
807 * see DET==1 after a reset.
808 */
ahci_avn_hardreset(struct ata_link * link,unsigned int * class,unsigned long deadline)809 static int ahci_avn_hardreset(struct ata_link *link, unsigned int *class,
810 unsigned long deadline)
811 {
812 const unsigned int *timing = sata_ehc_deb_timing(&link->eh_context);
813 struct ata_port *ap = link->ap;
814 struct ahci_port_priv *pp = ap->private_data;
815 struct ahci_host_priv *hpriv = ap->host->private_data;
816 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
817 unsigned long tmo = deadline - jiffies;
818 struct ata_taskfile tf;
819 bool online;
820 int rc, i;
821
822 hpriv->stop_engine(ap);
823
824 for (i = 0; i < 2; i++) {
825 u16 val;
826 u32 sstatus;
827 int port = ap->port_no;
828 struct ata_host *host = ap->host;
829 struct pci_dev *pdev = to_pci_dev(host->dev);
830
831 /* clear D2H reception area to properly wait for D2H FIS */
832 ata_tf_init(link->device, &tf);
833 tf.status = ATA_BUSY;
834 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
835
836 rc = sata_link_hardreset(link, timing, deadline, &online,
837 ahci_check_ready);
838
839 if (sata_scr_read(link, SCR_STATUS, &sstatus) != 0 ||
840 (sstatus & 0xf) != 1)
841 break;
842
843 ata_link_info(link, "avn bounce port%d\n", port);
844
845 pci_read_config_word(pdev, 0x92, &val);
846 val &= ~(1 << port);
847 pci_write_config_word(pdev, 0x92, val);
848 ata_msleep(ap, 1000);
849 val |= 1 << port;
850 pci_write_config_word(pdev, 0x92, val);
851 deadline += tmo;
852 }
853
854 hpriv->start_engine(ap);
855
856 if (online)
857 *class = ahci_dev_classify(ap);
858
859 return rc;
860 }
861
862
863 #ifdef CONFIG_PM
ahci_pci_disable_interrupts(struct ata_host * host)864 static void ahci_pci_disable_interrupts(struct ata_host *host)
865 {
866 struct ahci_host_priv *hpriv = host->private_data;
867 void __iomem *mmio = hpriv->mmio;
868 u32 ctl;
869
870 /* AHCI spec rev1.1 section 8.3.3:
871 * Software must disable interrupts prior to requesting a
872 * transition of the HBA to D3 state.
873 */
874 ctl = readl(mmio + HOST_CTL);
875 ctl &= ~HOST_IRQ_EN;
876 writel(ctl, mmio + HOST_CTL);
877 readl(mmio + HOST_CTL); /* flush */
878 }
879
ahci_pci_device_runtime_suspend(struct device * dev)880 static int ahci_pci_device_runtime_suspend(struct device *dev)
881 {
882 struct pci_dev *pdev = to_pci_dev(dev);
883 struct ata_host *host = pci_get_drvdata(pdev);
884
885 ahci_pci_disable_interrupts(host);
886 return 0;
887 }
888
ahci_pci_device_runtime_resume(struct device * dev)889 static int ahci_pci_device_runtime_resume(struct device *dev)
890 {
891 struct pci_dev *pdev = to_pci_dev(dev);
892 struct ata_host *host = pci_get_drvdata(pdev);
893 int rc;
894
895 rc = ahci_pci_reset_controller(host);
896 if (rc)
897 return rc;
898 ahci_pci_init_controller(host);
899 return 0;
900 }
901
902 #ifdef CONFIG_PM_SLEEP
ahci_pci_device_suspend(struct device * dev)903 static int ahci_pci_device_suspend(struct device *dev)
904 {
905 struct pci_dev *pdev = to_pci_dev(dev);
906 struct ata_host *host = pci_get_drvdata(pdev);
907 struct ahci_host_priv *hpriv = host->private_data;
908
909 if (hpriv->flags & AHCI_HFLAG_NO_SUSPEND) {
910 dev_err(&pdev->dev,
911 "BIOS update required for suspend/resume\n");
912 return -EIO;
913 }
914
915 ahci_pci_disable_interrupts(host);
916 ata_host_suspend(host, PMSG_SUSPEND);
917 return 0;
918 }
919
ahci_pci_device_resume(struct device * dev)920 static int ahci_pci_device_resume(struct device *dev)
921 {
922 struct pci_dev *pdev = to_pci_dev(dev);
923 struct ata_host *host = pci_get_drvdata(pdev);
924 int rc;
925
926 /* Apple BIOS helpfully mangles the registers on resume */
927 if (is_mcp89_apple(pdev))
928 ahci_mcp89_apple_enable(pdev);
929
930 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
931 rc = ahci_pci_reset_controller(host);
932 if (rc)
933 return rc;
934
935 ahci_pci_init_controller(host);
936 }
937
938 ata_host_resume(host);
939
940 return 0;
941 }
942 #endif
943
944 #endif /* CONFIG_PM */
945
ahci_configure_dma_masks(struct pci_dev * pdev,int using_dac)946 static int ahci_configure_dma_masks(struct pci_dev *pdev, int using_dac)
947 {
948 const int dma_bits = using_dac ? 64 : 32;
949 int rc;
950
951 /*
952 * If the device fixup already set the dma_mask to some non-standard
953 * value, don't extend it here. This happens on STA2X11, for example.
954 *
955 * XXX: manipulating the DMA mask from platform code is completely
956 * bogus, platform code should use dev->bus_dma_limit instead..
957 */
958 if (pdev->dma_mask && pdev->dma_mask < DMA_BIT_MASK(32))
959 return 0;
960
961 rc = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(dma_bits));
962 if (rc)
963 dev_err(&pdev->dev, "DMA enable failed\n");
964 return rc;
965 }
966
ahci_pci_print_info(struct ata_host * host)967 static void ahci_pci_print_info(struct ata_host *host)
968 {
969 struct pci_dev *pdev = to_pci_dev(host->dev);
970 u16 cc;
971 const char *scc_s;
972
973 pci_read_config_word(pdev, 0x0a, &cc);
974 if (cc == PCI_CLASS_STORAGE_IDE)
975 scc_s = "IDE";
976 else if (cc == PCI_CLASS_STORAGE_SATA)
977 scc_s = "SATA";
978 else if (cc == PCI_CLASS_STORAGE_RAID)
979 scc_s = "RAID";
980 else
981 scc_s = "unknown";
982
983 ahci_print_info(host, scc_s);
984 }
985
986 /* On ASUS P5W DH Deluxe, the second port of PCI device 00:1f.2 is
987 * hardwired to on-board SIMG 4726. The chipset is ICH8 and doesn't
988 * support PMP and the 4726 either directly exports the device
989 * attached to the first downstream port or acts as a hardware storage
990 * controller and emulate a single ATA device (can be RAID 0/1 or some
991 * other configuration).
992 *
993 * When there's no device attached to the first downstream port of the
994 * 4726, "Config Disk" appears, which is a pseudo ATA device to
995 * configure the 4726. However, ATA emulation of the device is very
996 * lame. It doesn't send signature D2H Reg FIS after the initial
997 * hardreset, pukes on SRST w/ PMP==0 and has bunch of other issues.
998 *
999 * The following function works around the problem by always using
1000 * hardreset on the port and not depending on receiving signature FIS
1001 * afterward. If signature FIS isn't received soon, ATA class is
1002 * assumed without follow-up softreset.
1003 */
ahci_p5wdh_workaround(struct ata_host * host)1004 static void ahci_p5wdh_workaround(struct ata_host *host)
1005 {
1006 static const struct dmi_system_id sysids[] = {
1007 {
1008 .ident = "P5W DH Deluxe",
1009 .matches = {
1010 DMI_MATCH(DMI_SYS_VENDOR,
1011 "ASUSTEK COMPUTER INC"),
1012 DMI_MATCH(DMI_PRODUCT_NAME, "P5W DH Deluxe"),
1013 },
1014 },
1015 { }
1016 };
1017 struct pci_dev *pdev = to_pci_dev(host->dev);
1018
1019 if (pdev->bus->number == 0 && pdev->devfn == PCI_DEVFN(0x1f, 2) &&
1020 dmi_check_system(sysids)) {
1021 struct ata_port *ap = host->ports[1];
1022
1023 dev_info(&pdev->dev,
1024 "enabling ASUS P5W DH Deluxe on-board SIMG4726 workaround\n");
1025
1026 ap->ops = &ahci_p5wdh_ops;
1027 ap->link.flags |= ATA_LFLAG_NO_SRST | ATA_LFLAG_ASSUME_ATA;
1028 }
1029 }
1030
1031 /*
1032 * Macbook7,1 firmware forcibly disables MCP89 AHCI and changes PCI ID when
1033 * booting in BIOS compatibility mode. We restore the registers but not ID.
1034 */
ahci_mcp89_apple_enable(struct pci_dev * pdev)1035 static void ahci_mcp89_apple_enable(struct pci_dev *pdev)
1036 {
1037 u32 val;
1038
1039 printk(KERN_INFO "ahci: enabling MCP89 AHCI mode\n");
1040
1041 pci_read_config_dword(pdev, 0xf8, &val);
1042 val |= 1 << 0x1b;
1043 /* the following changes the device ID, but appears not to affect function */
1044 /* val = (val & ~0xf0000000) | 0x80000000; */
1045 pci_write_config_dword(pdev, 0xf8, val);
1046
1047 pci_read_config_dword(pdev, 0x54c, &val);
1048 val |= 1 << 0xc;
1049 pci_write_config_dword(pdev, 0x54c, val);
1050
1051 pci_read_config_dword(pdev, 0x4a4, &val);
1052 val &= 0xff;
1053 val |= 0x01060100;
1054 pci_write_config_dword(pdev, 0x4a4, val);
1055
1056 pci_read_config_dword(pdev, 0x54c, &val);
1057 val &= ~(1 << 0xc);
1058 pci_write_config_dword(pdev, 0x54c, val);
1059
1060 pci_read_config_dword(pdev, 0xf8, &val);
1061 val &= ~(1 << 0x1b);
1062 pci_write_config_dword(pdev, 0xf8, val);
1063 }
1064
is_mcp89_apple(struct pci_dev * pdev)1065 static bool is_mcp89_apple(struct pci_dev *pdev)
1066 {
1067 return pdev->vendor == PCI_VENDOR_ID_NVIDIA &&
1068 pdev->device == PCI_DEVICE_ID_NVIDIA_NFORCE_MCP89_SATA &&
1069 pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE &&
1070 pdev->subsystem_device == 0xcb89;
1071 }
1072
1073 /* only some SB600 ahci controllers can do 64bit DMA */
ahci_sb600_enable_64bit(struct pci_dev * pdev)1074 static bool ahci_sb600_enable_64bit(struct pci_dev *pdev)
1075 {
1076 static const struct dmi_system_id sysids[] = {
1077 /*
1078 * The oldest version known to be broken is 0901 and
1079 * working is 1501 which was released on 2007-10-26.
1080 * Enable 64bit DMA on 1501 and anything newer.
1081 *
1082 * Please read bko#9412 for more info.
1083 */
1084 {
1085 .ident = "ASUS M2A-VM",
1086 .matches = {
1087 DMI_MATCH(DMI_BOARD_VENDOR,
1088 "ASUSTeK Computer INC."),
1089 DMI_MATCH(DMI_BOARD_NAME, "M2A-VM"),
1090 },
1091 .driver_data = "20071026", /* yyyymmdd */
1092 },
1093 /*
1094 * All BIOS versions for the MSI K9A2 Platinum (MS-7376)
1095 * support 64bit DMA.
1096 *
1097 * BIOS versions earlier than 1.5 had the Manufacturer DMI
1098 * fields as "MICRO-STAR INTERANTIONAL CO.,LTD".
1099 * This spelling mistake was fixed in BIOS version 1.5, so
1100 * 1.5 and later have the Manufacturer as
1101 * "MICRO-STAR INTERNATIONAL CO.,LTD".
1102 * So try to match on DMI_BOARD_VENDOR of "MICRO-STAR INTER".
1103 *
1104 * BIOS versions earlier than 1.9 had a Board Product Name
1105 * DMI field of "MS-7376". This was changed to be
1106 * "K9A2 Platinum (MS-7376)" in version 1.9, but we can still
1107 * match on DMI_BOARD_NAME of "MS-7376".
1108 */
1109 {
1110 .ident = "MSI K9A2 Platinum",
1111 .matches = {
1112 DMI_MATCH(DMI_BOARD_VENDOR,
1113 "MICRO-STAR INTER"),
1114 DMI_MATCH(DMI_BOARD_NAME, "MS-7376"),
1115 },
1116 },
1117 /*
1118 * All BIOS versions for the MSI K9AGM2 (MS-7327) support
1119 * 64bit DMA.
1120 *
1121 * This board also had the typo mentioned above in the
1122 * Manufacturer DMI field (fixed in BIOS version 1.5), so
1123 * match on DMI_BOARD_VENDOR of "MICRO-STAR INTER" again.
1124 */
1125 {
1126 .ident = "MSI K9AGM2",
1127 .matches = {
1128 DMI_MATCH(DMI_BOARD_VENDOR,
1129 "MICRO-STAR INTER"),
1130 DMI_MATCH(DMI_BOARD_NAME, "MS-7327"),
1131 },
1132 },
1133 /*
1134 * All BIOS versions for the Asus M3A support 64bit DMA.
1135 * (all release versions from 0301 to 1206 were tested)
1136 */
1137 {
1138 .ident = "ASUS M3A",
1139 .matches = {
1140 DMI_MATCH(DMI_BOARD_VENDOR,
1141 "ASUSTeK Computer INC."),
1142 DMI_MATCH(DMI_BOARD_NAME, "M3A"),
1143 },
1144 },
1145 { }
1146 };
1147 const struct dmi_system_id *match;
1148 int year, month, date;
1149 char buf[9];
1150
1151 match = dmi_first_match(sysids);
1152 if (pdev->bus->number != 0 || pdev->devfn != PCI_DEVFN(0x12, 0) ||
1153 !match)
1154 return false;
1155
1156 if (!match->driver_data)
1157 goto enable_64bit;
1158
1159 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
1160 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
1161
1162 if (strcmp(buf, match->driver_data) >= 0)
1163 goto enable_64bit;
1164 else {
1165 dev_warn(&pdev->dev,
1166 "%s: BIOS too old, forcing 32bit DMA, update BIOS\n",
1167 match->ident);
1168 return false;
1169 }
1170
1171 enable_64bit:
1172 dev_warn(&pdev->dev, "%s: enabling 64bit DMA\n", match->ident);
1173 return true;
1174 }
1175
ahci_broken_system_poweroff(struct pci_dev * pdev)1176 static bool ahci_broken_system_poweroff(struct pci_dev *pdev)
1177 {
1178 static const struct dmi_system_id broken_systems[] = {
1179 {
1180 .ident = "HP Compaq nx6310",
1181 .matches = {
1182 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1183 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq nx6310"),
1184 },
1185 /* PCI slot number of the controller */
1186 .driver_data = (void *)0x1FUL,
1187 },
1188 {
1189 .ident = "HP Compaq 6720s",
1190 .matches = {
1191 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1192 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq 6720s"),
1193 },
1194 /* PCI slot number of the controller */
1195 .driver_data = (void *)0x1FUL,
1196 },
1197
1198 { } /* terminate list */
1199 };
1200 const struct dmi_system_id *dmi = dmi_first_match(broken_systems);
1201
1202 if (dmi) {
1203 unsigned long slot = (unsigned long)dmi->driver_data;
1204 /* apply the quirk only to on-board controllers */
1205 return slot == PCI_SLOT(pdev->devfn);
1206 }
1207
1208 return false;
1209 }
1210
ahci_broken_suspend(struct pci_dev * pdev)1211 static bool ahci_broken_suspend(struct pci_dev *pdev)
1212 {
1213 static const struct dmi_system_id sysids[] = {
1214 /*
1215 * On HP dv[4-6] and HDX18 with earlier BIOSen, link
1216 * to the harddisk doesn't become online after
1217 * resuming from STR. Warn and fail suspend.
1218 *
1219 * http://bugzilla.kernel.org/show_bug.cgi?id=12276
1220 *
1221 * Use dates instead of versions to match as HP is
1222 * apparently recycling both product and version
1223 * strings.
1224 *
1225 * http://bugzilla.kernel.org/show_bug.cgi?id=15462
1226 */
1227 {
1228 .ident = "dv4",
1229 .matches = {
1230 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1231 DMI_MATCH(DMI_PRODUCT_NAME,
1232 "HP Pavilion dv4 Notebook PC"),
1233 },
1234 .driver_data = "20090105", /* F.30 */
1235 },
1236 {
1237 .ident = "dv5",
1238 .matches = {
1239 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1240 DMI_MATCH(DMI_PRODUCT_NAME,
1241 "HP Pavilion dv5 Notebook PC"),
1242 },
1243 .driver_data = "20090506", /* F.16 */
1244 },
1245 {
1246 .ident = "dv6",
1247 .matches = {
1248 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1249 DMI_MATCH(DMI_PRODUCT_NAME,
1250 "HP Pavilion dv6 Notebook PC"),
1251 },
1252 .driver_data = "20090423", /* F.21 */
1253 },
1254 {
1255 .ident = "HDX18",
1256 .matches = {
1257 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1258 DMI_MATCH(DMI_PRODUCT_NAME,
1259 "HP HDX18 Notebook PC"),
1260 },
1261 .driver_data = "20090430", /* F.23 */
1262 },
1263 /*
1264 * Acer eMachines G725 has the same problem. BIOS
1265 * V1.03 is known to be broken. V3.04 is known to
1266 * work. Between, there are V1.06, V2.06 and V3.03
1267 * that we don't have much idea about. For now,
1268 * blacklist anything older than V3.04.
1269 *
1270 * http://bugzilla.kernel.org/show_bug.cgi?id=15104
1271 */
1272 {
1273 .ident = "G725",
1274 .matches = {
1275 DMI_MATCH(DMI_SYS_VENDOR, "eMachines"),
1276 DMI_MATCH(DMI_PRODUCT_NAME, "eMachines G725"),
1277 },
1278 .driver_data = "20091216", /* V3.04 */
1279 },
1280 { } /* terminate list */
1281 };
1282 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1283 int year, month, date;
1284 char buf[9];
1285
1286 if (!dmi || pdev->bus->number || pdev->devfn != PCI_DEVFN(0x1f, 2))
1287 return false;
1288
1289 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
1290 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
1291
1292 return strcmp(buf, dmi->driver_data) < 0;
1293 }
1294
ahci_broken_lpm(struct pci_dev * pdev)1295 static bool ahci_broken_lpm(struct pci_dev *pdev)
1296 {
1297 static const struct dmi_system_id sysids[] = {
1298 /* Various Lenovo 50 series have LPM issues with older BIOSen */
1299 {
1300 .matches = {
1301 DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"),
1302 DMI_MATCH(DMI_PRODUCT_VERSION, "ThinkPad X250"),
1303 },
1304 .driver_data = "20180406", /* 1.31 */
1305 },
1306 {
1307 .matches = {
1308 DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"),
1309 DMI_MATCH(DMI_PRODUCT_VERSION, "ThinkPad L450"),
1310 },
1311 .driver_data = "20180420", /* 1.28 */
1312 },
1313 {
1314 .matches = {
1315 DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"),
1316 DMI_MATCH(DMI_PRODUCT_VERSION, "ThinkPad T450s"),
1317 },
1318 .driver_data = "20180315", /* 1.33 */
1319 },
1320 {
1321 .matches = {
1322 DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"),
1323 DMI_MATCH(DMI_PRODUCT_VERSION, "ThinkPad W541"),
1324 },
1325 /*
1326 * Note date based on release notes, 2.35 has been
1327 * reported to be good, but I've been unable to get
1328 * a hold of the reporter to get the DMI BIOS date.
1329 * TODO: fix this.
1330 */
1331 .driver_data = "20180310", /* 2.35 */
1332 },
1333 { } /* terminate list */
1334 };
1335 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1336 int year, month, date;
1337 char buf[9];
1338
1339 if (!dmi)
1340 return false;
1341
1342 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
1343 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
1344
1345 return strcmp(buf, dmi->driver_data) < 0;
1346 }
1347
ahci_broken_online(struct pci_dev * pdev)1348 static bool ahci_broken_online(struct pci_dev *pdev)
1349 {
1350 #define ENCODE_BUSDEVFN(bus, slot, func) \
1351 (void *)(unsigned long)(((bus) << 8) | PCI_DEVFN((slot), (func)))
1352 static const struct dmi_system_id sysids[] = {
1353 /*
1354 * There are several gigabyte boards which use
1355 * SIMG5723s configured as hardware RAID. Certain
1356 * 5723 firmware revisions shipped there keep the link
1357 * online but fail to answer properly to SRST or
1358 * IDENTIFY when no device is attached downstream
1359 * causing libata to retry quite a few times leading
1360 * to excessive detection delay.
1361 *
1362 * As these firmwares respond to the second reset try
1363 * with invalid device signature, considering unknown
1364 * sig as offline works around the problem acceptably.
1365 */
1366 {
1367 .ident = "EP45-DQ6",
1368 .matches = {
1369 DMI_MATCH(DMI_BOARD_VENDOR,
1370 "Gigabyte Technology Co., Ltd."),
1371 DMI_MATCH(DMI_BOARD_NAME, "EP45-DQ6"),
1372 },
1373 .driver_data = ENCODE_BUSDEVFN(0x0a, 0x00, 0),
1374 },
1375 {
1376 .ident = "EP45-DS5",
1377 .matches = {
1378 DMI_MATCH(DMI_BOARD_VENDOR,
1379 "Gigabyte Technology Co., Ltd."),
1380 DMI_MATCH(DMI_BOARD_NAME, "EP45-DS5"),
1381 },
1382 .driver_data = ENCODE_BUSDEVFN(0x03, 0x00, 0),
1383 },
1384 { } /* terminate list */
1385 };
1386 #undef ENCODE_BUSDEVFN
1387 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1388 unsigned int val;
1389
1390 if (!dmi)
1391 return false;
1392
1393 val = (unsigned long)dmi->driver_data;
1394
1395 return pdev->bus->number == (val >> 8) && pdev->devfn == (val & 0xff);
1396 }
1397
ahci_broken_devslp(struct pci_dev * pdev)1398 static bool ahci_broken_devslp(struct pci_dev *pdev)
1399 {
1400 /* device with broken DEVSLP but still showing SDS capability */
1401 static const struct pci_device_id ids[] = {
1402 { PCI_VDEVICE(INTEL, 0x0f23)}, /* Valleyview SoC */
1403 {}
1404 };
1405
1406 return pci_match_id(ids, pdev);
1407 }
1408
1409 #ifdef CONFIG_ATA_ACPI
ahci_gtf_filter_workaround(struct ata_host * host)1410 static void ahci_gtf_filter_workaround(struct ata_host *host)
1411 {
1412 static const struct dmi_system_id sysids[] = {
1413 /*
1414 * Aspire 3810T issues a bunch of SATA enable commands
1415 * via _GTF including an invalid one and one which is
1416 * rejected by the device. Among the successful ones
1417 * is FPDMA non-zero offset enable which when enabled
1418 * only on the drive side leads to NCQ command
1419 * failures. Filter it out.
1420 */
1421 {
1422 .ident = "Aspire 3810T",
1423 .matches = {
1424 DMI_MATCH(DMI_SYS_VENDOR, "Acer"),
1425 DMI_MATCH(DMI_PRODUCT_NAME, "Aspire 3810T"),
1426 },
1427 .driver_data = (void *)ATA_ACPI_FILTER_FPDMA_OFFSET,
1428 },
1429 { }
1430 };
1431 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1432 unsigned int filter;
1433 int i;
1434
1435 if (!dmi)
1436 return;
1437
1438 filter = (unsigned long)dmi->driver_data;
1439 dev_info(host->dev, "applying extra ACPI _GTF filter 0x%x for %s\n",
1440 filter, dmi->ident);
1441
1442 for (i = 0; i < host->n_ports; i++) {
1443 struct ata_port *ap = host->ports[i];
1444 struct ata_link *link;
1445 struct ata_device *dev;
1446
1447 ata_for_each_link(link, ap, EDGE)
1448 ata_for_each_dev(dev, link, ALL)
1449 dev->gtf_filter |= filter;
1450 }
1451 }
1452 #else
ahci_gtf_filter_workaround(struct ata_host * host)1453 static inline void ahci_gtf_filter_workaround(struct ata_host *host)
1454 {}
1455 #endif
1456
1457 /*
1458 * On the Acer Aspire Switch Alpha 12, sometimes all SATA ports are detected
1459 * as DUMMY, or detected but eventually get a "link down" and never get up
1460 * again. When this happens, CAP.NP may hold a value of 0x00 or 0x01, and the
1461 * port_map may hold a value of 0x00.
1462 *
1463 * Overriding CAP.NP to 0x02 and the port_map to 0x7 will reveal all 3 ports
1464 * and can significantly reduce the occurrence of the problem.
1465 *
1466 * https://bugzilla.kernel.org/show_bug.cgi?id=189471
1467 */
acer_sa5_271_workaround(struct ahci_host_priv * hpriv,struct pci_dev * pdev)1468 static void acer_sa5_271_workaround(struct ahci_host_priv *hpriv,
1469 struct pci_dev *pdev)
1470 {
1471 static const struct dmi_system_id sysids[] = {
1472 {
1473 .ident = "Acer Switch Alpha 12",
1474 .matches = {
1475 DMI_MATCH(DMI_SYS_VENDOR, "Acer"),
1476 DMI_MATCH(DMI_PRODUCT_NAME, "Switch SA5-271")
1477 },
1478 },
1479 { }
1480 };
1481
1482 if (dmi_check_system(sysids)) {
1483 dev_info(&pdev->dev, "enabling Acer Switch Alpha 12 workaround\n");
1484 if ((hpriv->saved_cap & 0xC734FF00) == 0xC734FF00) {
1485 hpriv->port_map = 0x7;
1486 hpriv->cap = 0xC734FF02;
1487 }
1488 }
1489 }
1490
1491 #ifdef CONFIG_ARM64
1492 /*
1493 * Due to ERRATA#22536, ThunderX needs to handle HOST_IRQ_STAT differently.
1494 * Workaround is to make sure all pending IRQs are served before leaving
1495 * handler.
1496 */
ahci_thunderx_irq_handler(int irq,void * dev_instance)1497 static irqreturn_t ahci_thunderx_irq_handler(int irq, void *dev_instance)
1498 {
1499 struct ata_host *host = dev_instance;
1500 struct ahci_host_priv *hpriv;
1501 unsigned int rc = 0;
1502 void __iomem *mmio;
1503 u32 irq_stat, irq_masked;
1504 unsigned int handled = 1;
1505
1506 hpriv = host->private_data;
1507 mmio = hpriv->mmio;
1508 irq_stat = readl(mmio + HOST_IRQ_STAT);
1509 if (!irq_stat)
1510 return IRQ_NONE;
1511
1512 do {
1513 irq_masked = irq_stat & hpriv->port_map;
1514 spin_lock(&host->lock);
1515 rc = ahci_handle_port_intr(host, irq_masked);
1516 if (!rc)
1517 handled = 0;
1518 writel(irq_stat, mmio + HOST_IRQ_STAT);
1519 irq_stat = readl(mmio + HOST_IRQ_STAT);
1520 spin_unlock(&host->lock);
1521 } while (irq_stat);
1522
1523 return IRQ_RETVAL(handled);
1524 }
1525 #endif
1526
ahci_remap_check(struct pci_dev * pdev,int bar,struct ahci_host_priv * hpriv)1527 static void ahci_remap_check(struct pci_dev *pdev, int bar,
1528 struct ahci_host_priv *hpriv)
1529 {
1530 int i;
1531 u32 cap;
1532
1533 /*
1534 * Check if this device might have remapped nvme devices.
1535 */
1536 if (pdev->vendor != PCI_VENDOR_ID_INTEL ||
1537 pci_resource_len(pdev, bar) < SZ_512K ||
1538 bar != AHCI_PCI_BAR_STANDARD ||
1539 !(readl(hpriv->mmio + AHCI_VSCAP) & 1))
1540 return;
1541
1542 cap = readq(hpriv->mmio + AHCI_REMAP_CAP);
1543 for (i = 0; i < AHCI_MAX_REMAP; i++) {
1544 if ((cap & (1 << i)) == 0)
1545 continue;
1546 if (readl(hpriv->mmio + ahci_remap_dcc(i))
1547 != PCI_CLASS_STORAGE_EXPRESS)
1548 continue;
1549
1550 /* We've found a remapped device */
1551 hpriv->remapped_nvme++;
1552 }
1553
1554 if (!hpriv->remapped_nvme)
1555 return;
1556
1557 dev_warn(&pdev->dev, "Found %u remapped NVMe devices.\n",
1558 hpriv->remapped_nvme);
1559 dev_warn(&pdev->dev,
1560 "Switch your BIOS from RAID to AHCI mode to use them.\n");
1561
1562 /*
1563 * Don't rely on the msi-x capability in the remap case,
1564 * share the legacy interrupt across ahci and remapped devices.
1565 */
1566 hpriv->flags |= AHCI_HFLAG_NO_MSI;
1567 }
1568
ahci_get_irq_vector(struct ata_host * host,int port)1569 static int ahci_get_irq_vector(struct ata_host *host, int port)
1570 {
1571 return pci_irq_vector(to_pci_dev(host->dev), port);
1572 }
1573
ahci_init_msi(struct pci_dev * pdev,unsigned int n_ports,struct ahci_host_priv * hpriv)1574 static int ahci_init_msi(struct pci_dev *pdev, unsigned int n_ports,
1575 struct ahci_host_priv *hpriv)
1576 {
1577 int nvec;
1578
1579 if (hpriv->flags & AHCI_HFLAG_NO_MSI)
1580 return -ENODEV;
1581
1582 /*
1583 * If number of MSIs is less than number of ports then Sharing Last
1584 * Message mode could be enforced. In this case assume that advantage
1585 * of multipe MSIs is negated and use single MSI mode instead.
1586 */
1587 if (n_ports > 1) {
1588 nvec = pci_alloc_irq_vectors(pdev, n_ports, INT_MAX,
1589 PCI_IRQ_MSIX | PCI_IRQ_MSI);
1590 if (nvec > 0) {
1591 if (!(readl(hpriv->mmio + HOST_CTL) & HOST_MRSM)) {
1592 hpriv->get_irq_vector = ahci_get_irq_vector;
1593 hpriv->flags |= AHCI_HFLAG_MULTI_MSI;
1594 return nvec;
1595 }
1596
1597 /*
1598 * Fallback to single MSI mode if the controller
1599 * enforced MRSM mode.
1600 */
1601 printk(KERN_INFO
1602 "ahci: MRSM is on, fallback to single MSI\n");
1603 pci_free_irq_vectors(pdev);
1604 }
1605 }
1606
1607 /*
1608 * If the host is not capable of supporting per-port vectors, fall
1609 * back to single MSI before finally attempting single MSI-X.
1610 */
1611 nvec = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_MSI);
1612 if (nvec == 1)
1613 return nvec;
1614 return pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_MSIX);
1615 }
1616
ahci_update_initial_lpm_policy(struct ata_port * ap,struct ahci_host_priv * hpriv)1617 static void ahci_update_initial_lpm_policy(struct ata_port *ap,
1618 struct ahci_host_priv *hpriv)
1619 {
1620 int policy = CONFIG_SATA_MOBILE_LPM_POLICY;
1621
1622
1623 /* Ignore processing for chipsets that don't use policy */
1624 if (!(hpriv->flags & AHCI_HFLAG_USE_LPM_POLICY))
1625 return;
1626
1627 /* user modified policy via module param */
1628 if (mobile_lpm_policy != -1) {
1629 policy = mobile_lpm_policy;
1630 goto update_policy;
1631 }
1632
1633 if (policy > ATA_LPM_MED_POWER && pm_suspend_default_s2idle()) {
1634 if (hpriv->cap & HOST_CAP_PART)
1635 policy = ATA_LPM_MIN_POWER_WITH_PARTIAL;
1636 else if (hpriv->cap & HOST_CAP_SSC)
1637 policy = ATA_LPM_MIN_POWER;
1638 }
1639
1640 update_policy:
1641 if (policy >= ATA_LPM_UNKNOWN && policy <= ATA_LPM_MIN_POWER)
1642 ap->target_lpm_policy = policy;
1643 }
1644
ahci_intel_pcs_quirk(struct pci_dev * pdev,struct ahci_host_priv * hpriv)1645 static void ahci_intel_pcs_quirk(struct pci_dev *pdev, struct ahci_host_priv *hpriv)
1646 {
1647 const struct pci_device_id *id = pci_match_id(ahci_pci_tbl, pdev);
1648 u16 tmp16;
1649
1650 /*
1651 * Only apply the 6-port PCS quirk for known legacy platforms.
1652 */
1653 if (!id || id->vendor != PCI_VENDOR_ID_INTEL)
1654 return;
1655
1656 /* Skip applying the quirk on Denverton and beyond */
1657 if (((enum board_ids) id->driver_data) >= board_ahci_pcs7)
1658 return;
1659
1660 /*
1661 * port_map is determined from PORTS_IMPL PCI register which is
1662 * implemented as write or write-once register. If the register
1663 * isn't programmed, ahci automatically generates it from number
1664 * of ports, which is good enough for PCS programming. It is
1665 * otherwise expected that platform firmware enables the ports
1666 * before the OS boots.
1667 */
1668 pci_read_config_word(pdev, PCS_6, &tmp16);
1669 if ((tmp16 & hpriv->port_map) != hpriv->port_map) {
1670 tmp16 |= hpriv->port_map;
1671 pci_write_config_word(pdev, PCS_6, tmp16);
1672 }
1673 }
1674
remapped_nvme_show(struct device * dev,struct device_attribute * attr,char * buf)1675 static ssize_t remapped_nvme_show(struct device *dev,
1676 struct device_attribute *attr,
1677 char *buf)
1678 {
1679 struct ata_host *host = dev_get_drvdata(dev);
1680 struct ahci_host_priv *hpriv = host->private_data;
1681
1682 return sysfs_emit(buf, "%u\n", hpriv->remapped_nvme);
1683 }
1684
1685 static DEVICE_ATTR_RO(remapped_nvme);
1686
ahci_init_one(struct pci_dev * pdev,const struct pci_device_id * ent)1687 static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1688 {
1689 unsigned int board_id = ent->driver_data;
1690 struct ata_port_info pi = ahci_port_info[board_id];
1691 const struct ata_port_info *ppi[] = { &pi, NULL };
1692 struct device *dev = &pdev->dev;
1693 struct ahci_host_priv *hpriv;
1694 struct ata_host *host;
1695 int n_ports, i, rc;
1696 int ahci_pci_bar = AHCI_PCI_BAR_STANDARD;
1697
1698 WARN_ON((int)ATA_MAX_QUEUE > AHCI_MAX_CMDS);
1699
1700 ata_print_version_once(&pdev->dev, DRV_VERSION);
1701
1702 /* The AHCI driver can only drive the SATA ports, the PATA driver
1703 can drive them all so if both drivers are selected make sure
1704 AHCI stays out of the way */
1705 if (pdev->vendor == PCI_VENDOR_ID_MARVELL && !marvell_enable)
1706 return -ENODEV;
1707
1708 /* Apple BIOS on MCP89 prevents us using AHCI */
1709 if (is_mcp89_apple(pdev))
1710 ahci_mcp89_apple_enable(pdev);
1711
1712 /* Promise's PDC42819 is a SAS/SATA controller that has an AHCI mode.
1713 * At the moment, we can only use the AHCI mode. Let the users know
1714 * that for SAS drives they're out of luck.
1715 */
1716 if (pdev->vendor == PCI_VENDOR_ID_PROMISE)
1717 dev_info(&pdev->dev,
1718 "PDC42819 can only drive SATA devices with this driver\n");
1719
1720 /* Some devices use non-standard BARs */
1721 if (pdev->vendor == PCI_VENDOR_ID_STMICRO && pdev->device == 0xCC06)
1722 ahci_pci_bar = AHCI_PCI_BAR_STA2X11;
1723 else if (pdev->vendor == 0x1c44 && pdev->device == 0x8000)
1724 ahci_pci_bar = AHCI_PCI_BAR_ENMOTUS;
1725 else if (pdev->vendor == PCI_VENDOR_ID_CAVIUM) {
1726 if (pdev->device == 0xa01c)
1727 ahci_pci_bar = AHCI_PCI_BAR_CAVIUM;
1728 if (pdev->device == 0xa084)
1729 ahci_pci_bar = AHCI_PCI_BAR_CAVIUM_GEN5;
1730 } else if (pdev->vendor == PCI_VENDOR_ID_LOONGSON) {
1731 if (pdev->device == 0x7a08)
1732 ahci_pci_bar = AHCI_PCI_BAR_LOONGSON;
1733 }
1734
1735 /* acquire resources */
1736 rc = pcim_enable_device(pdev);
1737 if (rc)
1738 return rc;
1739
1740 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
1741 (pdev->device == 0x2652 || pdev->device == 0x2653)) {
1742 u8 map;
1743
1744 /* ICH6s share the same PCI ID for both piix and ahci
1745 * modes. Enabling ahci mode while MAP indicates
1746 * combined mode is a bad idea. Yield to ata_piix.
1747 */
1748 pci_read_config_byte(pdev, ICH_MAP, &map);
1749 if (map & 0x3) {
1750 dev_info(&pdev->dev,
1751 "controller is in combined mode, can't enable AHCI mode\n");
1752 return -ENODEV;
1753 }
1754 }
1755
1756 /* AHCI controllers often implement SFF compatible interface.
1757 * Grab all PCI BARs just in case.
1758 */
1759 rc = pcim_iomap_regions_request_all(pdev, 1 << ahci_pci_bar, DRV_NAME);
1760 if (rc == -EBUSY)
1761 pcim_pin_device(pdev);
1762 if (rc)
1763 return rc;
1764
1765 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
1766 if (!hpriv)
1767 return -ENOMEM;
1768 hpriv->flags |= (unsigned long)pi.private_data;
1769
1770 /* MCP65 revision A1 and A2 can't do MSI */
1771 if (board_id == board_ahci_mcp65 &&
1772 (pdev->revision == 0xa1 || pdev->revision == 0xa2))
1773 hpriv->flags |= AHCI_HFLAG_NO_MSI;
1774
1775 /* SB800 does NOT need the workaround to ignore SERR_INTERNAL */
1776 if (board_id == board_ahci_sb700 && pdev->revision >= 0x40)
1777 hpriv->flags &= ~AHCI_HFLAG_IGN_SERR_INTERNAL;
1778
1779 /* only some SB600s can do 64bit DMA */
1780 if (ahci_sb600_enable_64bit(pdev))
1781 hpriv->flags &= ~AHCI_HFLAG_32BIT_ONLY;
1782
1783 hpriv->mmio = pcim_iomap_table(pdev)[ahci_pci_bar];
1784
1785 /* detect remapped nvme devices */
1786 ahci_remap_check(pdev, ahci_pci_bar, hpriv);
1787
1788 sysfs_add_file_to_group(&pdev->dev.kobj,
1789 &dev_attr_remapped_nvme.attr,
1790 NULL);
1791
1792 /* must set flag prior to save config in order to take effect */
1793 if (ahci_broken_devslp(pdev))
1794 hpriv->flags |= AHCI_HFLAG_NO_DEVSLP;
1795
1796 #ifdef CONFIG_ARM64
1797 if (pdev->vendor == PCI_VENDOR_ID_HUAWEI &&
1798 pdev->device == 0xa235 &&
1799 pdev->revision < 0x30)
1800 hpriv->flags |= AHCI_HFLAG_NO_SXS;
1801
1802 if (pdev->vendor == 0x177d && pdev->device == 0xa01c)
1803 hpriv->irq_handler = ahci_thunderx_irq_handler;
1804 #endif
1805
1806 /* save initial config */
1807 ahci_pci_save_initial_config(pdev, hpriv);
1808
1809 /* prepare host */
1810 if (hpriv->cap & HOST_CAP_NCQ) {
1811 pi.flags |= ATA_FLAG_NCQ;
1812 /*
1813 * Auto-activate optimization is supposed to be
1814 * supported on all AHCI controllers indicating NCQ
1815 * capability, but it seems to be broken on some
1816 * chipsets including NVIDIAs.
1817 */
1818 if (!(hpriv->flags & AHCI_HFLAG_NO_FPDMA_AA))
1819 pi.flags |= ATA_FLAG_FPDMA_AA;
1820
1821 /*
1822 * All AHCI controllers should be forward-compatible
1823 * with the new auxiliary field. This code should be
1824 * conditionalized if any buggy AHCI controllers are
1825 * encountered.
1826 */
1827 pi.flags |= ATA_FLAG_FPDMA_AUX;
1828 }
1829
1830 if (hpriv->cap & HOST_CAP_PMP)
1831 pi.flags |= ATA_FLAG_PMP;
1832
1833 ahci_set_em_messages(hpriv, &pi);
1834
1835 if (ahci_broken_system_poweroff(pdev)) {
1836 pi.flags |= ATA_FLAG_NO_POWEROFF_SPINDOWN;
1837 dev_info(&pdev->dev,
1838 "quirky BIOS, skipping spindown on poweroff\n");
1839 }
1840
1841 if (ahci_broken_lpm(pdev)) {
1842 pi.flags |= ATA_FLAG_NO_LPM;
1843 dev_warn(&pdev->dev,
1844 "BIOS update required for Link Power Management support\n");
1845 }
1846
1847 if (ahci_broken_suspend(pdev)) {
1848 hpriv->flags |= AHCI_HFLAG_NO_SUSPEND;
1849 dev_warn(&pdev->dev,
1850 "BIOS update required for suspend/resume\n");
1851 }
1852
1853 if (ahci_broken_online(pdev)) {
1854 hpriv->flags |= AHCI_HFLAG_SRST_TOUT_IS_OFFLINE;
1855 dev_info(&pdev->dev,
1856 "online status unreliable, applying workaround\n");
1857 }
1858
1859
1860 /* Acer SA5-271 workaround modifies private_data */
1861 acer_sa5_271_workaround(hpriv, pdev);
1862
1863 /* CAP.NP sometimes indicate the index of the last enabled
1864 * port, at other times, that of the last possible port, so
1865 * determining the maximum port number requires looking at
1866 * both CAP.NP and port_map.
1867 */
1868 n_ports = max(ahci_nr_ports(hpriv->cap), fls(hpriv->port_map));
1869
1870 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
1871 if (!host)
1872 return -ENOMEM;
1873 host->private_data = hpriv;
1874
1875 if (ahci_init_msi(pdev, n_ports, hpriv) < 0) {
1876 /* legacy intx interrupts */
1877 pci_intx(pdev, 1);
1878 }
1879 hpriv->irq = pci_irq_vector(pdev, 0);
1880
1881 if (!(hpriv->cap & HOST_CAP_SSS) || ahci_ignore_sss)
1882 host->flags |= ATA_HOST_PARALLEL_SCAN;
1883 else
1884 dev_info(&pdev->dev, "SSS flag set, parallel bus scan disabled\n");
1885
1886 if (!(hpriv->cap & HOST_CAP_PART))
1887 host->flags |= ATA_HOST_NO_PART;
1888
1889 if (!(hpriv->cap & HOST_CAP_SSC))
1890 host->flags |= ATA_HOST_NO_SSC;
1891
1892 if (!(hpriv->cap2 & HOST_CAP2_SDS))
1893 host->flags |= ATA_HOST_NO_DEVSLP;
1894
1895 if (pi.flags & ATA_FLAG_EM)
1896 ahci_reset_em(host);
1897
1898 for (i = 0; i < host->n_ports; i++) {
1899 struct ata_port *ap = host->ports[i];
1900
1901 ata_port_pbar_desc(ap, ahci_pci_bar, -1, "abar");
1902 ata_port_pbar_desc(ap, ahci_pci_bar,
1903 0x100 + ap->port_no * 0x80, "port");
1904
1905 /* set enclosure management message type */
1906 if (ap->flags & ATA_FLAG_EM)
1907 ap->em_message_type = hpriv->em_msg_type;
1908
1909 ahci_update_initial_lpm_policy(ap, hpriv);
1910
1911 /* disabled/not-implemented port */
1912 if (!(hpriv->port_map & (1 << i)))
1913 ap->ops = &ata_dummy_port_ops;
1914 }
1915
1916 /* apply workaround for ASUS P5W DH Deluxe mainboard */
1917 ahci_p5wdh_workaround(host);
1918
1919 /* apply gtf filter quirk */
1920 ahci_gtf_filter_workaround(host);
1921
1922 /* initialize adapter */
1923 rc = ahci_configure_dma_masks(pdev, hpriv->cap & HOST_CAP_64);
1924 if (rc)
1925 return rc;
1926
1927 rc = ahci_pci_reset_controller(host);
1928 if (rc)
1929 return rc;
1930
1931 ahci_pci_init_controller(host);
1932 ahci_pci_print_info(host);
1933
1934 pci_set_master(pdev);
1935
1936 rc = ahci_host_activate(host, &ahci_sht);
1937 if (rc)
1938 return rc;
1939
1940 pm_runtime_put_noidle(&pdev->dev);
1941 return 0;
1942 }
1943
ahci_shutdown_one(struct pci_dev * pdev)1944 static void ahci_shutdown_one(struct pci_dev *pdev)
1945 {
1946 ata_pci_shutdown_one(pdev);
1947 }
1948
ahci_remove_one(struct pci_dev * pdev)1949 static void ahci_remove_one(struct pci_dev *pdev)
1950 {
1951 sysfs_remove_file_from_group(&pdev->dev.kobj,
1952 &dev_attr_remapped_nvme.attr,
1953 NULL);
1954 pm_runtime_get_noresume(&pdev->dev);
1955 ata_pci_remove_one(pdev);
1956 }
1957
1958 module_pci_driver(ahci_pci_driver);
1959
1960 MODULE_AUTHOR("Jeff Garzik");
1961 MODULE_DESCRIPTION("AHCI SATA low-level driver");
1962 MODULE_LICENSE("GPL");
1963 MODULE_DEVICE_TABLE(pci, ahci_pci_tbl);
1964 MODULE_VERSION(DRV_VERSION);
1965
