1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3 * AMD ALSA SoC PCM Driver
4 *
5 * Copyright (C) 2021 Advanced Micro Devices, Inc. All rights reserved.
6 */
7
8 #include "vg_chip_offset_byte.h"
9 #include <sound/pcm.h>
10
11 #define ACP5x_PHY_BASE_ADDRESS 0x1240000
12 #define ACP_DEVICE_ID 0x15E2
13 #define ACP_SOFT_RESET_SOFTRESET_AUDDONE_MASK 0x00010001
14
15 #define ACP_PGFSM_CNTL_POWER_ON_MASK 0x01
16 #define ACP_PGFSM_CNTL_POWER_OFF_MASK 0x00
17 #define ACP_PGFSM_STATUS_MASK 0x03
18 #define ACP_POWERED_ON 0x00
19 #define ACP_POWER_ON_IN_PROGRESS 0x01
20 #define ACP_POWERED_OFF 0x02
21 #define ACP_POWER_OFF_IN_PROGRESS 0x03
22
23 #define ACP_ERR_INTR_MASK 0x20000000
24 #define ACP_EXT_INTR_STAT_CLEAR_MASK 0xFFFFFFFF
25
26 #define ACP5x_DEVS 4
27 #define ACP5x_REG_START 0x1240000
28 #define ACP5x_REG_END 0x1250200
29 #define ACP5x_I2STDM_REG_START 0x1242400
30 #define ACP5x_I2STDM_REG_END 0x1242410
31 #define ACP5x_HS_TDM_REG_START 0x1242814
32 #define ACP5x_HS_TDM_REG_END 0x1242824
33 #define I2S_MODE 0
34 #define ACP5x_I2S_MODE 1
35 #define ACP5x_RES 4
36 #define I2S_RX_THRESHOLD 27
37 #define I2S_TX_THRESHOLD 28
38 #define HS_TX_THRESHOLD 24
39 #define HS_RX_THRESHOLD 23
40
41 #define I2S_SP_INSTANCE 1
42 #define I2S_HS_INSTANCE 2
43
44 #define ACP_SRAM_PTE_OFFSET 0x02050000
45 #define ACP_SRAM_SP_PB_PTE_OFFSET 0x0
46 #define ACP_SRAM_SP_CP_PTE_OFFSET 0x100
47 #define ACP_SRAM_HS_PB_PTE_OFFSET 0x200
48 #define ACP_SRAM_HS_CP_PTE_OFFSET 0x300
49 #define PAGE_SIZE_4K_ENABLE 0x2
50 #define I2S_SP_TX_MEM_WINDOW_START 0x4000000
51 #define I2S_SP_RX_MEM_WINDOW_START 0x4020000
52 #define I2S_HS_TX_MEM_WINDOW_START 0x4040000
53 #define I2S_HS_RX_MEM_WINDOW_START 0x4060000
54
55 #define SP_PB_FIFO_ADDR_OFFSET 0x500
56 #define SP_CAPT_FIFO_ADDR_OFFSET 0x700
57 #define HS_PB_FIFO_ADDR_OFFSET 0x900
58 #define HS_CAPT_FIFO_ADDR_OFFSET 0xB00
59 #define PLAYBACK_MIN_NUM_PERIODS 2
60 #define PLAYBACK_MAX_NUM_PERIODS 8
61 #define PLAYBACK_MAX_PERIOD_SIZE 8192
62 #define PLAYBACK_MIN_PERIOD_SIZE 1024
63 #define CAPTURE_MIN_NUM_PERIODS 2
64 #define CAPTURE_MAX_NUM_PERIODS 8
65 #define CAPTURE_MAX_PERIOD_SIZE 8192
66 #define CAPTURE_MIN_PERIOD_SIZE 1024
67
68 #define MAX_BUFFER (PLAYBACK_MAX_PERIOD_SIZE * PLAYBACK_MAX_NUM_PERIODS)
69 #define MIN_BUFFER MAX_BUFFER
70 #define FIFO_SIZE 0x100
71 #define DMA_SIZE 0x40
72 #define FRM_LEN 0x100
73
74 #define I2S_MASTER_MODE_ENABLE 1
75 #define I2S_MASTER_MODE_DISABLE 0
76
77 #define SLOT_WIDTH_8 8
78 #define SLOT_WIDTH_16 16
79 #define SLOT_WIDTH_24 24
80 #define SLOT_WIDTH_32 32
81 #define TDM_ENABLE 1
82 #define TDM_DISABLE 0
83 #define ACP5x_ITER_IRER_SAMP_LEN_MASK 0x38
84
85 struct i2s_dev_data {
86 bool tdm_mode;
87 bool master_mode;
88 int i2s_irq;
89 u16 i2s_instance;
90 u32 tdm_fmt;
91 void __iomem *acp5x_base;
92 struct snd_pcm_substream *play_stream;
93 struct snd_pcm_substream *capture_stream;
94 struct snd_pcm_substream *i2ssp_play_stream;
95 struct snd_pcm_substream *i2ssp_capture_stream;
96 };
97
98 struct i2s_stream_instance {
99 u16 num_pages;
100 u16 i2s_instance;
101 u16 direction;
102 u16 channels;
103 u32 xfer_resolution;
104 u32 val;
105 dma_addr_t dma_addr;
106 u64 bytescount;
107 void __iomem *acp5x_base;
108 u32 lrclk_div;
109 u32 bclk_div;
110 };
111
112 union acp_dma_count {
113 struct {
114 u32 low;
115 u32 high;
116 } bcount;
117 u64 bytescount;
118 };
119
120 struct acp5x_platform_info {
121 u16 play_i2s_instance;
122 u16 cap_i2s_instance;
123 };
124
125 union acp_i2stdm_mstrclkgen {
126 struct {
127 u32 i2stdm_master_mode : 1;
128 u32 i2stdm_format_mode : 1;
129 u32 i2stdm_lrclk_div_val : 9;
130 u32 i2stdm_bclk_div_val : 11;
131 u32:10;
132 } bitfields, bits;
133 u32 u32_all;
134 };
135
136 /* common header file uses exact offset rather than relative
137 * offset which requires subtraction logic from base_addr
138 * for accessing ACP5x MMIO space registers
139 */
acp_readl(void __iomem * base_addr)140 static inline u32 acp_readl(void __iomem *base_addr)
141 {
142 return readl(base_addr - ACP5x_PHY_BASE_ADDRESS);
143 }
144
acp_writel(u32 val,void __iomem * base_addr)145 static inline void acp_writel(u32 val, void __iomem *base_addr)
146 {
147 writel(val, base_addr - ACP5x_PHY_BASE_ADDRESS);
148 }
149
acp_get_byte_count(struct i2s_stream_instance * rtd,int direction)150 static inline u64 acp_get_byte_count(struct i2s_stream_instance *rtd,
151 int direction)
152 {
153 union acp_dma_count byte_count;
154
155 if (direction == SNDRV_PCM_STREAM_PLAYBACK) {
156 switch (rtd->i2s_instance) {
157 case I2S_HS_INSTANCE:
158 byte_count.bcount.high =
159 acp_readl(rtd->acp5x_base +
160 ACP_HS_TX_LINEARPOSCNTR_HIGH);
161 byte_count.bcount.low =
162 acp_readl(rtd->acp5x_base +
163 ACP_HS_TX_LINEARPOSCNTR_LOW);
164 break;
165 case I2S_SP_INSTANCE:
166 default:
167 byte_count.bcount.high =
168 acp_readl(rtd->acp5x_base +
169 ACP_I2S_TX_LINEARPOSCNTR_HIGH);
170 byte_count.bcount.low =
171 acp_readl(rtd->acp5x_base +
172 ACP_I2S_TX_LINEARPOSCNTR_LOW);
173 }
174 } else {
175 switch (rtd->i2s_instance) {
176 case I2S_HS_INSTANCE:
177 byte_count.bcount.high =
178 acp_readl(rtd->acp5x_base +
179 ACP_HS_RX_LINEARPOSCNTR_HIGH);
180 byte_count.bcount.low =
181 acp_readl(rtd->acp5x_base +
182 ACP_HS_RX_LINEARPOSCNTR_LOW);
183 break;
184 case I2S_SP_INSTANCE:
185 default:
186 byte_count.bcount.high =
187 acp_readl(rtd->acp5x_base +
188 ACP_I2S_RX_LINEARPOSCNTR_HIGH);
189 byte_count.bcount.low =
190 acp_readl(rtd->acp5x_base +
191 ACP_I2S_RX_LINEARPOSCNTR_LOW);
192 }
193 }
194 return byte_count.bytescount;
195 }
196
acp5x_set_i2s_clk(struct i2s_dev_data * adata,struct i2s_stream_instance * rtd)197 static inline void acp5x_set_i2s_clk(struct i2s_dev_data *adata,
198 struct i2s_stream_instance *rtd)
199 {
200 union acp_i2stdm_mstrclkgen mclkgen;
201 u32 master_reg;
202
203 switch (rtd->i2s_instance) {
204 case I2S_HS_INSTANCE:
205 master_reg = ACP_I2STDM2_MSTRCLKGEN;
206 break;
207 case I2S_SP_INSTANCE:
208 default:
209 master_reg = ACP_I2STDM0_MSTRCLKGEN;
210 break;
211 }
212
213 mclkgen.bits.i2stdm_master_mode = 0x1;
214 if (adata->tdm_mode)
215 mclkgen.bits.i2stdm_format_mode = 0x01;
216 else
217 mclkgen.bits.i2stdm_format_mode = 0x00;
218
219 mclkgen.bits.i2stdm_bclk_div_val = rtd->bclk_div;
220 mclkgen.bits.i2stdm_lrclk_div_val = rtd->lrclk_div;
221 acp_writel(mclkgen.u32_all, rtd->acp5x_base + master_reg);
222 }
223
