1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd 4 */ 5 6#include <dt-bindings/clock/rk3328-cru.h> 7#include <dt-bindings/gpio/gpio.h> 8#include <dt-bindings/interrupt-controller/arm-gic.h> 9#include <dt-bindings/interrupt-controller/irq.h> 10#include <dt-bindings/pinctrl/rockchip.h> 11#include <dt-bindings/power/rk3328-power.h> 12#include <dt-bindings/soc/rockchip,boot-mode.h> 13#include <dt-bindings/thermal/thermal.h> 14 15/ { 16 compatible = "rockchip,rk3328"; 17 18 interrupt-parent = <&gic>; 19 #address-cells = <2>; 20 #size-cells = <2>; 21 22 aliases { 23 serial0 = &uart0; 24 serial1 = &uart1; 25 serial2 = &uart2; 26 i2c0 = &i2c0; 27 i2c1 = &i2c1; 28 i2c2 = &i2c2; 29 i2c3 = &i2c3; 30 ethernet0 = &gmac2io; 31 ethernet1 = &gmac2phy; 32 }; 33 34 cpus { 35 #address-cells = <2>; 36 #size-cells = <0>; 37 38 cpu0: cpu@0 { 39 device_type = "cpu"; 40 compatible = "arm,cortex-a53"; 41 reg = <0x0 0x0>; 42 clocks = <&cru ARMCLK>; 43 #cooling-cells = <2>; 44 dynamic-power-coefficient = <120>; 45 enable-method = "psci"; 46 next-level-cache = <&l2>; 47 operating-points-v2 = <&cpu0_opp_table>; 48 }; 49 50 cpu1: cpu@1 { 51 device_type = "cpu"; 52 compatible = "arm,cortex-a53"; 53 reg = <0x0 0x1>; 54 clocks = <&cru ARMCLK>; 55 #cooling-cells = <2>; 56 dynamic-power-coefficient = <120>; 57 enable-method = "psci"; 58 next-level-cache = <&l2>; 59 operating-points-v2 = <&cpu0_opp_table>; 60 }; 61 62 cpu2: cpu@2 { 63 device_type = "cpu"; 64 compatible = "arm,cortex-a53"; 65 reg = <0x0 0x2>; 66 clocks = <&cru ARMCLK>; 67 #cooling-cells = <2>; 68 dynamic-power-coefficient = <120>; 69 enable-method = "psci"; 70 next-level-cache = <&l2>; 71 operating-points-v2 = <&cpu0_opp_table>; 72 }; 73 74 cpu3: cpu@3 { 75 device_type = "cpu"; 76 compatible = "arm,cortex-a53"; 77 reg = <0x0 0x3>; 78 clocks = <&cru ARMCLK>; 79 #cooling-cells = <2>; 80 dynamic-power-coefficient = <120>; 81 enable-method = "psci"; 82 next-level-cache = <&l2>; 83 operating-points-v2 = <&cpu0_opp_table>; 84 }; 85 86 l2: l2-cache0 { 87 compatible = "cache"; 88 }; 89 }; 90 91 cpu0_opp_table: opp_table0 { 92 compatible = "operating-points-v2"; 93 opp-shared; 94 95 opp-408000000 { 96 opp-hz = /bits/ 64 <408000000>; 97 opp-microvolt = <950000>; 98 clock-latency-ns = <40000>; 99 opp-suspend; 100 }; 101 opp-600000000 { 102 opp-hz = /bits/ 64 <600000000>; 103 opp-microvolt = <950000>; 104 clock-latency-ns = <40000>; 105 }; 106 opp-816000000 { 107 opp-hz = /bits/ 64 <816000000>; 108 opp-microvolt = <1000000>; 109 clock-latency-ns = <40000>; 110 }; 111 opp-1008000000 { 112 opp-hz = /bits/ 64 <1008000000>; 113 opp-microvolt = <1100000>; 114 clock-latency-ns = <40000>; 115 }; 116 opp-1200000000 { 117 opp-hz = /bits/ 64 <1200000000>; 118 opp-microvolt = <1225000>; 119 clock-latency-ns = <40000>; 120 }; 121 opp-1296000000 { 122 opp-hz = /bits/ 64 <1296000000>; 123 opp-microvolt = <1300000>; 124 clock-latency-ns = <40000>; 125 }; 126 }; 127 128 amba { 129 compatible = "simple-bus"; 130 #address-cells = <2>; 131 #size-cells = <2>; 132 ranges; 133 134 dmac: dmac@ff1f0000 { 135 compatible = "arm,pl330", "arm,primecell"; 136 reg = <0x0 0xff1f0000 0x0 0x4000>; 137 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 138 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 139 clocks = <&cru ACLK_DMAC>; 140 clock-names = "apb_pclk"; 141 #dma-cells = <1>; 142 }; 143 }; 144 145 arm-pmu { 146 compatible = "arm,cortex-a53-pmu"; 147 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 148 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 149 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 150 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 151 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 152 }; 153 154 display_subsystem: display-subsystem { 155 compatible = "rockchip,display-subsystem"; 156 ports = <&vop_out>; 157 }; 158 159 psci { 160 compatible = "arm,psci-1.0", "arm,psci-0.2"; 161 method = "smc"; 162 }; 163 164 timer { 165 compatible = "arm,armv8-timer"; 166 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 167 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 168 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 169 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 170 }; 171 172 xin24m: xin24m { 173 compatible = "fixed-clock"; 174 #clock-cells = <0>; 175 clock-frequency = <24000000>; 176 clock-output-names = "xin24m"; 177 }; 178 179 i2s0: i2s@ff000000 { 180 compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s"; 181 reg = <0x0 0xff000000 0x0 0x1000>; 182 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 183 clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0_8CH>; 184 clock-names = "i2s_clk", "i2s_hclk"; 185 dmas = <&dmac 11>, <&dmac 12>; 186 dma-names = "tx", "rx"; 187 #sound-dai-cells = <0>; 188 status = "disabled"; 189 }; 190 191 i2s1: i2s@ff010000 { 192 compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s"; 193 reg = <0x0 0xff010000 0x0 0x1000>; 194 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 195 clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1_8CH>; 196 clock-names = "i2s_clk", "i2s_hclk"; 197 dmas = <&dmac 14>, <&dmac 15>; 198 dma-names = "tx", "rx"; 199 #sound-dai-cells = <0>; 200 status = "disabled"; 201 }; 202 203 i2s2: i2s@ff020000 { 204 compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s"; 205 reg = <0x0 0xff020000 0x0 0x1000>; 206 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 207 clocks = <&cru SCLK_I2S2>, <&cru HCLK_I2S2_2CH>; 208 clock-names = "i2s_clk", "i2s_hclk"; 209 dmas = <&dmac 0>, <&dmac 1>; 210 dma-names = "tx", "rx"; 211 #sound-dai-cells = <0>; 212 status = "disabled"; 213 }; 214 215 spdif: spdif@ff030000 { 216 compatible = "rockchip,rk3328-spdif"; 217 reg = <0x0 0xff030000 0x0 0x1000>; 218 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 219 clocks = <&cru SCLK_SPDIF>, <&cru HCLK_SPDIF_8CH>; 220 clock-names = "mclk", "hclk"; 221 dmas = <&dmac 10>; 222 dma-names = "tx"; 223 pinctrl-names = "default"; 224 pinctrl-0 = <&spdifm2_tx>; 225 #sound-dai-cells = <0>; 226 status = "disabled"; 227 }; 228 229 pdm: pdm@ff040000 { 230 compatible = "rockchip,pdm"; 231 reg = <0x0 0xff040000 0x0 0x1000>; 232 clocks = <&cru SCLK_PDM>, <&cru HCLK_PDM>; 233 clock-names = "pdm_clk", "pdm_hclk"; 234 dmas = <&dmac 16>; 235 dma-names = "rx"; 236 pinctrl-names = "default", "sleep"; 237 pinctrl-0 = <&pdmm0_clk 238 &pdmm0_sdi0 239 &pdmm0_sdi1 240 &pdmm0_sdi2 241 &pdmm0_sdi3>; 242 pinctrl-1 = <&pdmm0_clk_sleep 243 &pdmm0_sdi0_sleep 244 &pdmm0_sdi1_sleep 245 &pdmm0_sdi2_sleep 246 &pdmm0_sdi3_sleep>; 247 status = "disabled"; 248 }; 249 250 grf: syscon@ff100000 { 251 compatible = "rockchip,rk3328-grf", "syscon", "simple-mfd"; 252 reg = <0x0 0xff100000 0x0 0x1000>; 253 #address-cells = <1>; 254 #size-cells = <1>; 255 256 io_domains: io-domains { 257 compatible = "rockchip,rk3328-io-voltage-domain"; 258 status = "disabled"; 259 }; 260 261 grf_gpio: grf-gpio { 262 compatible = "rockchip,rk3328-grf-gpio"; 263 gpio-controller; 264 #gpio-cells = <2>; 265 }; 266 267 power: power-controller { 268 compatible = "rockchip,rk3328-power-controller"; 269 #power-domain-cells = <1>; 270 #address-cells = <1>; 271 #size-cells = <0>; 272 273 pd_hevc@RK3328_PD_HEVC { 274 reg = <RK3328_PD_HEVC>; 275 }; 276 pd_video@RK3328_PD_VIDEO { 277 reg = <RK3328_PD_VIDEO>; 278 }; 279 pd_vpu@RK3328_PD_VPU { 280 reg = <RK3328_PD_VPU>; 281 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; 282 }; 283 }; 284 285 reboot-mode { 286 compatible = "syscon-reboot-mode"; 287 offset = <0x5c8>; 288 mode-normal = <BOOT_NORMAL>; 289 mode-recovery = <BOOT_RECOVERY>; 290 mode-bootloader = <BOOT_FASTBOOT>; 291 mode-loader = <BOOT_BL_DOWNLOAD>; 292 }; 293 }; 294 295 uart0: serial@ff110000 { 296 compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart"; 297 reg = <0x0 0xff110000 0x0 0x100>; 298 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; 299 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; 300 clock-names = "baudclk", "apb_pclk"; 301 dmas = <&dmac 2>, <&dmac 3>; 302 dma-names = "tx", "rx"; 303 pinctrl-names = "default"; 304 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; 305 reg-io-width = <4>; 306 reg-shift = <2>; 307 status = "disabled"; 308 }; 309 310 uart1: serial@ff120000 { 311 compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart"; 312 reg = <0x0 0xff120000 0x0 0x100>; 313 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; 314 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; 315 clock-names = "baudclk", "apb_pclk"; 316 dmas = <&dmac 4>, <&dmac 5>; 317 dma-names = "tx", "rx"; 318 pinctrl-names = "default"; 319 pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>; 320 reg-io-width = <4>; 321 reg-shift = <2>; 322 status = "disabled"; 323 }; 324 325 uart2: serial@ff130000 { 326 compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart"; 327 reg = <0x0 0xff130000 0x0 0x100>; 328 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; 329 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; 330 clock-names = "baudclk", "apb_pclk"; 331 dmas = <&dmac 6>, <&dmac 7>; 332 dma-names = "tx", "rx"; 333 pinctrl-names = "default"; 334 pinctrl-0 = <&uart2m1_xfer>; 335 reg-io-width = <4>; 336 reg-shift = <2>; 337 status = "disabled"; 338 }; 339 340 i2c0: i2c@ff150000 { 341 compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c"; 342 reg = <0x0 0xff150000 0x0 0x1000>; 343 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 344 #address-cells = <1>; 345 #size-cells = <0>; 346 clocks = <&cru SCLK_I2C0>, <&cru PCLK_I2C0>; 347 clock-names = "i2c", "pclk"; 348 pinctrl-names = "default"; 349 pinctrl-0 = <&i2c0_xfer>; 350 status = "disabled"; 351 }; 352 353 i2c1: i2c@ff160000 { 354 compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c"; 355 reg = <0x0 0xff160000 0x0 0x1000>; 356 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 357 #address-cells = <1>; 358 #size-cells = <0>; 359 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>; 360 clock-names = "i2c", "pclk"; 361 pinctrl-names = "default"; 362 pinctrl-0 = <&i2c1_xfer>; 363 status = "disabled"; 364 }; 365 366 i2c2: i2c@ff170000 { 367 compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c"; 368 reg = <0x0 0xff170000 0x0 0x1000>; 369 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 370 #address-cells = <1>; 371 #size-cells = <0>; 372 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>; 373 clock-names = "i2c", "pclk"; 374 pinctrl-names = "default"; 375 pinctrl-0 = <&i2c2_xfer>; 376 status = "disabled"; 377 }; 378 379 i2c3: i2c@ff180000 { 380 compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c"; 381 reg = <0x0 0xff180000 0x0 0x1000>; 382 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 383 #address-cells = <1>; 384 #size-cells = <0>; 385 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>; 386 clock-names = "i2c", "pclk"; 387 pinctrl-names = "default"; 388 pinctrl-0 = <&i2c3_xfer>; 389 status = "disabled"; 390 }; 391 392 spi0: spi@ff190000 { 393 compatible = "rockchip,rk3328-spi", "rockchip,rk3066-spi"; 394 reg = <0x0 0xff190000 0x0 0x1000>; 395 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 396 #address-cells = <1>; 397 #size-cells = <0>; 398 clocks = <&cru SCLK_SPI>, <&cru PCLK_SPI>; 399 clock-names = "spiclk", "apb_pclk"; 400 dmas = <&dmac 8>, <&dmac 9>; 401 dma-names = "tx", "rx"; 402 pinctrl-names = "default"; 403 pinctrl-0 = <&spi0m2_clk &spi0m2_tx &spi0m2_rx &spi0m2_cs0>; 404 status = "disabled"; 405 }; 406 407 wdt: watchdog@ff1a0000 { 408 compatible = "snps,dw-wdt"; 409 reg = <0x0 0xff1a0000 0x0 0x100>; 410 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 411 clocks = <&cru PCLK_WDT>; 412 }; 413 414 pwm0: pwm@ff1b0000 { 415 compatible = "rockchip,rk3328-pwm"; 416 reg = <0x0 0xff1b0000 0x0 0x10>; 417 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>; 418 clock-names = "pwm", "pclk"; 419 pinctrl-names = "default"; 420 pinctrl-0 = <&pwm0_pin>; 421 #pwm-cells = <3>; 422 status = "disabled"; 423 }; 424 425 pwm1: pwm@ff1b0010 { 426 compatible = "rockchip,rk3328-pwm"; 427 reg = <0x0 0xff1b0010 0x0 0x10>; 428 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>; 429 clock-names = "pwm", "pclk"; 430 pinctrl-names = "default"; 431 pinctrl-0 = <&pwm1_pin>; 432 #pwm-cells = <3>; 433 status = "disabled"; 434 }; 435 436 pwm2: pwm@ff1b0020 { 437 compatible = "rockchip,rk3328-pwm"; 438 reg = <0x0 0xff1b0020 0x0 0x10>; 439 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>; 440 clock-names = "pwm", "pclk"; 441 pinctrl-names = "default"; 442 pinctrl-0 = <&pwm2_pin>; 443 #pwm-cells = <3>; 444 status = "disabled"; 445 }; 446 447 pwm3: pwm@ff1b0030 { 448 compatible = "rockchip,rk3328-pwm"; 449 reg = <0x0 0xff1b0030 0x0 0x10>; 450 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 451 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>; 452 clock-names = "pwm", "pclk"; 453 pinctrl-names = "default"; 454 pinctrl-0 = <&pwmir_pin>; 455 #pwm-cells = <3>; 456 status = "disabled"; 457 }; 458 459 thermal-zones { 460 soc_thermal: soc-thermal { 461 polling-delay-passive = <20>; 462 polling-delay = <1000>; 463 sustainable-power = <1000>; 464 465 thermal-sensors = <&tsadc 0>; 466 467 trips { 468 threshold: trip-point0 { 469 temperature = <70000>; 470 hysteresis = <2000>; 471 type = "passive"; 472 }; 473 target: trip-point1 { 474 temperature = <85000>; 475 hysteresis = <2000>; 476 type = "passive"; 477 }; 478 soc_crit: soc-crit { 479 temperature = <95000>; 480 hysteresis = <2000>; 481 type = "critical"; 482 }; 483 }; 484 485 cooling-maps { 486 map0 { 487 trip = <&target>; 488 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 489 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 490 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 491 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 492 contribution = <4096>; 493 }; 494 }; 495 }; 496 497 }; 498 499 tsadc: tsadc@ff250000 { 500 compatible = "rockchip,rk3328-tsadc"; 501 reg = <0x0 0xff250000 0x0 0x100>; 502 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; 503 assigned-clocks = <&cru SCLK_TSADC>; 504 assigned-clock-rates = <50000>; 505 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>; 506 clock-names = "tsadc", "apb_pclk"; 507 pinctrl-names = "init", "default", "sleep"; 508 pinctrl-0 = <&otp_gpio>; 509 pinctrl-1 = <&otp_out>; 510 pinctrl-2 = <&otp_gpio>; 511 resets = <&cru SRST_TSADC>; 512 reset-names = "tsadc-apb"; 513 rockchip,grf = <&grf>; 514 rockchip,hw-tshut-temp = <100000>; 515 #thermal-sensor-cells = <1>; 516 status = "disabled"; 517 }; 518 519 efuse: efuse@ff260000 { 520 compatible = "rockchip,rk3328-efuse"; 521 reg = <0x0 0xff260000 0x0 0x50>; 522 #address-cells = <1>; 523 #size-cells = <1>; 524 clocks = <&cru SCLK_EFUSE>; 525 clock-names = "pclk_efuse"; 526 rockchip,efuse-size = <0x20>; 527 528 /* Data cells */ 529 efuse_id: id@7 { 530 reg = <0x07 0x10>; 531 }; 532 cpu_leakage: cpu-leakage@17 { 533 reg = <0x17 0x1>; 534 }; 535 logic_leakage: logic-leakage@19 { 536 reg = <0x19 0x1>; 537 }; 538 efuse_cpu_version: cpu-version@1a { 539 reg = <0x1a 0x1>; 540 bits = <3 3>; 541 }; 542 }; 543 544 saradc: adc@ff280000 { 545 compatible = "rockchip,rk3328-saradc", "rockchip,rk3399-saradc"; 546 reg = <0x0 0xff280000 0x0 0x100>; 547 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; 548 #io-channel-cells = <1>; 549 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>; 550 clock-names = "saradc", "apb_pclk"; 551 resets = <&cru SRST_SARADC_P>; 552 reset-names = "saradc-apb"; 553 status = "disabled"; 554 }; 555 556 gpu: gpu@ff300000 { 557 compatible = "rockchip,rk3328-mali", "arm,mali-450"; 558 reg = <0x0 0xff300000 0x0 0x40000>; 559 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>, 560 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, 561 <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>, 562 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, 563 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, 564 <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>, 565 <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; 566 interrupt-names = "gp", 567 "gpmmu", 568 "pp", 569 "pp0", 570 "ppmmu0", 571 "pp1", 572 "ppmmu1"; 573 clocks = <&cru ACLK_GPU>, <&cru ACLK_GPU>; 574 clock-names = "bus", "core"; 575 resets = <&cru SRST_GPU_A>; 576 }; 577 578 h265e_mmu: iommu@ff330200 { 579 compatible = "rockchip,iommu"; 580 reg = <0x0 0xff330200 0 0x100>; 581 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 582 interrupt-names = "h265e_mmu"; 583 clocks = <&cru ACLK_H265>, <&cru PCLK_H265>; 584 clock-names = "aclk", "iface"; 585 #iommu-cells = <0>; 586 status = "disabled"; 587 }; 588 589 vepu_mmu: iommu@ff340800 { 590 compatible = "rockchip,iommu"; 591 reg = <0x0 0xff340800 0x0 0x40>; 592 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 593 interrupt-names = "vepu_mmu"; 594 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; 595 clock-names = "aclk", "iface"; 596 #iommu-cells = <0>; 597 status = "disabled"; 598 }; 599 600 vpu: video-codec@ff350000 { 601 compatible = "rockchip,rk3328-vpu"; 602 reg = <0x0 0xff350000 0x0 0x800>; 603 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 604 interrupt-names = "vdpu"; 605 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; 606 clock-names = "aclk", "hclk"; 607 iommus = <&vpu_mmu>; 608 power-domains = <&power RK3328_PD_VPU>; 609 }; 610 611 vpu_mmu: iommu@ff350800 { 612 compatible = "rockchip,iommu"; 613 reg = <0x0 0xff350800 0x0 0x40>; 614 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 615 interrupt-names = "vpu_mmu"; 616 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; 617 clock-names = "aclk", "iface"; 618 #iommu-cells = <0>; 619 power-domains = <&power RK3328_PD_VPU>; 620 }; 621 622 rkvdec_mmu: iommu@ff360480 { 623 compatible = "rockchip,iommu"; 624 reg = <0x0 0xff360480 0x0 0x40>, <0x0 0xff3604c0 0x0 0x40>; 625 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 626 interrupt-names = "rkvdec_mmu"; 627 clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>; 628 clock-names = "aclk", "iface"; 629 #iommu-cells = <0>; 630 status = "disabled"; 631 }; 632 633 vop: vop@ff370000 { 634 compatible = "rockchip,rk3328-vop"; 635 reg = <0x0 0xff370000 0x0 0x3efc>; 636 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 637 clocks = <&cru ACLK_VOP>, <&cru DCLK_LCDC>, <&cru HCLK_VOP>; 638 clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; 639 resets = <&cru SRST_VOP_A>, <&cru SRST_VOP_H>, <&cru SRST_VOP_D>; 640 reset-names = "axi", "ahb", "dclk"; 641 iommus = <&vop_mmu>; 642 status = "disabled"; 643 644 vop_out: port { 645 #address-cells = <1>; 646 #size-cells = <0>; 647 648 vop_out_hdmi: endpoint@0 { 649 reg = <0>; 650 remote-endpoint = <&hdmi_in_vop>; 651 }; 652 }; 653 }; 654 655 vop_mmu: iommu@ff373f00 { 656 compatible = "rockchip,iommu"; 657 reg = <0x0 0xff373f00 0x0 0x100>; 658 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 659 interrupt-names = "vop_mmu"; 660 clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>; 661 clock-names = "aclk", "iface"; 662 #iommu-cells = <0>; 663 status = "disabled"; 664 }; 665 666 hdmi: hdmi@ff3c0000 { 667 compatible = "rockchip,rk3328-dw-hdmi"; 668 reg = <0x0 0xff3c0000 0x0 0x20000>; 669 reg-io-width = <4>; 670 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, 671 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 672 clocks = <&cru PCLK_HDMI>, 673 <&cru SCLK_HDMI_SFC>, 674 <&cru SCLK_RTC32K>; 675 clock-names = "iahb", 676 "isfr", 677 "cec"; 678 phys = <&hdmiphy>; 679 phy-names = "hdmi"; 680 pinctrl-names = "default"; 681 pinctrl-0 = <&hdmi_cec &hdmii2c_xfer &hdmi_hpd>; 682 rockchip,grf = <&grf>; 683 #sound-dai-cells = <0>; 684 status = "disabled"; 685 686 ports { 687 hdmi_in: port { 688 hdmi_in_vop: endpoint { 689 remote-endpoint = <&vop_out_hdmi>; 690 }; 691 }; 692 }; 693 }; 694 695 codec: codec@ff410000 { 696 compatible = "rockchip,rk3328-codec"; 697 reg = <0x0 0xff410000 0x0 0x1000>; 698 clocks = <&cru PCLK_ACODECPHY>, <&cru SCLK_I2S1>; 699 clock-names = "pclk", "mclk"; 700 rockchip,grf = <&grf>; 701 #sound-dai-cells = <0>; 702 status = "disabled"; 703 }; 704 705 hdmiphy: phy@ff430000 { 706 compatible = "rockchip,rk3328-hdmi-phy"; 707 reg = <0x0 0xff430000 0x0 0x10000>; 708 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 709 clocks = <&cru PCLK_HDMIPHY>, <&xin24m>, <&cru DCLK_HDMIPHY>; 710 clock-names = "sysclk", "refoclk", "refpclk"; 711 clock-output-names = "hdmi_phy"; 712 #clock-cells = <0>; 713 nvmem-cells = <&efuse_cpu_version>; 714 nvmem-cell-names = "cpu-version"; 715 #phy-cells = <0>; 716 status = "disabled"; 717 }; 718 719 cru: clock-controller@ff440000 { 720 compatible = "rockchip,rk3328-cru", "rockchip,cru", "syscon"; 721 reg = <0x0 0xff440000 0x0 0x1000>; 722 rockchip,grf = <&grf>; 723 #clock-cells = <1>; 724 #reset-cells = <1>; 725 assigned-clocks = 726 /* 727 * CPLL should run at 1200, but that is to high for 728 * the initial dividers of most of its children. 729 * We need set cpll child clk div first, 730 * and then set the cpll frequency. 731 */ 732 <&cru DCLK_LCDC>, <&cru SCLK_PDM>, 733 <&cru SCLK_RTC32K>, <&cru SCLK_UART0>, 734 <&cru SCLK_UART1>, <&cru SCLK_UART2>, 735 <&cru ACLK_BUS_PRE>, <&cru ACLK_PERI_PRE>, 736 <&cru ACLK_VIO_PRE>, <&cru ACLK_RGA_PRE>, 737 <&cru ACLK_VOP_PRE>, <&cru ACLK_RKVDEC_PRE>, 738 <&cru ACLK_RKVENC>, <&cru ACLK_VPU_PRE>, 739 <&cru SCLK_VDEC_CABAC>, <&cru SCLK_VDEC_CORE>, 740 <&cru SCLK_VENC_CORE>, <&cru SCLK_VENC_DSP>, 741 <&cru SCLK_SDIO>, <&cru SCLK_TSP>, 742 <&cru SCLK_WIFI>, <&cru ARMCLK>, 743 <&cru PLL_GPLL>, <&cru PLL_CPLL>, 744 <&cru ACLK_BUS_PRE>, <&cru HCLK_BUS_PRE>, 745 <&cru PCLK_BUS_PRE>, <&cru ACLK_PERI_PRE>, 746 <&cru HCLK_PERI>, <&cru PCLK_PERI>, 747 <&cru SCLK_RTC32K>; 748 assigned-clock-parents = 749 <&cru HDMIPHY>, <&cru PLL_APLL>, 750 <&cru PLL_GPLL>, <&xin24m>, 751 <&xin24m>, <&xin24m>; 752 assigned-clock-rates = 753 <0>, <61440000>, 754 <0>, <24000000>, 755 <24000000>, <24000000>, 756 <15000000>, <15000000>, 757 <100000000>, <100000000>, 758 <100000000>, <100000000>, 759 <50000000>, <100000000>, 760 <100000000>, <100000000>, 761 <50000000>, <50000000>, 762 <50000000>, <50000000>, 763 <24000000>, <600000000>, 764 <491520000>, <1200000000>, 765 <150000000>, <75000000>, 766 <75000000>, <150000000>, 767 <75000000>, <75000000>, 768 <32768>; 769 }; 770 771 usb2phy_grf: syscon@ff450000 { 772 compatible = "rockchip,rk3328-usb2phy-grf", "syscon", 773 "simple-mfd"; 774 reg = <0x0 0xff450000 0x0 0x10000>; 775 #address-cells = <1>; 776 #size-cells = <1>; 777 778 u2phy: usb2-phy@100 { 779 compatible = "rockchip,rk3328-usb2phy"; 780 reg = <0x100 0x10>; 781 clocks = <&xin24m>; 782 clock-names = "phyclk"; 783 clock-output-names = "usb480m_phy"; 784 #clock-cells = <0>; 785 assigned-clocks = <&cru USB480M>; 786 assigned-clock-parents = <&u2phy>; 787 status = "disabled"; 788 789 u2phy_otg: otg-port { 790 #phy-cells = <0>; 791 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, 792 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>, 793 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 794 interrupt-names = "otg-bvalid", "otg-id", 795 "linestate"; 796 status = "disabled"; 797 }; 798 799 u2phy_host: host-port { 800 #phy-cells = <0>; 801 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 802 interrupt-names = "linestate"; 803 status = "disabled"; 804 }; 805 }; 806 }; 807 808 sdmmc: dwmmc@ff500000 { 809 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc"; 810 reg = <0x0 0xff500000 0x0 0x4000>; 811 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 812 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, 813 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; 814 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 815 fifo-depth = <0x100>; 816 max-frequency = <150000000>; 817 status = "disabled"; 818 }; 819 820 sdio: dwmmc@ff510000 { 821 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc"; 822 reg = <0x0 0xff510000 0x0 0x4000>; 823 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 824 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>, 825 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; 826 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 827 fifo-depth = <0x100>; 828 max-frequency = <150000000>; 829 status = "disabled"; 830 }; 831 832 emmc: dwmmc@ff520000 { 833 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc"; 834 reg = <0x0 0xff520000 0x0 0x4000>; 835 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 836 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>, 837 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; 838 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 839 fifo-depth = <0x100>; 840 max-frequency = <150000000>; 841 status = "disabled"; 842 }; 843 844 gmac2io: ethernet@ff540000 { 845 compatible = "rockchip,rk3328-gmac"; 846 reg = <0x0 0xff540000 0x0 0x10000>; 847 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 848 interrupt-names = "macirq"; 849 clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_RX>, 850 <&cru SCLK_MAC2IO_TX>, <&cru SCLK_MAC2IO_REF>, 851 <&cru SCLK_MAC2IO_REFOUT>, <&cru ACLK_MAC2IO>, 852 <&cru PCLK_MAC2IO>; 853 clock-names = "stmmaceth", "mac_clk_rx", 854 "mac_clk_tx", "clk_mac_ref", 855 "clk_mac_refout", "aclk_mac", 856 "pclk_mac"; 857 resets = <&cru SRST_GMAC2IO_A>; 858 reset-names = "stmmaceth"; 859 rockchip,grf = <&grf>; 860 status = "disabled"; 861 }; 862 863 gmac2phy: ethernet@ff550000 { 864 compatible = "rockchip,rk3328-gmac"; 865 reg = <0x0 0xff550000 0x0 0x10000>; 866 rockchip,grf = <&grf>; 867 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 868 interrupt-names = "macirq"; 869 clocks = <&cru SCLK_MAC2PHY_SRC>, <&cru SCLK_MAC2PHY_RXTX>, 870 <&cru SCLK_MAC2PHY_RXTX>, <&cru SCLK_MAC2PHY_REF>, 871 <&cru ACLK_MAC2PHY>, <&cru PCLK_MAC2PHY>, 872 <&cru SCLK_MAC2PHY_OUT>; 873 clock-names = "stmmaceth", "mac_clk_rx", 874 "mac_clk_tx", "clk_mac_ref", 875 "aclk_mac", "pclk_mac", 876 "clk_macphy"; 877 resets = <&cru SRST_GMAC2PHY_A>, <&cru SRST_MACPHY>; 878 reset-names = "stmmaceth", "mac-phy"; 879 phy-mode = "rmii"; 880 phy-handle = <&phy>; 881 status = "disabled"; 882 883 mdio { 884 compatible = "snps,dwmac-mdio"; 885 #address-cells = <1>; 886 #size-cells = <0>; 887 888 phy: phy@0 { 889 compatible = "ethernet-phy-id1234.d400", "ethernet-phy-ieee802.3-c22"; 890 reg = <0>; 891 clocks = <&cru SCLK_MAC2PHY_OUT>; 892 resets = <&cru SRST_MACPHY>; 893 pinctrl-names = "default"; 894 pinctrl-0 = <&fephyled_rxm1 &fephyled_linkm1>; 895 phy-is-integrated; 896 }; 897 }; 898 }; 899 900 usb20_otg: usb@ff580000 { 901 compatible = "rockchip,rk3328-usb", "rockchip,rk3066-usb", 902 "snps,dwc2"; 903 reg = <0x0 0xff580000 0x0 0x40000>; 904 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 905 clocks = <&cru HCLK_OTG>; 906 clock-names = "otg"; 907 dr_mode = "otg"; 908 g-np-tx-fifo-size = <16>; 909 g-rx-fifo-size = <280>; 910 g-tx-fifo-size = <256 128 128 64 32 16>; 911 g-use-dma; 912 phys = <&u2phy_otg>; 913 phy-names = "usb2-phy"; 914 status = "disabled"; 915 }; 916 917 usb_host0_ehci: usb@ff5c0000 { 918 compatible = "generic-ehci"; 919 reg = <0x0 0xff5c0000 0x0 0x10000>; 920 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 921 clocks = <&cru HCLK_HOST0>, <&u2phy>; 922 clock-names = "usbhost", "utmi"; 923 phys = <&u2phy_host>; 924 phy-names = "usb"; 925 status = "disabled"; 926 }; 927 928 usb_host0_ohci: usb@ff5d0000 { 929 compatible = "generic-ohci"; 930 reg = <0x0 0xff5d0000 0x0 0x10000>; 931 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 932 clocks = <&cru HCLK_HOST0>, <&u2phy>; 933 clock-names = "usbhost", "utmi"; 934 phys = <&u2phy_host>; 935 phy-names = "usb"; 936 status = "disabled"; 937 }; 938 939 gic: interrupt-controller@ff811000 { 940 compatible = "arm,gic-400"; 941 #interrupt-cells = <3>; 942 #address-cells = <0>; 943 interrupt-controller; 944 reg = <0x0 0xff811000 0 0x1000>, 945 <0x0 0xff812000 0 0x2000>, 946 <0x0 0xff814000 0 0x2000>, 947 <0x0 0xff816000 0 0x2000>; 948 interrupts = <GIC_PPI 9 949 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 950 }; 951 952 pinctrl: pinctrl { 953 compatible = "rockchip,rk3328-pinctrl"; 954 rockchip,grf = <&grf>; 955 #address-cells = <2>; 956 #size-cells = <2>; 957 ranges; 958 959 gpio0: gpio0@ff210000 { 960 compatible = "rockchip,gpio-bank"; 961 reg = <0x0 0xff210000 0x0 0x100>; 962 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 963 clocks = <&cru PCLK_GPIO0>; 964 965 gpio-controller; 966 #gpio-cells = <2>; 967 968 interrupt-controller; 969 #interrupt-cells = <2>; 970 }; 971 972 gpio1: gpio1@ff220000 { 973 compatible = "rockchip,gpio-bank"; 974 reg = <0x0 0xff220000 0x0 0x100>; 975 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 976 clocks = <&cru PCLK_GPIO1>; 977 978 gpio-controller; 979 #gpio-cells = <2>; 980 981 interrupt-controller; 982 #interrupt-cells = <2>; 983 }; 984 985 gpio2: gpio2@ff230000 { 986 compatible = "rockchip,gpio-bank"; 987 reg = <0x0 0xff230000 0x0 0x100>; 988 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 989 clocks = <&cru PCLK_GPIO2>; 990 991 gpio-controller; 992 #gpio-cells = <2>; 993 994 interrupt-controller; 995 #interrupt-cells = <2>; 996 }; 997 998 gpio3: gpio3@ff240000 { 999 compatible = "rockchip,gpio-bank"; 1000 reg = <0x0 0xff240000 0x0 0x100>; 1001 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; 1002 clocks = <&cru PCLK_GPIO3>; 1003 1004 gpio-controller; 1005 #gpio-cells = <2>; 1006 1007 interrupt-controller; 1008 #interrupt-cells = <2>; 1009 }; 1010 1011 pcfg_pull_up: pcfg-pull-up { 1012 bias-pull-up; 1013 }; 1014 1015 pcfg_pull_down: pcfg-pull-down { 1016 bias-pull-down; 1017 }; 1018 1019 pcfg_pull_none: pcfg-pull-none { 1020 bias-disable; 1021 }; 1022 1023 pcfg_pull_none_2ma: pcfg-pull-none-2ma { 1024 bias-disable; 1025 drive-strength = <2>; 1026 }; 1027 1028 pcfg_pull_up_2ma: pcfg-pull-up-2ma { 1029 bias-pull-up; 1030 drive-strength = <2>; 1031 }; 1032 1033 pcfg_pull_up_4ma: pcfg-pull-up-4ma { 1034 bias-pull-up; 1035 drive-strength = <4>; 1036 }; 1037 1038 pcfg_pull_none_4ma: pcfg-pull-none-4ma { 1039 bias-disable; 1040 drive-strength = <4>; 1041 }; 1042 1043 pcfg_pull_down_4ma: pcfg-pull-down-4ma { 1044 bias-pull-down; 1045 drive-strength = <4>; 1046 }; 1047 1048 pcfg_pull_none_8ma: pcfg-pull-none-8ma { 1049 bias-disable; 1050 drive-strength = <8>; 1051 }; 1052 1053 pcfg_pull_up_8ma: pcfg-pull-up-8ma { 1054 bias-pull-up; 1055 drive-strength = <8>; 1056 }; 1057 1058 pcfg_pull_none_12ma: pcfg-pull-none-12ma { 1059 bias-disable; 1060 drive-strength = <12>; 1061 }; 1062 1063 pcfg_pull_up_12ma: pcfg-pull-up-12ma { 1064 bias-pull-up; 1065 drive-strength = <12>; 1066 }; 1067 1068 pcfg_output_high: pcfg-output-high { 1069 output-high; 1070 }; 1071 1072 pcfg_output_low: pcfg-output-low { 1073 output-low; 1074 }; 1075 1076 pcfg_input_high: pcfg-input-high { 1077 bias-pull-up; 1078 input-enable; 1079 }; 1080 1081 pcfg_input: pcfg-input { 1082 input-enable; 1083 }; 1084 1085 i2c0 { 1086 i2c0_xfer: i2c0-xfer { 1087 rockchip,pins = <2 RK_PD0 1 &pcfg_pull_none>, 1088 <2 RK_PD1 1 &pcfg_pull_none>; 1089 }; 1090 }; 1091 1092 i2c1 { 1093 i2c1_xfer: i2c1-xfer { 1094 rockchip,pins = <2 RK_PA4 2 &pcfg_pull_none>, 1095 <2 RK_PA5 2 &pcfg_pull_none>; 1096 }; 1097 }; 1098 1099 i2c2 { 1100 i2c2_xfer: i2c2-xfer { 1101 rockchip,pins = <2 RK_PB5 1 &pcfg_pull_none>, 1102 <2 RK_PB6 1 &pcfg_pull_none>; 1103 }; 1104 }; 1105 1106 i2c3 { 1107 i2c3_xfer: i2c3-xfer { 1108 rockchip,pins = <0 RK_PA5 2 &pcfg_pull_none>, 1109 <0 RK_PA6 2 &pcfg_pull_none>; 1110 }; 1111 i2c3_gpio: i2c3-gpio { 1112 rockchip,pins = 1113 <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>, 1114 <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; 1115 }; 1116 }; 1117 1118 hdmi_i2c { 1119 hdmii2c_xfer: hdmii2c-xfer { 1120 rockchip,pins = <0 RK_PA5 1 &pcfg_pull_none>, 1121 <0 RK_PA6 1 &pcfg_pull_none>; 1122 }; 1123 }; 1124 1125 pdm-0 { 1126 pdmm0_clk: pdmm0-clk { 1127 rockchip,pins = <2 RK_PC2 2 &pcfg_pull_none>; 1128 }; 1129 1130 pdmm0_fsync: pdmm0-fsync { 1131 rockchip,pins = <2 RK_PC7 2 &pcfg_pull_none>; 1132 }; 1133 1134 pdmm0_sdi0: pdmm0-sdi0 { 1135 rockchip,pins = <2 RK_PC3 2 &pcfg_pull_none>; 1136 }; 1137 1138 pdmm0_sdi1: pdmm0-sdi1 { 1139 rockchip,pins = <2 RK_PC4 2 &pcfg_pull_none>; 1140 }; 1141 1142 pdmm0_sdi2: pdmm0-sdi2 { 1143 rockchip,pins = <2 RK_PC5 2 &pcfg_pull_none>; 1144 }; 1145 1146 pdmm0_sdi3: pdmm0-sdi3 { 1147 rockchip,pins = <2 RK_PC6 2 &pcfg_pull_none>; 1148 }; 1149 1150 pdmm0_clk_sleep: pdmm0-clk-sleep { 1151 rockchip,pins = 1152 <2 RK_PC2 RK_FUNC_GPIO &pcfg_input_high>; 1153 }; 1154 1155 pdmm0_sdi0_sleep: pdmm0-sdi0-sleep { 1156 rockchip,pins = 1157 <2 RK_PC3 RK_FUNC_GPIO &pcfg_input_high>; 1158 }; 1159 1160 pdmm0_sdi1_sleep: pdmm0-sdi1-sleep { 1161 rockchip,pins = 1162 <2 RK_PC4 RK_FUNC_GPIO &pcfg_input_high>; 1163 }; 1164 1165 pdmm0_sdi2_sleep: pdmm0-sdi2-sleep { 1166 rockchip,pins = 1167 <2 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>; 1168 }; 1169 1170 pdmm0_sdi3_sleep: pdmm0-sdi3-sleep { 1171 rockchip,pins = 1172 <2 RK_PC6 RK_FUNC_GPIO &pcfg_input_high>; 1173 }; 1174 1175 pdmm0_fsync_sleep: pdmm0-fsync-sleep { 1176 rockchip,pins = 1177 <2 RK_PC7 RK_FUNC_GPIO &pcfg_input_high>; 1178 }; 1179 }; 1180 1181 tsadc { 1182 otp_gpio: otp-gpio { 1183 rockchip,pins = <2 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; 1184 }; 1185 1186 otp_out: otp-out { 1187 rockchip,pins = <2 RK_PB5 1 &pcfg_pull_none>; 1188 }; 1189 }; 1190 1191 uart0 { 1192 uart0_xfer: uart0-xfer { 1193 rockchip,pins = <1 RK_PB1 1 &pcfg_pull_up>, 1194 <1 RK_PB0 1 &pcfg_pull_none>; 1195 }; 1196 1197 uart0_cts: uart0-cts { 1198 rockchip,pins = <1 RK_PB3 1 &pcfg_pull_none>; 1199 }; 1200 1201 uart0_rts: uart0-rts { 1202 rockchip,pins = <1 RK_PB2 1 &pcfg_pull_none>; 1203 }; 1204 1205 uart0_rts_gpio: uart0-rts-gpio { 1206 rockchip,pins = <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; 1207 }; 1208 }; 1209 1210 uart1 { 1211 uart1_xfer: uart1-xfer { 1212 rockchip,pins = <3 RK_PA4 4 &pcfg_pull_up>, 1213 <3 RK_PA6 4 &pcfg_pull_none>; 1214 }; 1215 1216 uart1_cts: uart1-cts { 1217 rockchip,pins = <3 RK_PA7 4 &pcfg_pull_none>; 1218 }; 1219 1220 uart1_rts: uart1-rts { 1221 rockchip,pins = <3 RK_PA5 4 &pcfg_pull_none>; 1222 }; 1223 1224 uart1_rts_gpio: uart1-rts-gpio { 1225 rockchip,pins = <3 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; 1226 }; 1227 }; 1228 1229 uart2-0 { 1230 uart2m0_xfer: uart2m0-xfer { 1231 rockchip,pins = <1 RK_PA0 2 &pcfg_pull_up>, 1232 <1 RK_PA1 2 &pcfg_pull_none>; 1233 }; 1234 }; 1235 1236 uart2-1 { 1237 uart2m1_xfer: uart2m1-xfer { 1238 rockchip,pins = <2 RK_PA0 1 &pcfg_pull_up>, 1239 <2 RK_PA1 1 &pcfg_pull_none>; 1240 }; 1241 }; 1242 1243 spi0-0 { 1244 spi0m0_clk: spi0m0-clk { 1245 rockchip,pins = <2 RK_PB0 1 &pcfg_pull_up>; 1246 }; 1247 1248 spi0m0_cs0: spi0m0-cs0 { 1249 rockchip,pins = <2 RK_PB3 1 &pcfg_pull_up>; 1250 }; 1251 1252 spi0m0_tx: spi0m0-tx { 1253 rockchip,pins = <2 RK_PB1 1 &pcfg_pull_up>; 1254 }; 1255 1256 spi0m0_rx: spi0m0-rx { 1257 rockchip,pins = <2 RK_PB2 1 &pcfg_pull_up>; 1258 }; 1259 1260 spi0m0_cs1: spi0m0-cs1 { 1261 rockchip,pins = <2 RK_PB4 1 &pcfg_pull_up>; 1262 }; 1263 }; 1264 1265 spi0-1 { 1266 spi0m1_clk: spi0m1-clk { 1267 rockchip,pins = <3 RK_PC7 2 &pcfg_pull_up>; 1268 }; 1269 1270 spi0m1_cs0: spi0m1-cs0 { 1271 rockchip,pins = <3 RK_PD2 2 &pcfg_pull_up>; 1272 }; 1273 1274 spi0m1_tx: spi0m1-tx { 1275 rockchip,pins = <3 RK_PD1 2 &pcfg_pull_up>; 1276 }; 1277 1278 spi0m1_rx: spi0m1-rx { 1279 rockchip,pins = <3 RK_PD0 2 &pcfg_pull_up>; 1280 }; 1281 1282 spi0m1_cs1: spi0m1-cs1 { 1283 rockchip,pins = <3 RK_PD3 2 &pcfg_pull_up>; 1284 }; 1285 }; 1286 1287 spi0-2 { 1288 spi0m2_clk: spi0m2-clk { 1289 rockchip,pins = <3 RK_PA0 4 &pcfg_pull_up>; 1290 }; 1291 1292 spi0m2_cs0: spi0m2-cs0 { 1293 rockchip,pins = <3 RK_PB0 3 &pcfg_pull_up>; 1294 }; 1295 1296 spi0m2_tx: spi0m2-tx { 1297 rockchip,pins = <3 RK_PA1 4 &pcfg_pull_up>; 1298 }; 1299 1300 spi0m2_rx: spi0m2-rx { 1301 rockchip,pins = <3 RK_PA2 4 &pcfg_pull_up>; 1302 }; 1303 }; 1304 1305 i2s1 { 1306 i2s1_mclk: i2s1-mclk { 1307 rockchip,pins = <2 RK_PB7 1 &pcfg_pull_none>; 1308 }; 1309 1310 i2s1_sclk: i2s1-sclk { 1311 rockchip,pins = <2 RK_PC2 1 &pcfg_pull_none>; 1312 }; 1313 1314 i2s1_lrckrx: i2s1-lrckrx { 1315 rockchip,pins = <2 RK_PC0 1 &pcfg_pull_none>; 1316 }; 1317 1318 i2s1_lrcktx: i2s1-lrcktx { 1319 rockchip,pins = <2 RK_PC1 1 &pcfg_pull_none>; 1320 }; 1321 1322 i2s1_sdi: i2s1-sdi { 1323 rockchip,pins = <2 RK_PC3 1 &pcfg_pull_none>; 1324 }; 1325 1326 i2s1_sdo: i2s1-sdo { 1327 rockchip,pins = <2 RK_PC7 1 &pcfg_pull_none>; 1328 }; 1329 1330 i2s1_sdio1: i2s1-sdio1 { 1331 rockchip,pins = <2 RK_PC4 1 &pcfg_pull_none>; 1332 }; 1333 1334 i2s1_sdio2: i2s1-sdio2 { 1335 rockchip,pins = <2 RK_PC5 1 &pcfg_pull_none>; 1336 }; 1337 1338 i2s1_sdio3: i2s1-sdio3 { 1339 rockchip,pins = <2 RK_PC6 1 &pcfg_pull_none>; 1340 }; 1341 1342 i2s1_sleep: i2s1-sleep { 1343 rockchip,pins = 1344 <2 RK_PB7 RK_FUNC_GPIO &pcfg_input_high>, 1345 <2 RK_PC0 RK_FUNC_GPIO &pcfg_input_high>, 1346 <2 RK_PC1 RK_FUNC_GPIO &pcfg_input_high>, 1347 <2 RK_PC2 RK_FUNC_GPIO &pcfg_input_high>, 1348 <2 RK_PC3 RK_FUNC_GPIO &pcfg_input_high>, 1349 <2 RK_PC4 RK_FUNC_GPIO &pcfg_input_high>, 1350 <2 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>, 1351 <2 RK_PC6 RK_FUNC_GPIO &pcfg_input_high>, 1352 <2 RK_PC7 RK_FUNC_GPIO &pcfg_input_high>; 1353 }; 1354 }; 1355 1356 i2s2-0 { 1357 i2s2m0_mclk: i2s2m0-mclk { 1358 rockchip,pins = <1 RK_PC5 1 &pcfg_pull_none>; 1359 }; 1360 1361 i2s2m0_sclk: i2s2m0-sclk { 1362 rockchip,pins = <1 RK_PC6 1 &pcfg_pull_none>; 1363 }; 1364 1365 i2s2m0_lrckrx: i2s2m0-lrckrx { 1366 rockchip,pins = <1 RK_PD2 1 &pcfg_pull_none>; 1367 }; 1368 1369 i2s2m0_lrcktx: i2s2m0-lrcktx { 1370 rockchip,pins = <1 RK_PC7 1 &pcfg_pull_none>; 1371 }; 1372 1373 i2s2m0_sdi: i2s2m0-sdi { 1374 rockchip,pins = <1 RK_PD0 1 &pcfg_pull_none>; 1375 }; 1376 1377 i2s2m0_sdo: i2s2m0-sdo { 1378 rockchip,pins = <1 RK_PD1 1 &pcfg_pull_none>; 1379 }; 1380 1381 i2s2m0_sleep: i2s2m0-sleep { 1382 rockchip,pins = 1383 <1 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>, 1384 <1 RK_PC6 RK_FUNC_GPIO &pcfg_input_high>, 1385 <1 RK_PD2 RK_FUNC_GPIO &pcfg_input_high>, 1386 <1 RK_PC7 RK_FUNC_GPIO &pcfg_input_high>, 1387 <1 RK_PD0 RK_FUNC_GPIO &pcfg_input_high>, 1388 <1 RK_PD1 RK_FUNC_GPIO &pcfg_input_high>; 1389 }; 1390 }; 1391 1392 i2s2-1 { 1393 i2s2m1_mclk: i2s2m1-mclk { 1394 rockchip,pins = <1 RK_PC5 1 &pcfg_pull_none>; 1395 }; 1396 1397 i2s2m1_sclk: i2s2m1-sclk { 1398 rockchip,pins = <3 RK_PA0 6 &pcfg_pull_none>; 1399 }; 1400 1401 i2s2m1_lrckrx: i2sm1-lrckrx { 1402 rockchip,pins = <3 RK_PB0 6 &pcfg_pull_none>; 1403 }; 1404 1405 i2s2m1_lrcktx: i2s2m1-lrcktx { 1406 rockchip,pins = <3 RK_PB0 4 &pcfg_pull_none>; 1407 }; 1408 1409 i2s2m1_sdi: i2s2m1-sdi { 1410 rockchip,pins = <3 RK_PA2 6 &pcfg_pull_none>; 1411 }; 1412 1413 i2s2m1_sdo: i2s2m1-sdo { 1414 rockchip,pins = <3 RK_PA1 6 &pcfg_pull_none>; 1415 }; 1416 1417 i2s2m1_sleep: i2s2m1-sleep { 1418 rockchip,pins = 1419 <1 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>, 1420 <3 RK_PA0 RK_FUNC_GPIO &pcfg_input_high>, 1421 <3 RK_PB0 RK_FUNC_GPIO &pcfg_input_high>, 1422 <3 RK_PA2 RK_FUNC_GPIO &pcfg_input_high>, 1423 <3 RK_PA1 RK_FUNC_GPIO &pcfg_input_high>; 1424 }; 1425 }; 1426 1427 spdif-0 { 1428 spdifm0_tx: spdifm0-tx { 1429 rockchip,pins = <0 RK_PD3 1 &pcfg_pull_none>; 1430 }; 1431 }; 1432 1433 spdif-1 { 1434 spdifm1_tx: spdifm1-tx { 1435 rockchip,pins = <2 RK_PC1 2 &pcfg_pull_none>; 1436 }; 1437 }; 1438 1439 spdif-2 { 1440 spdifm2_tx: spdifm2-tx { 1441 rockchip,pins = <0 RK_PA2 2 &pcfg_pull_none>; 1442 }; 1443 }; 1444 1445 sdmmc0-0 { 1446 sdmmc0m0_pwren: sdmmc0m0-pwren { 1447 rockchip,pins = <2 RK_PA7 1 &pcfg_pull_up_4ma>; 1448 }; 1449 1450 sdmmc0m0_gpio: sdmmc0m0-gpio { 1451 rockchip,pins = <2 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up_4ma>; 1452 }; 1453 }; 1454 1455 sdmmc0-1 { 1456 sdmmc0m1_pwren: sdmmc0m1-pwren { 1457 rockchip,pins = <0 RK_PD6 3 &pcfg_pull_up_4ma>; 1458 }; 1459 1460 sdmmc0m1_gpio: sdmmc0m1-gpio { 1461 rockchip,pins = <0 RK_PD6 RK_FUNC_GPIO &pcfg_pull_up_4ma>; 1462 }; 1463 }; 1464 1465 sdmmc0 { 1466 sdmmc0_clk: sdmmc0-clk { 1467 rockchip,pins = <1 RK_PA6 1 &pcfg_pull_none_8ma>; 1468 }; 1469 1470 sdmmc0_cmd: sdmmc0-cmd { 1471 rockchip,pins = <1 RK_PA4 1 &pcfg_pull_up_8ma>; 1472 }; 1473 1474 sdmmc0_dectn: sdmmc0-dectn { 1475 rockchip,pins = <1 RK_PA5 1 &pcfg_pull_up_4ma>; 1476 }; 1477 1478 sdmmc0_wrprt: sdmmc0-wrprt { 1479 rockchip,pins = <1 RK_PA7 1 &pcfg_pull_up_4ma>; 1480 }; 1481 1482 sdmmc0_bus1: sdmmc0-bus1 { 1483 rockchip,pins = <1 RK_PA0 1 &pcfg_pull_up_8ma>; 1484 }; 1485 1486 sdmmc0_bus4: sdmmc0-bus4 { 1487 rockchip,pins = <1 RK_PA0 1 &pcfg_pull_up_8ma>, 1488 <1 RK_PA1 1 &pcfg_pull_up_8ma>, 1489 <1 RK_PA2 1 &pcfg_pull_up_8ma>, 1490 <1 RK_PA3 1 &pcfg_pull_up_8ma>; 1491 }; 1492 1493 sdmmc0_gpio: sdmmc0-gpio { 1494 rockchip,pins = 1495 <1 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1496 <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1497 <1 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1498 <1 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1499 <1 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1500 <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1501 <1 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1502 <1 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up_4ma>; 1503 }; 1504 }; 1505 1506 sdmmc0ext { 1507 sdmmc0ext_clk: sdmmc0ext-clk { 1508 rockchip,pins = <3 RK_PA2 3 &pcfg_pull_none_4ma>; 1509 }; 1510 1511 sdmmc0ext_cmd: sdmmc0ext-cmd { 1512 rockchip,pins = <3 RK_PA0 3 &pcfg_pull_up_4ma>; 1513 }; 1514 1515 sdmmc0ext_wrprt: sdmmc0ext-wrprt { 1516 rockchip,pins = <3 RK_PA3 3 &pcfg_pull_up_4ma>; 1517 }; 1518 1519 sdmmc0ext_dectn: sdmmc0ext-dectn { 1520 rockchip,pins = <3 RK_PA1 3 &pcfg_pull_up_4ma>; 1521 }; 1522 1523 sdmmc0ext_bus1: sdmmc0ext-bus1 { 1524 rockchip,pins = <3 RK_PA4 3 &pcfg_pull_up_4ma>; 1525 }; 1526 1527 sdmmc0ext_bus4: sdmmc0ext-bus4 { 1528 rockchip,pins = 1529 <3 RK_PA4 3 &pcfg_pull_up_4ma>, 1530 <3 RK_PA5 3 &pcfg_pull_up_4ma>, 1531 <3 RK_PA6 3 &pcfg_pull_up_4ma>, 1532 <3 RK_PA7 3 &pcfg_pull_up_4ma>; 1533 }; 1534 1535 sdmmc0ext_gpio: sdmmc0ext-gpio { 1536 rockchip,pins = 1537 <3 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1538 <3 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1539 <3 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1540 <3 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1541 <3 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1542 <3 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1543 <3 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1544 <3 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up_4ma>; 1545 }; 1546 }; 1547 1548 sdmmc1 { 1549 sdmmc1_clk: sdmmc1-clk { 1550 rockchip,pins = <1 RK_PB4 1 &pcfg_pull_none_8ma>; 1551 }; 1552 1553 sdmmc1_cmd: sdmmc1-cmd { 1554 rockchip,pins = <1 RK_PB5 1 &pcfg_pull_up_8ma>; 1555 }; 1556 1557 sdmmc1_pwren: sdmmc1-pwren { 1558 rockchip,pins = <1 RK_PC2 1 &pcfg_pull_up_8ma>; 1559 }; 1560 1561 sdmmc1_wrprt: sdmmc1-wrprt { 1562 rockchip,pins = <1 RK_PC4 1 &pcfg_pull_up_8ma>; 1563 }; 1564 1565 sdmmc1_dectn: sdmmc1-dectn { 1566 rockchip,pins = <1 RK_PC3 1 &pcfg_pull_up_8ma>; 1567 }; 1568 1569 sdmmc1_bus1: sdmmc1-bus1 { 1570 rockchip,pins = <1 RK_PB6 1 &pcfg_pull_up_8ma>; 1571 }; 1572 1573 sdmmc1_bus4: sdmmc1-bus4 { 1574 rockchip,pins = <1 RK_PB6 1 &pcfg_pull_up_8ma>, 1575 <1 RK_PB7 1 &pcfg_pull_up_8ma>, 1576 <1 RK_PC0 1 &pcfg_pull_up_8ma>, 1577 <1 RK_PC1 1 &pcfg_pull_up_8ma>; 1578 }; 1579 1580 sdmmc1_gpio: sdmmc1-gpio { 1581 rockchip,pins = 1582 <1 RK_PB4 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1583 <1 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1584 <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1585 <1 RK_PB7 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1586 <1 RK_PC0 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1587 <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1588 <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1589 <1 RK_PC3 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1590 <1 RK_PC4 RK_FUNC_GPIO &pcfg_pull_up_4ma>; 1591 }; 1592 }; 1593 1594 emmc { 1595 emmc_clk: emmc-clk { 1596 rockchip,pins = <3 RK_PC5 2 &pcfg_pull_none_12ma>; 1597 }; 1598 1599 emmc_cmd: emmc-cmd { 1600 rockchip,pins = <3 RK_PC3 2 &pcfg_pull_up_12ma>; 1601 }; 1602 1603 emmc_pwren: emmc-pwren { 1604 rockchip,pins = <3 RK_PC6 2 &pcfg_pull_none>; 1605 }; 1606 1607 emmc_rstnout: emmc-rstnout { 1608 rockchip,pins = <3 RK_PC4 2 &pcfg_pull_none>; 1609 }; 1610 1611 emmc_bus1: emmc-bus1 { 1612 rockchip,pins = <0 RK_PA7 2 &pcfg_pull_up_12ma>; 1613 }; 1614 1615 emmc_bus4: emmc-bus4 { 1616 rockchip,pins = 1617 <0 RK_PA7 2 &pcfg_pull_up_12ma>, 1618 <2 RK_PD4 2 &pcfg_pull_up_12ma>, 1619 <2 RK_PD5 2 &pcfg_pull_up_12ma>, 1620 <2 RK_PD6 2 &pcfg_pull_up_12ma>; 1621 }; 1622 1623 emmc_bus8: emmc-bus8 { 1624 rockchip,pins = 1625 <0 RK_PA7 2 &pcfg_pull_up_12ma>, 1626 <2 RK_PD4 2 &pcfg_pull_up_12ma>, 1627 <2 RK_PD5 2 &pcfg_pull_up_12ma>, 1628 <2 RK_PD6 2 &pcfg_pull_up_12ma>, 1629 <2 RK_PD7 2 &pcfg_pull_up_12ma>, 1630 <3 RK_PC0 2 &pcfg_pull_up_12ma>, 1631 <3 RK_PC1 2 &pcfg_pull_up_12ma>, 1632 <3 RK_PC2 2 &pcfg_pull_up_12ma>; 1633 }; 1634 }; 1635 1636 pwm0 { 1637 pwm0_pin: pwm0-pin { 1638 rockchip,pins = <2 RK_PA4 1 &pcfg_pull_none>; 1639 }; 1640 }; 1641 1642 pwm1 { 1643 pwm1_pin: pwm1-pin { 1644 rockchip,pins = <2 RK_PA5 1 &pcfg_pull_none>; 1645 }; 1646 }; 1647 1648 pwm2 { 1649 pwm2_pin: pwm2-pin { 1650 rockchip,pins = <2 RK_PA6 1 &pcfg_pull_none>; 1651 }; 1652 }; 1653 1654 pwmir { 1655 pwmir_pin: pwmir-pin { 1656 rockchip,pins = <2 RK_PA2 1 &pcfg_pull_none>; 1657 }; 1658 }; 1659 1660 gmac-1 { 1661 rgmiim1_pins: rgmiim1-pins { 1662 rockchip,pins = 1663 /* mac_txclk */ 1664 <1 RK_PB4 2 &pcfg_pull_none_8ma>, 1665 /* mac_rxclk */ 1666 <1 RK_PB5 2 &pcfg_pull_none_4ma>, 1667 /* mac_mdio */ 1668 <1 RK_PC3 2 &pcfg_pull_none_4ma>, 1669 /* mac_txen */ 1670 <1 RK_PD1 2 &pcfg_pull_none_8ma>, 1671 /* mac_clk */ 1672 <1 RK_PC5 2 &pcfg_pull_none_4ma>, 1673 /* mac_rxdv */ 1674 <1 RK_PC6 2 &pcfg_pull_none_4ma>, 1675 /* mac_mdc */ 1676 <1 RK_PC7 2 &pcfg_pull_none_4ma>, 1677 /* mac_rxd1 */ 1678 <1 RK_PB2 2 &pcfg_pull_none_4ma>, 1679 /* mac_rxd0 */ 1680 <1 RK_PB3 2 &pcfg_pull_none_4ma>, 1681 /* mac_txd1 */ 1682 <1 RK_PB0 2 &pcfg_pull_none_8ma>, 1683 /* mac_txd0 */ 1684 <1 RK_PB1 2 &pcfg_pull_none_8ma>, 1685 /* mac_rxd3 */ 1686 <1 RK_PB6 2 &pcfg_pull_none_4ma>, 1687 /* mac_rxd2 */ 1688 <1 RK_PB7 2 &pcfg_pull_none_4ma>, 1689 /* mac_txd3 */ 1690 <1 RK_PC0 2 &pcfg_pull_none_8ma>, 1691 /* mac_txd2 */ 1692 <1 RK_PC1 2 &pcfg_pull_none_8ma>, 1693 1694 /* mac_txclk */ 1695 <0 RK_PB0 1 &pcfg_pull_none_8ma>, 1696 /* mac_txen */ 1697 <0 RK_PB4 1 &pcfg_pull_none_8ma>, 1698 /* mac_clk */ 1699 <0 RK_PD0 1 &pcfg_pull_none_4ma>, 1700 /* mac_txd1 */ 1701 <0 RK_PC0 1 &pcfg_pull_none_8ma>, 1702 /* mac_txd0 */ 1703 <0 RK_PC1 1 &pcfg_pull_none_8ma>, 1704 /* mac_txd3 */ 1705 <0 RK_PC7 1 &pcfg_pull_none_8ma>, 1706 /* mac_txd2 */ 1707 <0 RK_PC6 1 &pcfg_pull_none_8ma>; 1708 }; 1709 1710 rmiim1_pins: rmiim1-pins { 1711 rockchip,pins = 1712 /* mac_mdio */ 1713 <1 RK_PC3 2 &pcfg_pull_none_2ma>, 1714 /* mac_txen */ 1715 <1 RK_PD1 2 &pcfg_pull_none_12ma>, 1716 /* mac_clk */ 1717 <1 RK_PC5 2 &pcfg_pull_none_2ma>, 1718 /* mac_rxer */ 1719 <1 RK_PD0 2 &pcfg_pull_none_2ma>, 1720 /* mac_rxdv */ 1721 <1 RK_PC6 2 &pcfg_pull_none_2ma>, 1722 /* mac_mdc */ 1723 <1 RK_PC7 2 &pcfg_pull_none_2ma>, 1724 /* mac_rxd1 */ 1725 <1 RK_PB2 2 &pcfg_pull_none_2ma>, 1726 /* mac_rxd0 */ 1727 <1 RK_PB3 2 &pcfg_pull_none_2ma>, 1728 /* mac_txd1 */ 1729 <1 RK_PB0 2 &pcfg_pull_none_12ma>, 1730 /* mac_txd0 */ 1731 <1 RK_PB1 2 &pcfg_pull_none_12ma>, 1732 1733 /* mac_mdio */ 1734 <0 RK_PB3 1 &pcfg_pull_none>, 1735 /* mac_txen */ 1736 <0 RK_PB4 1 &pcfg_pull_none>, 1737 /* mac_clk */ 1738 <0 RK_PD0 1 &pcfg_pull_none>, 1739 /* mac_mdc */ 1740 <0 RK_PC3 1 &pcfg_pull_none>, 1741 /* mac_txd1 */ 1742 <0 RK_PC0 1 &pcfg_pull_none>, 1743 /* mac_txd0 */ 1744 <0 RK_PC1 1 &pcfg_pull_none>; 1745 }; 1746 }; 1747 1748 gmac2phy { 1749 fephyled_speed100: fephyled-speed100 { 1750 rockchip,pins = <0 RK_PD7 1 &pcfg_pull_none>; 1751 }; 1752 1753 fephyled_speed10: fephyled-speed10 { 1754 rockchip,pins = <0 RK_PD6 1 &pcfg_pull_none>; 1755 }; 1756 1757 fephyled_duplex: fephyled-duplex { 1758 rockchip,pins = <0 RK_PD6 2 &pcfg_pull_none>; 1759 }; 1760 1761 fephyled_rxm0: fephyled-rxm0 { 1762 rockchip,pins = <0 RK_PD5 1 &pcfg_pull_none>; 1763 }; 1764 1765 fephyled_txm0: fephyled-txm0 { 1766 rockchip,pins = <0 RK_PD5 2 &pcfg_pull_none>; 1767 }; 1768 1769 fephyled_linkm0: fephyled-linkm0 { 1770 rockchip,pins = <0 RK_PD4 1 &pcfg_pull_none>; 1771 }; 1772 1773 fephyled_rxm1: fephyled-rxm1 { 1774 rockchip,pins = <2 RK_PD1 2 &pcfg_pull_none>; 1775 }; 1776 1777 fephyled_txm1: fephyled-txm1 { 1778 rockchip,pins = <2 RK_PD1 3 &pcfg_pull_none>; 1779 }; 1780 1781 fephyled_linkm1: fephyled-linkm1 { 1782 rockchip,pins = <2 RK_PD0 2 &pcfg_pull_none>; 1783 }; 1784 }; 1785 1786 tsadc_pin { 1787 tsadc_int: tsadc-int { 1788 rockchip,pins = <2 RK_PB5 2 &pcfg_pull_none>; 1789 }; 1790 tsadc_gpio: tsadc-gpio { 1791 rockchip,pins = <2 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; 1792 }; 1793 }; 1794 1795 hdmi_pin { 1796 hdmi_cec: hdmi-cec { 1797 rockchip,pins = <0 RK_PA3 1 &pcfg_pull_none>; 1798 }; 1799 1800 hdmi_hpd: hdmi-hpd { 1801 rockchip,pins = <0 RK_PA4 1 &pcfg_pull_down>; 1802 }; 1803 }; 1804 1805 cif-0 { 1806 dvp_d2d9_m0:dvp-d2d9-m0 { 1807 rockchip,pins = 1808 /* cif_d0 */ 1809 <3 RK_PA4 2 &pcfg_pull_none>, 1810 /* cif_d1 */ 1811 <3 RK_PA5 2 &pcfg_pull_none>, 1812 /* cif_d2 */ 1813 <3 RK_PA6 2 &pcfg_pull_none>, 1814 /* cif_d3 */ 1815 <3 RK_PA7 2 &pcfg_pull_none>, 1816 /* cif_d4 */ 1817 <3 RK_PB0 2 &pcfg_pull_none>, 1818 /* cif_d5m0 */ 1819 <3 RK_PB1 2 &pcfg_pull_none>, 1820 /* cif_d6m0 */ 1821 <3 RK_PB2 2 &pcfg_pull_none>, 1822 /* cif_d7m0 */ 1823 <3 RK_PB3 2 &pcfg_pull_none>, 1824 /* cif_href */ 1825 <3 RK_PA1 2 &pcfg_pull_none>, 1826 /* cif_vsync */ 1827 <3 RK_PA0 2 &pcfg_pull_none>, 1828 /* cif_clkoutm0 */ 1829 <3 RK_PA3 2 &pcfg_pull_none>, 1830 /* cif_clkin */ 1831 <3 RK_PA2 2 &pcfg_pull_none>; 1832 }; 1833 }; 1834 1835 cif-1 { 1836 dvp_d2d9_m1:dvp-d2d9-m1 { 1837 rockchip,pins = 1838 /* cif_d0 */ 1839 <3 RK_PA4 2 &pcfg_pull_none>, 1840 /* cif_d1 */ 1841 <3 RK_PA5 2 &pcfg_pull_none>, 1842 /* cif_d2 */ 1843 <3 RK_PA6 2 &pcfg_pull_none>, 1844 /* cif_d3 */ 1845 <3 RK_PA7 2 &pcfg_pull_none>, 1846 /* cif_d4 */ 1847 <3 RK_PB0 2 &pcfg_pull_none>, 1848 /* cif_d5m1 */ 1849 <2 RK_PC0 4 &pcfg_pull_none>, 1850 /* cif_d6m1 */ 1851 <2 RK_PC1 4 &pcfg_pull_none>, 1852 /* cif_d7m1 */ 1853 <2 RK_PC2 4 &pcfg_pull_none>, 1854 /* cif_href */ 1855 <3 RK_PA1 2 &pcfg_pull_none>, 1856 /* cif_vsync */ 1857 <3 RK_PA0 2 &pcfg_pull_none>, 1858 /* cif_clkoutm1 */ 1859 <2 RK_PB7 4 &pcfg_pull_none>, 1860 /* cif_clkin */ 1861 <3 RK_PA2 2 &pcfg_pull_none>; 1862 }; 1863 }; 1864 }; 1865}; 1866
