1/* 2 * Device Tree Source for OMAP3 SoC 3 * 4 * Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/ 5 * 6 * This file is licensed under the terms of the GNU General Public License 7 * version 2. This program is licensed "as is" without any warranty of any 8 * kind, whether express or implied. 9 */ 10 11#include <dt-bindings/bus/ti-sysc.h> 12#include <dt-bindings/gpio/gpio.h> 13#include <dt-bindings/interrupt-controller/irq.h> 14#include <dt-bindings/pinctrl/omap.h> 15 16/ { 17 compatible = "ti,omap3430", "ti,omap3"; 18 interrupt-parent = <&intc>; 19 #address-cells = <1>; 20 #size-cells = <1>; 21 chosen { }; 22 23 aliases { 24 i2c0 = &i2c1; 25 i2c1 = &i2c2; 26 i2c2 = &i2c3; 27 serial0 = &uart1; 28 serial1 = &uart2; 29 serial2 = &uart3; 30 }; 31 32 cpus { 33 #address-cells = <1>; 34 #size-cells = <0>; 35 36 cpu@0 { 37 compatible = "arm,cortex-a8"; 38 device_type = "cpu"; 39 reg = <0x0>; 40 41 clocks = <&dpll1_ck>; 42 clock-names = "cpu"; 43 44 clock-latency = <300000>; /* From omap-cpufreq driver */ 45 }; 46 }; 47 48 pmu@54000000 { 49 compatible = "arm,cortex-a8-pmu"; 50 reg = <0x54000000 0x800000>; 51 interrupts = <3>; 52 ti,hwmods = "debugss"; 53 }; 54 55 /* 56 * The soc node represents the soc top level view. It is used for IPs 57 * that are not memory mapped in the MPU view or for the MPU itself. 58 */ 59 soc { 60 compatible = "ti,omap-infra"; 61 mpu { 62 compatible = "ti,omap3-mpu"; 63 ti,hwmods = "mpu"; 64 }; 65 66 iva: iva { 67 compatible = "ti,iva2.2"; 68 ti,hwmods = "iva"; 69 70 dsp { 71 compatible = "ti,omap3-c64"; 72 }; 73 }; 74 }; 75 76 /* 77 * XXX: Use a flat representation of the OMAP3 interconnect. 78 * The real OMAP interconnect network is quite complex. 79 * Since it will not bring real advantage to represent that in DT for 80 * the moment, just use a fake OCP bus entry to represent the whole bus 81 * hierarchy. 82 */ 83 ocp@68000000 { 84 compatible = "ti,omap3-l3-smx", "simple-bus"; 85 reg = <0x68000000 0x10000>; 86 interrupts = <9 10>; 87 #address-cells = <1>; 88 #size-cells = <1>; 89 ranges; 90 ti,hwmods = "l3_main"; 91 92 l4_core: l4@48000000 { 93 compatible = "ti,omap3-l4-core", "simple-bus"; 94 #address-cells = <1>; 95 #size-cells = <1>; 96 ranges = <0 0x48000000 0x1000000>; 97 98 scm: scm@2000 { 99 compatible = "ti,omap3-scm", "simple-bus"; 100 reg = <0x2000 0x2000>; 101 #address-cells = <1>; 102 #size-cells = <1>; 103 ranges = <0 0x2000 0x2000>; 104 105 omap3_pmx_core: pinmux@30 { 106 compatible = "ti,omap3-padconf", 107 "pinctrl-single"; 108 reg = <0x30 0x238>; 109 #address-cells = <1>; 110 #size-cells = <0>; 111 #pinctrl-cells = <1>; 112 #interrupt-cells = <1>; 113 interrupt-controller; 114 pinctrl-single,register-width = <16>; 115 pinctrl-single,function-mask = <0xff1f>; 116 }; 117 118 scm_conf: scm_conf@270 { 119 compatible = "syscon", "simple-bus"; 120 reg = <0x270 0x330>; 121 #address-cells = <1>; 122 #size-cells = <1>; 123 ranges = <0 0x270 0x330>; 124 125 pbias_regulator: pbias_regulator@2b0 { 126 compatible = "ti,pbias-omap3", "ti,pbias-omap"; 127 reg = <0x2b0 0x4>; 128 syscon = <&scm_conf>; 129 pbias_mmc_reg: pbias_mmc_omap2430 { 130 regulator-name = "pbias_mmc_omap2430"; 131 regulator-min-microvolt = <1800000>; 132 regulator-max-microvolt = <3000000>; 133 }; 134 }; 135 136 scm_clocks: clocks { 137 #address-cells = <1>; 138 #size-cells = <0>; 139 }; 140 }; 141 142 scm_clockdomains: clockdomains { 143 }; 144 145 omap3_pmx_wkup: pinmux@a00 { 146 compatible = "ti,omap3-padconf", 147 "pinctrl-single"; 148 reg = <0xa00 0x5c>; 149 #address-cells = <1>; 150 #size-cells = <0>; 151 #pinctrl-cells = <1>; 152 #interrupt-cells = <1>; 153 interrupt-controller; 154 pinctrl-single,register-width = <16>; 155 pinctrl-single,function-mask = <0xff1f>; 156 }; 157 }; 158 }; 159 160 aes1_target: target-module@480a6000 { 161 compatible = "ti,sysc-omap2", "ti,sysc"; 162 reg = <0x480a6044 0x4>, 163 <0x480a6048 0x4>, 164 <0x480a604c 0x4>; 165 reg-names = "rev", "sysc", "syss"; 166 ti,sysc-mask = <(SYSC_OMAP2_AUTOIDLE)>; 167 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 168 <SYSC_IDLE_NO>, 169 <SYSC_IDLE_SMART>; 170 ti,syss-mask = <1>; 171 clocks = <&aes1_ick>; 172 clock-names = "ick"; 173 #address-cells = <1>; 174 #size-cells = <1>; 175 ranges = <0 0x480a6000 0x2000>; 176 177 aes1: aes1@0 { 178 compatible = "ti,omap3-aes"; 179 reg = <0 0x50>; 180 interrupts = <0>; 181 dmas = <&sdma 9 &sdma 10>; 182 dma-names = "tx", "rx"; 183 }; 184 }; 185 186 aes2_target: target-module@480c5000 { 187 compatible = "ti,sysc-omap2", "ti,sysc"; 188 reg = <0x480c5044 0x4>, 189 <0x480c5048 0x4>, 190 <0x480c504c 0x4>; 191 reg-names = "rev", "sysc", "syss"; 192 ti,sysc-mask = <(SYSC_OMAP2_AUTOIDLE)>; 193 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 194 <SYSC_IDLE_NO>, 195 <SYSC_IDLE_SMART>; 196 ti,syss-mask = <1>; 197 clocks = <&aes2_ick>; 198 clock-names = "ick"; 199 #address-cells = <1>; 200 #size-cells = <1>; 201 ranges = <0 0x480c5000 0x2000>; 202 203 aes2: aes2@0 { 204 compatible = "ti,omap3-aes"; 205 reg = <0 0x50>; 206 interrupts = <0>; 207 dmas = <&sdma 65 &sdma 66>; 208 dma-names = "tx", "rx"; 209 }; 210 }; 211 212 prm: prm@48306000 { 213 compatible = "ti,omap3-prm"; 214 reg = <0x48306000 0x4000>; 215 interrupts = <11>; 216 217 prm_clocks: clocks { 218 #address-cells = <1>; 219 #size-cells = <0>; 220 }; 221 222 prm_clockdomains: clockdomains { 223 }; 224 }; 225 226 cm: cm@48004000 { 227 compatible = "ti,omap3-cm"; 228 reg = <0x48004000 0x4000>; 229 230 cm_clocks: clocks { 231 #address-cells = <1>; 232 #size-cells = <0>; 233 }; 234 235 cm_clockdomains: clockdomains { 236 }; 237 }; 238 239 target-module@48320000 { 240 compatible = "ti,sysc-omap2", "ti,sysc"; 241 reg = <0x48320000 0x4>, 242 <0x48320004 0x4>; 243 reg-names = "rev", "sysc"; 244 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 245 <SYSC_IDLE_NO>; 246 clocks = <&wkup_32k_fck>, <&omap_32ksync_ick>; 247 clock-names = "fck", "ick"; 248 #address-cells = <1>; 249 #size-cells = <1>; 250 ranges = <0x0 0x48320000 0x1000>; 251 252 counter32k: counter@0 { 253 compatible = "ti,omap-counter32k"; 254 reg = <0x0 0x20>; 255 }; 256 }; 257 258 intc: interrupt-controller@48200000 { 259 compatible = "ti,omap3-intc"; 260 interrupt-controller; 261 #interrupt-cells = <1>; 262 reg = <0x48200000 0x1000>; 263 }; 264 265 target-module@48056000 { 266 compatible = "ti,sysc-omap2", "ti,sysc"; 267 reg = <0x48056000 0x4>, 268 <0x4805602c 0x4>, 269 <0x48056028 0x4>; 270 reg-names = "rev", "sysc", "syss"; 271 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | 272 SYSC_OMAP2_EMUFREE | 273 SYSC_OMAP2_SOFTRESET | 274 SYSC_OMAP2_AUTOIDLE)>; 275 ti,sysc-midle = <SYSC_IDLE_FORCE>, 276 <SYSC_IDLE_NO>, 277 <SYSC_IDLE_SMART>; 278 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 279 <SYSC_IDLE_NO>, 280 <SYSC_IDLE_SMART>; 281 ti,syss-mask = <1>; 282 /* Domains (V, P, C): core, core_pwrdm, core_l3_clkdm */ 283 clocks = <&core_l3_ick>; 284 clock-names = "ick"; 285 #address-cells = <1>; 286 #size-cells = <1>; 287 ranges = <0 0x48056000 0x1000>; 288 289 sdma: dma-controller@0 { 290 compatible = "ti,omap3430-sdma", "ti,omap-sdma"; 291 reg = <0x0 0x1000>; 292 interrupts = <12>, 293 <13>, 294 <14>, 295 <15>; 296 #dma-cells = <1>; 297 dma-channels = <32>; 298 dma-requests = <96>; 299 }; 300 }; 301 302 gpio1: gpio@48310000 { 303 compatible = "ti,omap3-gpio"; 304 reg = <0x48310000 0x200>; 305 interrupts = <29>; 306 ti,hwmods = "gpio1"; 307 ti,gpio-always-on; 308 gpio-controller; 309 #gpio-cells = <2>; 310 interrupt-controller; 311 #interrupt-cells = <2>; 312 }; 313 314 gpio2: gpio@49050000 { 315 compatible = "ti,omap3-gpio"; 316 reg = <0x49050000 0x200>; 317 interrupts = <30>; 318 ti,hwmods = "gpio2"; 319 gpio-controller; 320 #gpio-cells = <2>; 321 interrupt-controller; 322 #interrupt-cells = <2>; 323 }; 324 325 gpio3: gpio@49052000 { 326 compatible = "ti,omap3-gpio"; 327 reg = <0x49052000 0x200>; 328 interrupts = <31>; 329 ti,hwmods = "gpio3"; 330 gpio-controller; 331 #gpio-cells = <2>; 332 interrupt-controller; 333 #interrupt-cells = <2>; 334 }; 335 336 gpio4: gpio@49054000 { 337 compatible = "ti,omap3-gpio"; 338 reg = <0x49054000 0x200>; 339 interrupts = <32>; 340 ti,hwmods = "gpio4"; 341 gpio-controller; 342 #gpio-cells = <2>; 343 interrupt-controller; 344 #interrupt-cells = <2>; 345 }; 346 347 gpio5: gpio@49056000 { 348 compatible = "ti,omap3-gpio"; 349 reg = <0x49056000 0x200>; 350 interrupts = <33>; 351 ti,hwmods = "gpio5"; 352 gpio-controller; 353 #gpio-cells = <2>; 354 interrupt-controller; 355 #interrupt-cells = <2>; 356 }; 357 358 gpio6: gpio@49058000 { 359 compatible = "ti,omap3-gpio"; 360 reg = <0x49058000 0x200>; 361 interrupts = <34>; 362 ti,hwmods = "gpio6"; 363 gpio-controller; 364 #gpio-cells = <2>; 365 interrupt-controller; 366 #interrupt-cells = <2>; 367 }; 368 369 uart1: serial@4806a000 { 370 compatible = "ti,omap3-uart"; 371 reg = <0x4806a000 0x2000>; 372 interrupts-extended = <&intc 72>; 373 dmas = <&sdma 49 &sdma 50>; 374 dma-names = "tx", "rx"; 375 ti,hwmods = "uart1"; 376 clock-frequency = <48000000>; 377 }; 378 379 uart2: serial@4806c000 { 380 compatible = "ti,omap3-uart"; 381 reg = <0x4806c000 0x400>; 382 interrupts-extended = <&intc 73>; 383 dmas = <&sdma 51 &sdma 52>; 384 dma-names = "tx", "rx"; 385 ti,hwmods = "uart2"; 386 clock-frequency = <48000000>; 387 }; 388 389 uart3: serial@49020000 { 390 compatible = "ti,omap3-uart"; 391 reg = <0x49020000 0x400>; 392 interrupts-extended = <&intc 74>; 393 dmas = <&sdma 53 &sdma 54>; 394 dma-names = "tx", "rx"; 395 ti,hwmods = "uart3"; 396 clock-frequency = <48000000>; 397 }; 398 399 i2c1: i2c@48070000 { 400 compatible = "ti,omap3-i2c"; 401 reg = <0x48070000 0x80>; 402 interrupts = <56>; 403 dmas = <&sdma 27 &sdma 28>; 404 dma-names = "tx", "rx"; 405 #address-cells = <1>; 406 #size-cells = <0>; 407 ti,hwmods = "i2c1"; 408 }; 409 410 i2c2: i2c@48072000 { 411 compatible = "ti,omap3-i2c"; 412 reg = <0x48072000 0x80>; 413 interrupts = <57>; 414 dmas = <&sdma 29 &sdma 30>; 415 dma-names = "tx", "rx"; 416 #address-cells = <1>; 417 #size-cells = <0>; 418 ti,hwmods = "i2c2"; 419 }; 420 421 i2c3: i2c@48060000 { 422 compatible = "ti,omap3-i2c"; 423 reg = <0x48060000 0x80>; 424 interrupts = <61>; 425 dmas = <&sdma 25 &sdma 26>; 426 dma-names = "tx", "rx"; 427 #address-cells = <1>; 428 #size-cells = <0>; 429 ti,hwmods = "i2c3"; 430 }; 431 432 mailbox: mailbox@48094000 { 433 compatible = "ti,omap3-mailbox"; 434 ti,hwmods = "mailbox"; 435 reg = <0x48094000 0x200>; 436 interrupts = <26>; 437 #mbox-cells = <1>; 438 ti,mbox-num-users = <2>; 439 ti,mbox-num-fifos = <2>; 440 mbox_dsp: dsp { 441 ti,mbox-tx = <0 0 0>; 442 ti,mbox-rx = <1 0 0>; 443 }; 444 }; 445 446 mcspi1: spi@48098000 { 447 compatible = "ti,omap2-mcspi"; 448 reg = <0x48098000 0x100>; 449 interrupts = <65>; 450 #address-cells = <1>; 451 #size-cells = <0>; 452 ti,hwmods = "mcspi1"; 453 ti,spi-num-cs = <4>; 454 dmas = <&sdma 35>, 455 <&sdma 36>, 456 <&sdma 37>, 457 <&sdma 38>, 458 <&sdma 39>, 459 <&sdma 40>, 460 <&sdma 41>, 461 <&sdma 42>; 462 dma-names = "tx0", "rx0", "tx1", "rx1", 463 "tx2", "rx2", "tx3", "rx3"; 464 }; 465 466 mcspi2: spi@4809a000 { 467 compatible = "ti,omap2-mcspi"; 468 reg = <0x4809a000 0x100>; 469 interrupts = <66>; 470 #address-cells = <1>; 471 #size-cells = <0>; 472 ti,hwmods = "mcspi2"; 473 ti,spi-num-cs = <2>; 474 dmas = <&sdma 43>, 475 <&sdma 44>, 476 <&sdma 45>, 477 <&sdma 46>; 478 dma-names = "tx0", "rx0", "tx1", "rx1"; 479 }; 480 481 mcspi3: spi@480b8000 { 482 compatible = "ti,omap2-mcspi"; 483 reg = <0x480b8000 0x100>; 484 interrupts = <91>; 485 #address-cells = <1>; 486 #size-cells = <0>; 487 ti,hwmods = "mcspi3"; 488 ti,spi-num-cs = <2>; 489 dmas = <&sdma 15>, 490 <&sdma 16>, 491 <&sdma 23>, 492 <&sdma 24>; 493 dma-names = "tx0", "rx0", "tx1", "rx1"; 494 }; 495 496 mcspi4: spi@480ba000 { 497 compatible = "ti,omap2-mcspi"; 498 reg = <0x480ba000 0x100>; 499 interrupts = <48>; 500 #address-cells = <1>; 501 #size-cells = <0>; 502 ti,hwmods = "mcspi4"; 503 ti,spi-num-cs = <1>; 504 dmas = <&sdma 70>, <&sdma 71>; 505 dma-names = "tx0", "rx0"; 506 }; 507 508 hdqw1w: 1w@480b2000 { 509 compatible = "ti,omap3-1w"; 510 reg = <0x480b2000 0x1000>; 511 interrupts = <58>; 512 ti,hwmods = "hdq1w"; 513 }; 514 515 mmc1: mmc@4809c000 { 516 compatible = "ti,omap3-hsmmc"; 517 reg = <0x4809c000 0x200>; 518 interrupts = <83>; 519 ti,hwmods = "mmc1"; 520 ti,dual-volt; 521 dmas = <&sdma 61>, <&sdma 62>; 522 dma-names = "tx", "rx"; 523 pbias-supply = <&pbias_mmc_reg>; 524 }; 525 526 mmc2: mmc@480b4000 { 527 compatible = "ti,omap3-hsmmc"; 528 reg = <0x480b4000 0x200>; 529 interrupts = <86>; 530 ti,hwmods = "mmc2"; 531 dmas = <&sdma 47>, <&sdma 48>; 532 dma-names = "tx", "rx"; 533 }; 534 535 mmc3: mmc@480ad000 { 536 compatible = "ti,omap3-hsmmc"; 537 reg = <0x480ad000 0x200>; 538 interrupts = <94>; 539 ti,hwmods = "mmc3"; 540 dmas = <&sdma 77>, <&sdma 78>; 541 dma-names = "tx", "rx"; 542 }; 543 544 mmu_isp: mmu@480bd400 { 545 #iommu-cells = <0>; 546 compatible = "ti,omap2-iommu"; 547 reg = <0x480bd400 0x80>; 548 interrupts = <24>; 549 ti,hwmods = "mmu_isp"; 550 ti,#tlb-entries = <8>; 551 }; 552 553 mmu_iva: mmu@5d000000 { 554 #iommu-cells = <0>; 555 compatible = "ti,omap2-iommu"; 556 reg = <0x5d000000 0x80>; 557 interrupts = <28>; 558 ti,hwmods = "mmu_iva"; 559 status = "disabled"; 560 }; 561 562 wdt2: wdt@48314000 { 563 compatible = "ti,omap3-wdt"; 564 reg = <0x48314000 0x80>; 565 ti,hwmods = "wd_timer2"; 566 }; 567 568 mcbsp1: mcbsp@48074000 { 569 compatible = "ti,omap3-mcbsp"; 570 reg = <0x48074000 0xff>; 571 reg-names = "mpu"; 572 interrupts = <16>, /* OCP compliant interrupt */ 573 <59>, /* TX interrupt */ 574 <60>; /* RX interrupt */ 575 interrupt-names = "common", "tx", "rx"; 576 ti,buffer-size = <128>; 577 ti,hwmods = "mcbsp1"; 578 dmas = <&sdma 31>, 579 <&sdma 32>; 580 dma-names = "tx", "rx"; 581 clocks = <&mcbsp1_fck>; 582 clock-names = "fck"; 583 status = "disabled"; 584 }; 585 586 /* Likely needs to be tagged disabled on HS devices */ 587 rng_target: target-module@480a0000 { 588 compatible = "ti,sysc-omap2", "ti,sysc"; 589 reg = <0x480a003c 0x4>, 590 <0x480a0040 0x4>, 591 <0x480a0044 0x4>; 592 reg-names = "rev", "sysc", "syss"; 593 ti,sysc-mask = <(SYSC_OMAP2_AUTOIDLE)>; 594 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 595 <SYSC_IDLE_NO>; 596 ti,syss-mask = <1>; 597 clocks = <&rng_ick>; 598 clock-names = "ick"; 599 #address-cells = <1>; 600 #size-cells = <1>; 601 ranges = <0 0x480a0000 0x2000>; 602 603 rng: rng@0 { 604 compatible = "ti,omap2-rng"; 605 reg = <0x0 0x2000>; 606 interrupts = <52>; 607 }; 608 }; 609 610 mcbsp2: mcbsp@49022000 { 611 compatible = "ti,omap3-mcbsp"; 612 reg = <0x49022000 0xff>, 613 <0x49028000 0xff>; 614 reg-names = "mpu", "sidetone"; 615 interrupts = <17>, /* OCP compliant interrupt */ 616 <62>, /* TX interrupt */ 617 <63>, /* RX interrupt */ 618 <4>; /* Sidetone */ 619 interrupt-names = "common", "tx", "rx", "sidetone"; 620 ti,buffer-size = <1280>; 621 ti,hwmods = "mcbsp2", "mcbsp2_sidetone"; 622 dmas = <&sdma 33>, 623 <&sdma 34>; 624 dma-names = "tx", "rx"; 625 clocks = <&mcbsp2_fck>, <&mcbsp2_ick>; 626 clock-names = "fck", "ick"; 627 status = "disabled"; 628 }; 629 630 mcbsp3: mcbsp@49024000 { 631 compatible = "ti,omap3-mcbsp"; 632 reg = <0x49024000 0xff>, 633 <0x4902a000 0xff>; 634 reg-names = "mpu", "sidetone"; 635 interrupts = <22>, /* OCP compliant interrupt */ 636 <89>, /* TX interrupt */ 637 <90>, /* RX interrupt */ 638 <5>; /* Sidetone */ 639 interrupt-names = "common", "tx", "rx", "sidetone"; 640 ti,buffer-size = <128>; 641 ti,hwmods = "mcbsp3", "mcbsp3_sidetone"; 642 dmas = <&sdma 17>, 643 <&sdma 18>; 644 dma-names = "tx", "rx"; 645 clocks = <&mcbsp3_fck>, <&mcbsp3_ick>; 646 clock-names = "fck", "ick"; 647 status = "disabled"; 648 }; 649 650 mcbsp4: mcbsp@49026000 { 651 compatible = "ti,omap3-mcbsp"; 652 reg = <0x49026000 0xff>; 653 reg-names = "mpu"; 654 interrupts = <23>, /* OCP compliant interrupt */ 655 <54>, /* TX interrupt */ 656 <55>; /* RX interrupt */ 657 interrupt-names = "common", "tx", "rx"; 658 ti,buffer-size = <128>; 659 ti,hwmods = "mcbsp4"; 660 dmas = <&sdma 19>, 661 <&sdma 20>; 662 dma-names = "tx", "rx"; 663 clocks = <&mcbsp4_fck>; 664 clock-names = "fck"; 665 #sound-dai-cells = <0>; 666 status = "disabled"; 667 }; 668 669 mcbsp5: mcbsp@48096000 { 670 compatible = "ti,omap3-mcbsp"; 671 reg = <0x48096000 0xff>; 672 reg-names = "mpu"; 673 interrupts = <27>, /* OCP compliant interrupt */ 674 <81>, /* TX interrupt */ 675 <82>; /* RX interrupt */ 676 interrupt-names = "common", "tx", "rx"; 677 ti,buffer-size = <128>; 678 ti,hwmods = "mcbsp5"; 679 dmas = <&sdma 21>, 680 <&sdma 22>; 681 dma-names = "tx", "rx"; 682 clocks = <&mcbsp5_fck>; 683 clock-names = "fck"; 684 status = "disabled"; 685 }; 686 687 sham: sham@480c3000 { 688 compatible = "ti,omap3-sham"; 689 ti,hwmods = "sham"; 690 reg = <0x480c3000 0x64>; 691 interrupts = <49>; 692 dmas = <&sdma 69>; 693 dma-names = "rx"; 694 }; 695 696 timer1_target: target-module@48318000 { 697 compatible = "ti,sysc-omap2-timer", "ti,sysc"; 698 reg = <0x48318000 0x4>, 699 <0x48318010 0x4>, 700 <0x48318014 0x4>; 701 reg-names = "rev", "sysc", "syss"; 702 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | 703 SYSC_OMAP2_EMUFREE | 704 SYSC_OMAP2_ENAWAKEUP | 705 SYSC_OMAP2_SOFTRESET | 706 SYSC_OMAP2_AUTOIDLE)>; 707 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 708 <SYSC_IDLE_NO>, 709 <SYSC_IDLE_SMART>; 710 ti,syss-mask = <1>; 711 clocks = <&gpt1_fck>, <&gpt1_ick>; 712 clock-names = "fck", "ick"; 713 #address-cells = <1>; 714 #size-cells = <1>; 715 ranges = <0x0 0x48318000 0x1000>; 716 717 timer1: timer@0 { 718 compatible = "ti,omap3430-timer"; 719 reg = <0x0 0x80>; 720 clocks = <&gpt1_fck>; 721 clock-names = "fck"; 722 interrupts = <37>; 723 ti,timer-alwon; 724 }; 725 }; 726 727 timer2_target: target-module@49032000 { 728 compatible = "ti,sysc-omap2-timer", "ti,sysc"; 729 reg = <0x49032000 0x4>, 730 <0x49032010 0x4>, 731 <0x49032014 0x4>; 732 reg-names = "rev", "sysc", "syss"; 733 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | 734 SYSC_OMAP2_EMUFREE | 735 SYSC_OMAP2_ENAWAKEUP | 736 SYSC_OMAP2_SOFTRESET | 737 SYSC_OMAP2_AUTOIDLE)>; 738 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 739 <SYSC_IDLE_NO>, 740 <SYSC_IDLE_SMART>; 741 ti,syss-mask = <1>; 742 clocks = <&gpt2_fck>, <&gpt2_ick>; 743 clock-names = "fck", "ick"; 744 #address-cells = <1>; 745 #size-cells = <1>; 746 ranges = <0x0 0x49032000 0x1000>; 747 748 timer2: timer@0 { 749 compatible = "ti,omap3430-timer"; 750 reg = <0 0x400>; 751 interrupts = <38>; 752 }; 753 }; 754 755 timer3: timer@49034000 { 756 compatible = "ti,omap3430-timer"; 757 reg = <0x49034000 0x400>; 758 interrupts = <39>; 759 ti,hwmods = "timer3"; 760 }; 761 762 timer4: timer@49036000 { 763 compatible = "ti,omap3430-timer"; 764 reg = <0x49036000 0x400>; 765 interrupts = <40>; 766 ti,hwmods = "timer4"; 767 }; 768 769 timer5: timer@49038000 { 770 compatible = "ti,omap3430-timer"; 771 reg = <0x49038000 0x400>; 772 interrupts = <41>; 773 ti,hwmods = "timer5"; 774 ti,timer-dsp; 775 }; 776 777 timer6: timer@4903a000 { 778 compatible = "ti,omap3430-timer"; 779 reg = <0x4903a000 0x400>; 780 interrupts = <42>; 781 ti,hwmods = "timer6"; 782 ti,timer-dsp; 783 }; 784 785 timer7: timer@4903c000 { 786 compatible = "ti,omap3430-timer"; 787 reg = <0x4903c000 0x400>; 788 interrupts = <43>; 789 ti,hwmods = "timer7"; 790 ti,timer-dsp; 791 }; 792 793 timer8: timer@4903e000 { 794 compatible = "ti,omap3430-timer"; 795 reg = <0x4903e000 0x400>; 796 interrupts = <44>; 797 ti,hwmods = "timer8"; 798 ti,timer-pwm; 799 ti,timer-dsp; 800 }; 801 802 timer9: timer@49040000 { 803 compatible = "ti,omap3430-timer"; 804 reg = <0x49040000 0x400>; 805 interrupts = <45>; 806 ti,hwmods = "timer9"; 807 ti,timer-pwm; 808 }; 809 810 timer10: timer@48086000 { 811 compatible = "ti,omap3430-timer"; 812 reg = <0x48086000 0x400>; 813 interrupts = <46>; 814 ti,hwmods = "timer10"; 815 ti,timer-pwm; 816 }; 817 818 timer11: timer@48088000 { 819 compatible = "ti,omap3430-timer"; 820 reg = <0x48088000 0x400>; 821 interrupts = <47>; 822 ti,hwmods = "timer11"; 823 ti,timer-pwm; 824 }; 825 826 timer12_target: target-module@48304000 { 827 compatible = "ti,sysc-omap2-timer", "ti,sysc"; 828 reg = <0x48304000 0x4>, 829 <0x48304010 0x4>, 830 <0x48304014 0x4>; 831 reg-names = "rev", "sysc", "syss"; 832 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | 833 SYSC_OMAP2_EMUFREE | 834 SYSC_OMAP2_ENAWAKEUP | 835 SYSC_OMAP2_SOFTRESET | 836 SYSC_OMAP2_AUTOIDLE)>; 837 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 838 <SYSC_IDLE_NO>, 839 <SYSC_IDLE_SMART>; 840 ti,syss-mask = <1>; 841 clocks = <&gpt12_fck>, <&gpt12_ick>; 842 clock-names = "fck", "ick"; 843 #address-cells = <1>; 844 #size-cells = <1>; 845 ranges = <0x0 0x48304000 0x1000>; 846 847 timer12: timer@0 { 848 compatible = "ti,omap3430-timer"; 849 reg = <0 0x400>; 850 interrupts = <95>; 851 ti,timer-alwon; 852 ti,timer-secure; 853 }; 854 }; 855 856 usbhstll: usbhstll@48062000 { 857 compatible = "ti,usbhs-tll"; 858 reg = <0x48062000 0x1000>; 859 interrupts = <78>; 860 ti,hwmods = "usb_tll_hs"; 861 }; 862 863 usbhshost: usbhshost@48064000 { 864 compatible = "ti,usbhs-host"; 865 reg = <0x48064000 0x400>; 866 ti,hwmods = "usb_host_hs"; 867 #address-cells = <1>; 868 #size-cells = <1>; 869 ranges; 870 871 usbhsohci: ohci@48064400 { 872 compatible = "ti,ohci-omap3"; 873 reg = <0x48064400 0x400>; 874 interrupts = <76>; 875 remote-wakeup-connected; 876 }; 877 878 usbhsehci: ehci@48064800 { 879 compatible = "ti,ehci-omap"; 880 reg = <0x48064800 0x400>; 881 interrupts = <77>; 882 }; 883 }; 884 885 gpmc: gpmc@6e000000 { 886 compatible = "ti,omap3430-gpmc"; 887 ti,hwmods = "gpmc"; 888 reg = <0x6e000000 0x02d0>; 889 interrupts = <20>; 890 dmas = <&sdma 4>; 891 dma-names = "rxtx"; 892 gpmc,num-cs = <8>; 893 gpmc,num-waitpins = <4>; 894 #address-cells = <2>; 895 #size-cells = <1>; 896 interrupt-controller; 897 #interrupt-cells = <2>; 898 gpio-controller; 899 #gpio-cells = <2>; 900 }; 901 902 usb_otg_hs: usb_otg_hs@480ab000 { 903 compatible = "ti,omap3-musb"; 904 reg = <0x480ab000 0x1000>; 905 interrupts = <92>, <93>; 906 interrupt-names = "mc", "dma"; 907 ti,hwmods = "usb_otg_hs"; 908 multipoint = <1>; 909 num-eps = <16>; 910 ram-bits = <12>; 911 }; 912 913 dss: dss@48050000 { 914 compatible = "ti,omap3-dss"; 915 reg = <0x48050000 0x200>; 916 status = "disabled"; 917 ti,hwmods = "dss_core"; 918 clocks = <&dss1_alwon_fck>; 919 clock-names = "fck"; 920 #address-cells = <1>; 921 #size-cells = <1>; 922 ranges; 923 924 dispc@48050400 { 925 compatible = "ti,omap3-dispc"; 926 reg = <0x48050400 0x400>; 927 interrupts = <25>; 928 ti,hwmods = "dss_dispc"; 929 clocks = <&dss1_alwon_fck>; 930 clock-names = "fck"; 931 }; 932 933 dsi: encoder@4804fc00 { 934 compatible = "ti,omap3-dsi"; 935 reg = <0x4804fc00 0x200>, 936 <0x4804fe00 0x40>, 937 <0x4804ff00 0x20>; 938 reg-names = "proto", "phy", "pll"; 939 interrupts = <25>; 940 status = "disabled"; 941 ti,hwmods = "dss_dsi1"; 942 clocks = <&dss1_alwon_fck>, <&dss2_alwon_fck>; 943 clock-names = "fck", "sys_clk"; 944 945 #address-cells = <1>; 946 #size-cells = <0>; 947 }; 948 949 rfbi: encoder@48050800 { 950 compatible = "ti,omap3-rfbi"; 951 reg = <0x48050800 0x100>; 952 status = "disabled"; 953 ti,hwmods = "dss_rfbi"; 954 clocks = <&dss1_alwon_fck>, <&dss_ick>; 955 clock-names = "fck", "ick"; 956 }; 957 958 venc: encoder@48050c00 { 959 compatible = "ti,omap3-venc"; 960 reg = <0x48050c00 0x100>; 961 status = "disabled"; 962 ti,hwmods = "dss_venc"; 963 clocks = <&dss_tv_fck>; 964 clock-names = "fck"; 965 }; 966 }; 967 968 ssi: ssi-controller@48058000 { 969 compatible = "ti,omap3-ssi"; 970 ti,hwmods = "ssi"; 971 972 status = "disabled"; 973 974 reg = <0x48058000 0x1000>, 975 <0x48059000 0x1000>; 976 reg-names = "sys", 977 "gdd"; 978 979 interrupts = <71>; 980 interrupt-names = "gdd_mpu"; 981 982 #address-cells = <1>; 983 #size-cells = <1>; 984 ranges; 985 986 ssi_port1: ssi-port@4805a000 { 987 compatible = "ti,omap3-ssi-port"; 988 989 reg = <0x4805a000 0x800>, 990 <0x4805a800 0x800>; 991 reg-names = "tx", 992 "rx"; 993 994 interrupts = <67>, 995 <68>; 996 }; 997 998 ssi_port2: ssi-port@4805b000 { 999 compatible = "ti,omap3-ssi-port"; 1000 1001 reg = <0x4805b000 0x800>, 1002 <0x4805b800 0x800>; 1003 reg-names = "tx", 1004 "rx"; 1005 1006 interrupts = <69>, 1007 <70>; 1008 }; 1009 }; 1010 }; 1011}; 1012 1013#include "omap3xxx-clocks.dtsi" 1014 1015/* Preferred always-on timer for clockevent. Some boards must use dmtimer12 */ 1016&timer1_target { 1017 ti,no-reset-on-init; 1018 ti,no-idle; 1019 timer@0 { 1020 assigned-clocks = <&gpt1_fck>; 1021 assigned-clock-parents = <&omap_32k_fck>; 1022 }; 1023}; 1024
