1ARM Virtual Generic Interrupt Controller v3 and later (VGICv3)
2==============================================================
3
4
5Device types supported:
6  KVM_DEV_TYPE_ARM_VGIC_V3     ARM Generic Interrupt Controller v3.0
7
8Only one VGIC instance may be instantiated through this API.  The created VGIC
9will act as the VM interrupt controller, requiring emulated user-space devices
10to inject interrupts to the VGIC instead of directly to CPUs.  It is not
11possible to create both a GICv3 and GICv2 on the same VM.
12
13Creating a guest GICv3 device requires a host GICv3 as well.
14
15
16Groups:
17  KVM_DEV_ARM_VGIC_GRP_ADDR
18  Attributes:
19    KVM_VGIC_V3_ADDR_TYPE_DIST (rw, 64-bit)
20      Base address in the guest physical address space of the GICv3 distributor
21      register mappings. Only valid for KVM_DEV_TYPE_ARM_VGIC_V3.
22      This address needs to be 64K aligned and the region covers 64 KByte.
23
24    KVM_VGIC_V3_ADDR_TYPE_REDIST (rw, 64-bit)
25      Base address in the guest physical address space of the GICv3
26      redistributor register mappings. There are two 64K pages for each
27      VCPU and all of the redistributor pages are contiguous.
28      Only valid for KVM_DEV_TYPE_ARM_VGIC_V3.
29      This address needs to be 64K aligned.
30
31    KVM_VGIC_V3_ADDR_TYPE_REDIST_REGION (rw, 64-bit)
32      The attribute data pointed to by kvm_device_attr.addr is a __u64 value:
33      bits:     | 63   ....  52  |  51   ....   16 | 15 - 12  |11 - 0
34      values:   |     count      |       base      |  flags   | index
35      - index encodes the unique redistributor region index
36      - flags: reserved for future use, currently 0
37      - base field encodes bits [51:16] of the guest physical base address
38        of the first redistributor in the region.
39      - count encodes the number of redistributors in the region. Must be
40        greater than 0.
41      There are two 64K pages for each redistributor in the region and
42      redistributors are laid out contiguously within the region. Regions
43      are filled with redistributors in the index order. The sum of all
44      region count fields must be greater than or equal to the number of
45      VCPUs. Redistributor regions must be registered in the incremental
46      index order, starting from index 0.
47      The characteristics of a specific redistributor region can be read
48      by presetting the index field in the attr data.
49      Only valid for KVM_DEV_TYPE_ARM_VGIC_V3.
50
51  It is invalid to mix calls with KVM_VGIC_V3_ADDR_TYPE_REDIST and
52  KVM_VGIC_V3_ADDR_TYPE_REDIST_REGION attributes.
53
54  Errors:
55    -E2BIG:  Address outside of addressable IPA range
56    -EINVAL: Incorrectly aligned address, bad redistributor region
57             count/index, mixed redistributor region attribute usage
58    -EEXIST: Address already configured
59    -ENOENT: Attempt to read the characteristics of a non existing
60             redistributor region
61    -ENXIO:  The group or attribute is unknown/unsupported for this device
62             or hardware support is missing.
63    -EFAULT: Invalid user pointer for attr->addr.
64
65
66  KVM_DEV_ARM_VGIC_GRP_DIST_REGS
67  KVM_DEV_ARM_VGIC_GRP_REDIST_REGS
68  Attributes:
69    The attr field of kvm_device_attr encodes two values:
70    bits:     | 63   ....  32  |  31   ....    0 |
71    values:   |      mpidr     |      offset     |
72
73    All distributor regs are (rw, 32-bit) and kvm_device_attr.addr points to a
74    __u32 value.  64-bit registers must be accessed by separately accessing the
75    lower and higher word.
76
77    Writes to read-only registers are ignored by the kernel.
78
79    KVM_DEV_ARM_VGIC_GRP_DIST_REGS accesses the main distributor registers.
80    KVM_DEV_ARM_VGIC_GRP_REDIST_REGS accesses the redistributor of the CPU
81    specified by the mpidr.
82
83    The offset is relative to the "[Re]Distributor base address" as defined
84    in the GICv3/4 specs.  Getting or setting such a register has the same
85    effect as reading or writing the register on real hardware, except for the
86    following registers: GICD_STATUSR, GICR_STATUSR, GICD_ISPENDR,
87    GICR_ISPENDR0, GICD_ICPENDR, and GICR_ICPENDR0.  These registers behave
88    differently when accessed via this interface compared to their
89    architecturally defined behavior to allow software a full view of the
90    VGIC's internal state.
91
92    The mpidr field is used to specify which
93    redistributor is accessed.  The mpidr is ignored for the distributor.
94
95    The mpidr encoding is based on the affinity information in the
96    architecture defined MPIDR, and the field is encoded as follows:
97      | 63 .... 56 | 55 .... 48 | 47 .... 40 | 39 .... 32 |
98      |    Aff3    |    Aff2    |    Aff1    |    Aff0    |
99
100    Note that distributor fields are not banked, but return the same value
101    regardless of the mpidr used to access the register.
102
103    GICD_IIDR.Revision is updated when the KVM implementation is changed in a
104    way directly observable by the guest or userspace.  Userspace should read
105    GICD_IIDR from KVM and write back the read value to confirm its expected
106    behavior is aligned with the KVM implementation.  Userspace should set
107    GICD_IIDR before setting any other registers to ensure the expected
108    behavior.
109
110
111    The GICD_STATUSR and GICR_STATUSR registers are architecturally defined such
112    that a write of a clear bit has no effect, whereas a write with a set bit
113    clears that value.  To allow userspace to freely set the values of these two
114    registers, setting the attributes with the register offsets for these two
115    registers simply sets the non-reserved bits to the value written.
116
117
118    Accesses (reads and writes) to the GICD_ISPENDR register region and
119    GICR_ISPENDR0 registers get/set the value of the latched pending state for
120    the interrupts.
121
122    This is identical to the value returned by a guest read from ISPENDR for an
123    edge triggered interrupt, but may differ for level triggered interrupts.
124    For edge triggered interrupts, once an interrupt becomes pending (whether
125    because of an edge detected on the input line or because of a guest write
126    to ISPENDR) this state is "latched", and only cleared when either the
127    interrupt is activated or when the guest writes to ICPENDR. A level
128    triggered interrupt may be pending either because the level input is held
129    high by a device, or because of a guest write to the ISPENDR register. Only
130    ISPENDR writes are latched; if the device lowers the line level then the
131    interrupt is no longer pending unless the guest also wrote to ISPENDR, and
132    conversely writes to ICPENDR or activations of the interrupt do not clear
133    the pending status if the line level is still being held high.  (These
134    rules are documented in the GICv3 specification descriptions of the ICPENDR
135    and ISPENDR registers.) For a level triggered interrupt the value accessed
136    here is that of the latch which is set by ISPENDR and cleared by ICPENDR or
137    interrupt activation, whereas the value returned by a guest read from
138    ISPENDR is the logical OR of the latch value and the input line level.
139
140    Raw access to the latch state is provided to userspace so that it can save
141    and restore the entire GIC internal state (which is defined by the
142    combination of the current input line level and the latch state, and cannot
143    be deduced from purely the line level and the value of the ISPENDR
144    registers).
145
146    Accesses to GICD_ICPENDR register region and GICR_ICPENDR0 registers have
147    RAZ/WI semantics, meaning that reads always return 0 and writes are always
148    ignored.
149
150  Errors:
151    -ENXIO: Getting or setting this register is not yet supported
152    -EBUSY: One or more VCPUs are running
153
154
155  KVM_DEV_ARM_VGIC_GRP_CPU_SYSREGS
156  Attributes:
157    The attr field of kvm_device_attr encodes two values:
158    bits:     | 63      ....       32 | 31  ....  16 | 15  ....  0 |
159    values:   |         mpidr         |      RES     |    instr    |
160
161    The mpidr field encodes the CPU ID based on the affinity information in the
162    architecture defined MPIDR, and the field is encoded as follows:
163      | 63 .... 56 | 55 .... 48 | 47 .... 40 | 39 .... 32 |
164      |    Aff3    |    Aff2    |    Aff1    |    Aff0    |
165
166    The instr field encodes the system register to access based on the fields
167    defined in the A64 instruction set encoding for system register access
168    (RES means the bits are reserved for future use and should be zero):
169
170      | 15 ... 14 | 13 ... 11 | 10 ... 7 | 6 ... 3 | 2 ... 0 |
171      |   Op 0    |    Op1    |    CRn   |   CRm   |   Op2   |
172
173    All system regs accessed through this API are (rw, 64-bit) and
174    kvm_device_attr.addr points to a __u64 value.
175
176    KVM_DEV_ARM_VGIC_GRP_CPU_SYSREGS accesses the CPU interface registers for the
177    CPU specified by the mpidr field.
178
179    CPU interface registers access is not implemented for AArch32 mode.
180    Error -ENXIO is returned when accessed in AArch32 mode.
181  Errors:
182    -ENXIO: Getting or setting this register is not yet supported
183    -EBUSY: VCPU is running
184    -EINVAL: Invalid mpidr or register value supplied
185
186
187  KVM_DEV_ARM_VGIC_GRP_NR_IRQS
188  Attributes:
189    A value describing the number of interrupts (SGI, PPI and SPI) for
190    this GIC instance, ranging from 64 to 1024, in increments of 32.
191
192    kvm_device_attr.addr points to a __u32 value.
193
194  Errors:
195    -EINVAL: Value set is out of the expected range
196    -EBUSY: Value has already be set.
197
198
199  KVM_DEV_ARM_VGIC_GRP_CTRL
200  Attributes:
201    KVM_DEV_ARM_VGIC_CTRL_INIT
202      request the initialization of the VGIC, no additional parameter in
203      kvm_device_attr.addr.
204    KVM_DEV_ARM_VGIC_SAVE_PENDING_TABLES
205      save all LPI pending bits into guest RAM pending tables.
206
207      The first kB of the pending table is not altered by this operation.
208  Errors:
209    -ENXIO: VGIC not properly configured as required prior to calling
210     this attribute
211    -ENODEV: no online VCPU
212    -ENOMEM: memory shortage when allocating vgic internal data
213    -EFAULT: Invalid guest ram access
214    -EBUSY:  One or more VCPUS are running
215
216
217  KVM_DEV_ARM_VGIC_GRP_LEVEL_INFO
218  Attributes:
219    The attr field of kvm_device_attr encodes the following values:
220    bits:     | 63      ....       32 | 31   ....    10 | 9  ....  0 |
221    values:   |         mpidr         |      info       |   vINTID   |
222
223    The vINTID specifies which set of IRQs is reported on.
224
225    The info field specifies which information userspace wants to get or set
226    using this interface.  Currently we support the following info values:
227
228      VGIC_LEVEL_INFO_LINE_LEVEL:
229	Get/Set the input level of the IRQ line for a set of 32 contiguously
230	numbered interrupts.
231	vINTID must be a multiple of 32.
232
233	kvm_device_attr.addr points to a __u32 value which will contain a
234	bitmap where a set bit means the interrupt level is asserted.
235
236	Bit[n] indicates the status for interrupt vINTID + n.
237
238    SGIs and any interrupt with a higher ID than the number of interrupts
239    supported, will be RAZ/WI.  LPIs are always edge-triggered and are
240    therefore not supported by this interface.
241
242    PPIs are reported per VCPU as specified in the mpidr field, and SPIs are
243    reported with the same value regardless of the mpidr specified.
244
245    The mpidr field encodes the CPU ID based on the affinity information in the
246    architecture defined MPIDR, and the field is encoded as follows:
247      | 63 .... 56 | 55 .... 48 | 47 .... 40 | 39 .... 32 |
248      |    Aff3    |    Aff2    |    Aff1    |    Aff0    |
249  Errors:
250    -EINVAL: vINTID is not multiple of 32 or
251     info field is not VGIC_LEVEL_INFO_LINE_LEVEL
252