1.. include:: <isonum.txt> 2 3Qualcomm Camera Subsystem driver 4================================ 5 6Introduction 7------------ 8 9This file documents the Qualcomm Camera Subsystem driver located under 10drivers/media/platform/qcom/camss. 11 12The current version of the driver supports the Camera Subsystem found on 13Qualcomm MSM8916/APQ8016 and MSM8996/APQ8096 processors. 14 15The driver implements V4L2, Media controller and V4L2 subdev interfaces. 16Camera sensor using V4L2 subdev interface in the kernel is supported. 17 18The driver is implemented using as a reference the Qualcomm Camera Subsystem 19driver for Android as found in Code Aurora [#f1]_ [#f2]_. 20 21 22Qualcomm Camera Subsystem hardware 23---------------------------------- 24 25The Camera Subsystem hardware found on 8x16 / 8x96 processors and supported by 26the driver consists of: 27 28- 2 / 3 CSIPHY modules. They handle the Physical layer of the CSI2 receivers. 29 A separate camera sensor can be connected to each of the CSIPHY module; 30- 2 / 4 CSID (CSI Decoder) modules. They handle the Protocol and Application 31 layer of the CSI2 receivers. A CSID can decode data stream from any of the 32 CSIPHY. Each CSID also contains a TG (Test Generator) block which can generate 33 artificial input data for test purposes; 34- ISPIF (ISP Interface) module. Handles the routing of the data streams from 35 the CSIDs to the inputs of the VFE; 36- 1 / 2 VFE (Video Front End) module(s). Contain a pipeline of image processing 37 hardware blocks. The VFE has different input interfaces. The PIX (Pixel) input 38 interface feeds the input data to the image processing pipeline. The image 39 processing pipeline contains also a scale and crop module at the end. Three 40 RDI (Raw Dump Interface) input interfaces bypass the image processing 41 pipeline. The VFE also contains the AXI bus interface which writes the output 42 data to memory. 43 44 45Supported functionality 46----------------------- 47 48The current version of the driver supports: 49 50- Input from camera sensor via CSIPHY; 51- Generation of test input data by the TG in CSID; 52- RDI interface of VFE 53 54 - Raw dump of the input data to memory. 55 56 Supported formats: 57 58 - YUYV/UYVY/YVYU/VYUY (packed YUV 4:2:2 - V4L2_PIX_FMT_YUYV / 59 V4L2_PIX_FMT_UYVY / V4L2_PIX_FMT_YVYU / V4L2_PIX_FMT_VYUY); 60 - MIPI RAW8 (8bit Bayer RAW - V4L2_PIX_FMT_SRGGB8 / 61 V4L2_PIX_FMT_SGRBG8 / V4L2_PIX_FMT_SGBRG8 / V4L2_PIX_FMT_SBGGR8); 62 - MIPI RAW10 (10bit packed Bayer RAW - V4L2_PIX_FMT_SBGGR10P / 63 V4L2_PIX_FMT_SGBRG10P / V4L2_PIX_FMT_SGRBG10P / V4L2_PIX_FMT_SRGGB10P / 64 V4L2_PIX_FMT_Y10P); 65 - MIPI RAW12 (12bit packed Bayer RAW - V4L2_PIX_FMT_SRGGB12P / 66 V4L2_PIX_FMT_SGBRG12P / V4L2_PIX_FMT_SGRBG12P / V4L2_PIX_FMT_SRGGB12P). 67 - (8x96 only) MIPI RAW14 (14bit packed Bayer RAW - V4L2_PIX_FMT_SRGGB14P / 68 V4L2_PIX_FMT_SGBRG14P / V4L2_PIX_FMT_SGRBG14P / V4L2_PIX_FMT_SRGGB14P). 69 70 - (8x96 only) Format conversion of the input data. 71 72 Supported input formats: 73 74 - MIPI RAW10 (10bit packed Bayer RAW - V4L2_PIX_FMT_SBGGR10P / V4L2_PIX_FMT_Y10P). 75 76 Supported output formats: 77 78 - Plain16 RAW10 (10bit unpacked Bayer RAW - V4L2_PIX_FMT_SBGGR10 / V4L2_PIX_FMT_Y10). 79 80- PIX interface of VFE 81 82 - Format conversion of the input data. 83 84 Supported input formats: 85 86 - YUYV/UYVY/YVYU/VYUY (packed YUV 4:2:2 - V4L2_PIX_FMT_YUYV / 87 V4L2_PIX_FMT_UYVY / V4L2_PIX_FMT_YVYU / V4L2_PIX_FMT_VYUY). 88 89 Supported output formats: 90 91 - NV12/NV21 (two plane YUV 4:2:0 - V4L2_PIX_FMT_NV12 / V4L2_PIX_FMT_NV21); 92 - NV16/NV61 (two plane YUV 4:2:2 - V4L2_PIX_FMT_NV16 / V4L2_PIX_FMT_NV61). 93 - (8x96 only) YUYV/UYVY/YVYU/VYUY (packed YUV 4:2:2 - V4L2_PIX_FMT_YUYV / 94 V4L2_PIX_FMT_UYVY / V4L2_PIX_FMT_YVYU / V4L2_PIX_FMT_VYUY). 95 96 - Scaling support. Configuration of the VFE Encoder Scale module 97 for downscalling with ratio up to 16x. 98 99 - Cropping support. Configuration of the VFE Encoder Crop module. 100 101- Concurrent and independent usage of two (8x96: three) data inputs - 102 could be camera sensors and/or TG. 103 104 105Driver Architecture and Design 106------------------------------ 107 108The driver implements the V4L2 subdev interface. With the goal to model the 109hardware links between the modules and to expose a clean, logical and usable 110interface, the driver is split into V4L2 sub-devices as follows (8x16 / 8x96): 111 112- 2 / 3 CSIPHY sub-devices - each CSIPHY is represented by a single sub-device; 113- 2 / 4 CSID sub-devices - each CSID is represented by a single sub-device; 114- 2 / 4 ISPIF sub-devices - ISPIF is represented by a number of sub-devices 115 equal to the number of CSID sub-devices; 116- 4 / 8 VFE sub-devices - VFE is represented by a number of sub-devices equal to 117 the number of the input interfaces (3 RDI and 1 PIX for each VFE). 118 119The considerations to split the driver in this particular way are as follows: 120 121- representing CSIPHY and CSID modules by a separate sub-device for each module 122 allows to model the hardware links between these modules; 123- representing VFE by a separate sub-devices for each input interface allows 124 to use the input interfaces concurently and independently as this is 125 supported by the hardware; 126- representing ISPIF by a number of sub-devices equal to the number of CSID 127 sub-devices allows to create linear media controller pipelines when using two 128 cameras simultaneously. This avoids branches in the pipelines which otherwise 129 will require a) userspace and b) media framework (e.g. power on/off 130 operations) to make assumptions about the data flow from a sink pad to a 131 source pad on a single media entity. 132 133Each VFE sub-device is linked to a separate video device node. 134 135The media controller pipeline graph is as follows (with connected two / three 136OV5645 camera sensors): 137 138.. _qcom_camss_graph: 139 140.. kernel-figure:: qcom_camss_graph.dot 141 :alt: qcom_camss_graph.dot 142 :align: center 143 144 Media pipeline graph 8x16 145 146.. kernel-figure:: qcom_camss_8x96_graph.dot 147 :alt: qcom_camss_8x96_graph.dot 148 :align: center 149 150 Media pipeline graph 8x96 151 152 153Implementation 154-------------- 155 156Runtime configuration of the hardware (updating settings while streaming) is 157not required to implement the currently supported functionality. The complete 158configuration on each hardware module is applied on STREAMON ioctl based on 159the current active media links, formats and controls set. 160 161The output size of the scaler module in the VFE is configured with the actual 162compose selection rectangle on the sink pad of the 'msm_vfe0_pix' entity. 163 164The crop output area of the crop module in the VFE is configured with the actual 165crop selection rectangle on the source pad of the 'msm_vfe0_pix' entity. 166 167 168Documentation 169------------- 170 171APQ8016 Specification: 172https://developer.qualcomm.com/download/sd410/snapdragon-410-processor-device-specification.pdf 173Referenced 2016-11-24. 174 175APQ8096 Specification: 176https://developer.qualcomm.com/download/sd820e/qualcomm-snapdragon-820e-processor-apq8096sge-device-specification.pdf 177Referenced 2018-06-22. 178 179References 180---------- 181 182.. [#f1] https://source.codeaurora.org/quic/la/kernel/msm-3.10/ 183.. [#f2] https://source.codeaurora.org/quic/la/kernel/msm-3.18/ 184
