1Driver i2c-mlxcpld
2
3Author: Michael Shych <michaelsh@mellanox.com>
4
5This is the Mellanox I2C controller logic, implemented in Lattice CPLD
6device.
7Device supports:
8 - Master mode.
9 - One physical bus.
10 - Polling mode.
11
12This controller is equipped within the next Mellanox systems:
13"msx6710", "msx6720", "msb7700", "msn2700", "msx1410", "msn2410", "msb7800",
14"msn2740", "msn2100".
15
16The next transaction types are supported:
17 - Receive Byte/Block.
18 - Send Byte/Block.
19 - Read Byte/Block.
20 - Write Byte/Block.
21
22Registers:
23CPBLTY		0x0 - capability reg.
24			Bits [6:5] - transaction length. b01 - 72B is supported,
25			36B in other case.
26			Bit 7 - SMBus block read support.
27CTRL		0x1 - control reg.
28			Resets all the registers.
29HALF_CYC	0x4 - cycle reg.
30			Configure the width of I2C SCL half clock cycle (in 4 LPC_CLK
31			units).
32I2C_HOLD	0x5 - hold reg.
33			OE (output enable) is delayed by value set to this register
34			(in LPC_CLK units)
35CMD			0x6 - command reg.
36			Bit 0, 0 = write, 1 = read.
37			Bits [7:1] - the 7bit Address of the I2C device.
38			It should be written last as it triggers an I2C transaction.
39NUM_DATA	0x7 - data size reg.
40			Number of data bytes to write in read transaction
41NUM_ADDR	0x8 - address reg.
42			Number of address bytes to write in read transaction.
43STATUS		0x9 - status reg.
44			Bit 0 - transaction is completed.
45			Bit 4 - ACK/NACK.
46DATAx		0xa - 0x54  - 68 bytes data buffer regs.
47			For write transaction address is specified in four first bytes
48			(DATA1 - DATA4), data starting from DATA4.
49			For read transactions address is sent in a separate transaction and
50			specified in the four first bytes (DATA0 - DATA3). Data is read
51			starting from DATA0.
52