1Samsung GPIO and Pin Mux/Config controller 2 3Samsung's ARM based SoC's integrates a GPIO and Pin mux/config hardware 4controller. It controls the input/output settings on the available pads/pins 5and also provides ability to multiplex and configure the output of various 6on-chip controllers onto these pads. 7 8Required Properties: 9- compatible: should be one of the following. 10 - "samsung,s3c2412-pinctrl": for S3C2412-compatible pin-controller, 11 - "samsung,s3c2416-pinctrl": for S3C2416-compatible pin-controller, 12 - "samsung,s3c2440-pinctrl": for S3C2440-compatible pin-controller, 13 - "samsung,s3c2450-pinctrl": for S3C2450-compatible pin-controller, 14 - "samsung,s3c64xx-pinctrl": for S3C64xx-compatible pin-controller, 15 - "samsung,s5pv210-pinctrl": for S5PV210-compatible pin-controller, 16 - "samsung,exynos3250-pinctrl": for Exynos3250 compatible pin-controller. 17 - "samsung,exynos4210-pinctrl": for Exynos4210 compatible pin-controller. 18 - "samsung,exynos4x12-pinctrl": for Exynos4x12 compatible pin-controller. 19 - "samsung,exynos5250-pinctrl": for Exynos5250 compatible pin-controller. 20 - "samsung,exynos5260-pinctrl": for Exynos5260 compatible pin-controller. 21 - "samsung,exynos5410-pinctrl": for Exynos5410 compatible pin-controller. 22 - "samsung,exynos5420-pinctrl": for Exynos5420 compatible pin-controller. 23 - "samsung,exynos5433-pinctrl": for Exynos5433 compatible pin-controller. 24 - "samsung,exynos7-pinctrl": for Exynos7 compatible pin-controller. 25 - "samsung,exynos850-pinctrl": for Exynos850 compatible pin-controller. 26 27- reg: Base address of the pin controller hardware module and length of 28 the address space it occupies. 29 30 - reg: Second base address of the pin controller if the specific registers 31 of the pin controller are separated into the different base address. 32 33 Eg: GPF[1-5] of Exynos5433 are separated into the two base address. 34 - First base address is for GPAx and GPF[1-5] external interrupt 35 registers. 36 - Second base address is for GPF[1-5] pinctrl registers. 37 38 pinctrl_0: pinctrl@10580000 { 39 compatible = "samsung,exynos5433-pinctrl"; 40 reg = <0x10580000 0x1a20>, <0x11090000 0x100>; 41 42 wakeup-interrupt-controller { 43 compatible = "samsung,exynos7-wakeup-eint"; 44 interrupts = <0 16 0>; 45 }; 46 }; 47 48- Pin banks as child nodes: Pin banks of the controller are represented by child 49 nodes of the controller node. Bank name is taken from name of the node. Each 50 bank node must contain following properties: 51 52 - gpio-controller: identifies the node as a gpio controller and pin bank. 53 - #gpio-cells: number of cells in GPIO specifier. Since the generic GPIO 54 binding is used, the amount of cells must be specified as 2. See the below 55 mentioned gpio binding representation for description of particular cells. 56 57 Eg: <&gpx2 6 0> 58 <[phandle of the gpio controller node] 59 [pin number within the gpio controller] 60 [flags]> 61 62 Values for gpio specifier: 63 - Pin number: is a value between 0 to 7. 64 - Flags: 0 - Active High 65 1 - Active Low 66 67- Pin mux/config groups as child nodes: The pin mux (selecting pin function 68 mode) and pin config (pull up/down, driver strength) settings are represented 69 as child nodes of the pin-controller node. There should be at least one 70 child node and there is no limit on the count of these child nodes. It is 71 also possible for a child node to consist of several further child nodes 72 to allow grouping multiple pinctrl groups into one. The format of second 73 level child nodes is exactly the same as for first level ones and is 74 described below. 75 76 The child node should contain a list of pin(s) on which a particular pin 77 function selection or pin configuration (or both) have to applied. This 78 list of pins is specified using the property name "samsung,pins". There 79 should be at least one pin specified for this property and there is no upper 80 limit on the count of pins that can be specified. The pins are specified 81 using pin names which are derived from the hardware manual of the SoC. As 82 an example, the pins in GPA0 bank of the pin controller can be represented 83 as "gpa0-0", "gpa0-1", "gpa0-2" and so on. The names should be in lower case. 84 The format of the pin names should be (as per the hardware manual) 85 "[pin bank name]-[pin number within the bank]". 86 87 The pin function selection that should be applied on the pins listed in the 88 child node is specified using the "samsung,pin-function" property. The value 89 of this property that should be applied to each of the pins listed in the 90 "samsung,pins" property should be picked from the hardware manual of the SoC 91 for the specified pin group. This property is optional in the child node if 92 no specific function selection is desired for the pins listed in the child 93 node. The value of this property is used as-is to program the pin-controller 94 function selector register of the pin-bank. 95 96 The child node can also optionally specify one or more of the pin 97 configuration that should be applied on all the pins listed in the 98 "samsung,pins" property of the child node. The following pin configuration 99 properties are supported. 100 101 - samsung,pin-val: Initial value of pin output buffer. 102 - samsung,pin-pud: Pull up/down configuration. 103 - samsung,pin-drv: Drive strength configuration. 104 - samsung,pin-pud-pdn: Pull up/down configuration in power down mode. 105 - samsung,pin-drv-pdn: Drive strength configuration in power down mode. 106 107 The values specified by these config properties should be derived from the 108 hardware manual and these values are programmed as-is into the pin 109 pull up/down and driver strength register of the pin-controller. 110 111 Note: A child should include at least a pin function selection property or 112 pin configuration property (one or more) or both. 113 114 The client nodes that require a particular pin function selection and/or 115 pin configuration should use the bindings listed in the "pinctrl-bindings.txt" 116 file. 117 118External GPIO and Wakeup Interrupts: 119 120The controller supports two types of external interrupts over gpio. The first 121is the external gpio interrupt and second is the external wakeup interrupts. 122The difference between the two is that the external wakeup interrupts can be 123used as system wakeup events. 124 125A. External GPIO Interrupts: For supporting external gpio interrupts, the 126 following properties should be specified in the pin-controller device node. 127 128 - interrupts: interrupt specifier for the controller. The format and value of 129 the interrupt specifier depends on the interrupt parent for the controller. 130 131 In addition, following properties must be present in node of every bank 132 of pins supporting GPIO interrupts: 133 134 - interrupt-controller: identifies the controller node as interrupt-parent. 135 - #interrupt-cells: the value of this property should be 2. 136 - First Cell: represents the external gpio interrupt number local to the 137 external gpio interrupt space of the controller. 138 - Second Cell: flags to identify the type of the interrupt 139 - 1 = rising edge triggered 140 - 2 = falling edge triggered 141 - 3 = rising and falling edge triggered 142 - 4 = high level triggered 143 - 8 = low level triggered 144 145B. External Wakeup Interrupts: For supporting external wakeup interrupts, a 146 child node representing the external wakeup interrupt controller should be 147 included in the pin-controller device node. 148 149 Only one pin-controller device node can include external wakeup interrupts 150 child node (in other words, only one External Wakeup Interrupts 151 pin-controller is supported). 152 153 This child node should include following properties: 154 155 - compatible: identifies the type of the external wakeup interrupt controller 156 The possible values are: 157 - samsung,s3c2410-wakeup-eint: represents wakeup interrupt controller 158 found on Samsung S3C24xx SoCs except S3C2412 and S3C2413, 159 - samsung,s3c2412-wakeup-eint: represents wakeup interrupt controller 160 found on Samsung S3C2412 and S3C2413 SoCs, 161 - samsung,s3c64xx-wakeup-eint: represents wakeup interrupt controller 162 found on Samsung S3C64xx SoCs, 163 - samsung,s5pv210-wakeup-eint: represents wakeup interrupt controller 164 found on Samsung S5Pv210 SoCs, 165 - samsung,exynos4210-wakeup-eint: represents wakeup interrupt controller 166 found on Samsung Exynos4210 and S5PC110/S5PV210 SoCs. 167 - samsung,exynos7-wakeup-eint: represents wakeup interrupt controller 168 found on Samsung Exynos7 SoC. 169 - interrupts: interrupt used by multiplexed wakeup interrupts. 170 171 In addition, following properties must be present in node of every bank 172 of pins supporting wake-up interrupts: 173 174 - interrupt-controller: identifies the node as interrupt-parent. 175 - #interrupt-cells: the value of this property should be 2 176 - First Cell: represents the external wakeup interrupt number local to 177 the external wakeup interrupt space of the controller. 178 - Second Cell: flags to identify the type of the interrupt 179 - 1 = rising edge triggered 180 - 2 = falling edge triggered 181 - 3 = rising and falling edge triggered 182 - 4 = high level triggered 183 - 8 = low level triggered 184 185 Node of every bank of pins supporting direct wake-up interrupts (without 186 multiplexing) must contain following properties: 187 188 - interrupts: interrupts of the interrupt parent which are used for external 189 wakeup interrupts from pins of the bank, must contain interrupts for all 190 pins of the bank. 191 192Aliases: 193 194All the pin controller nodes should be represented in the aliases node using 195the following format 'pinctrl{n}' where n is a unique number for the alias. 196 197Aliases for controllers compatible with "samsung,exynos7-pinctrl": 198- pinctrl0: pin controller of ALIVE block, 199- pinctrl1: pin controller of BUS0 block, 200- pinctrl2: pin controller of NFC block, 201- pinctrl3: pin controller of TOUCH block, 202- pinctrl4: pin controller of FF block, 203- pinctrl5: pin controller of ESE block, 204- pinctrl6: pin controller of FSYS0 block, 205- pinctrl7: pin controller of FSYS1 block, 206- pinctrl8: pin controller of BUS1 block, 207- pinctrl9: pin controller of AUDIO block, 208 209Example: A pin-controller node with pin banks: 210 211 pinctrl_0: pinctrl@11400000 { 212 compatible = "samsung,exynos4210-pinctrl"; 213 reg = <0x11400000 0x1000>; 214 interrupts = <0 47 0>; 215 216 /* ... */ 217 218 /* Pin bank without external interrupts */ 219 gpy0: gpy0 { 220 gpio-controller; 221 #gpio-cells = <2>; 222 }; 223 224 /* ... */ 225 226 /* Pin bank with external GPIO or muxed wake-up interrupts */ 227 gpj0: gpj0 { 228 gpio-controller; 229 #gpio-cells = <2>; 230 231 interrupt-controller; 232 #interrupt-cells = <2>; 233 }; 234 235 /* ... */ 236 237 /* Pin bank with external direct wake-up interrupts */ 238 gpx0: gpx0 { 239 gpio-controller; 240 #gpio-cells = <2>; 241 242 interrupt-controller; 243 interrupt-parent = <&gic>; 244 interrupts = <0 16 0>, <0 17 0>, <0 18 0>, <0 19 0>, 245 <0 20 0>, <0 21 0>, <0 22 0>, <0 23 0>; 246 #interrupt-cells = <2>; 247 }; 248 249 /* ... */ 250 }; 251 252Example 1: A pin-controller node with pin groups. 253 254 #include <dt-bindings/pinctrl/samsung.h> 255 256 pinctrl_0: pinctrl@11400000 { 257 compatible = "samsung,exynos4210-pinctrl"; 258 reg = <0x11400000 0x1000>; 259 interrupts = <0 47 0>; 260 261 /* ... */ 262 263 uart0_data: uart0-data { 264 samsung,pins = "gpa0-0", "gpa0-1"; 265 samsung,pin-function = <EXYNOS_PIN_FUNC_2>; 266 samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; 267 samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; 268 }; 269 270 uart0_fctl: uart0-fctl { 271 samsung,pins = "gpa0-2", "gpa0-3"; 272 samsung,pin-function = <EXYNOS_PIN_FUNC_2>; 273 samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; 274 samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; 275 }; 276 277 uart1_data: uart1-data { 278 samsung,pins = "gpa0-4", "gpa0-5"; 279 samsung,pin-function = <EXYNOS_PIN_FUNC_2>; 280 samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; 281 samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; 282 }; 283 284 uart1_fctl: uart1-fctl { 285 samsung,pins = "gpa0-6", "gpa0-7"; 286 samsung,pin-function = <EXYNOS_PIN_FUNC_2>; 287 samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; 288 samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; 289 }; 290 291 i2c2_bus: i2c2-bus { 292 samsung,pins = "gpa0-6", "gpa0-7"; 293 samsung,pin-function = <EXYNOS_PIN_FUNC_3>; 294 samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; 295 samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; 296 }; 297 298 sd4_bus8: sd4-bus-width8 { 299 part-1 { 300 samsung,pins = "gpk0-3", "gpk0-4", 301 "gpk0-5", "gpk0-6"; 302 samsung,pin-function = <EXYNOS_PIN_FUNC_3>; 303 samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; 304 samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; 305 }; 306 part-2 { 307 samsung,pins = "gpk1-3", "gpk1-4", 308 "gpk1-5", "gpk1-6"; 309 samsung,pin-function = <EXYNOS_PIN_FUNC_4>; 310 samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; 311 samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>; 312 }; 313 }; 314 }; 315 316Example 2: A pin-controller node with external wakeup interrupt controller node. 317 318 pinctrl_1: pinctrl@11000000 { 319 compatible = "samsung,exynos4210-pinctrl"; 320 reg = <0x11000000 0x1000>; 321 interrupts = <0 46 0> 322 323 /* ... */ 324 325 wakeup-interrupt-controller { 326 compatible = "samsung,exynos4210-wakeup-eint"; 327 interrupt-parent = <&gic>; 328 interrupts = <0 32 0>; 329 }; 330 }; 331 332Example 3: A uart client node that supports 'default' and 'flow-control' states. 333 334 uart@13800000 { 335 compatible = "samsung,exynos4210-uart"; 336 reg = <0x13800000 0x100>; 337 interrupts = <0 52 0>; 338 pinctrl-names = "default", "flow-control; 339 pinctrl-0 = <&uart0_data>; 340 pinctrl-1 = <&uart0_data>, <&uart0_fctl>; 341 }; 342 343Example 4: Set up the default pin state for uart controller. 344 345 static int s3c24xx_serial_probe(struct platform_device *pdev) { 346 struct pinctrl *pinctrl; 347 348 /* ... */ 349 350 pinctrl = devm_pinctrl_get_select_default(&pdev->dev); 351 } 352 353Example 5: A display port client node that supports 'default' pinctrl state 354 and gpio binding. 355 356 display-port-controller { 357 /* ... */ 358 359 samsung,hpd-gpio = <&gpx2 6 0>; 360 pinctrl-names = "default"; 361 pinctrl-0 = <&dp_hpd>; 362 }; 363 364Example 6: Request the gpio for display port controller 365 366 static int exynos_dp_probe(struct platform_device *pdev) 367 { 368 int hpd_gpio, ret; 369 struct device *dev = &pdev->dev; 370 struct device_node *dp_node = dev->of_node; 371 372 /* ... */ 373 374 hpd_gpio = of_get_named_gpio(dp_node, "samsung,hpd-gpio", 0); 375 376 /* ... */ 377 378 ret = devm_gpio_request_one(&pdev->dev, hpd_gpio, GPIOF_IN, 379 "hpd_gpio"); 380 /* ... */ 381 } 382
