1* Mediatek MT65XX Pin Controller
2
3The Mediatek's Pin controller is used to control SoC pins.
4
5Required properties:
6- compatible: value should be one of the following.
7	"mediatek,mt2701-pinctrl", compatible with mt2701 pinctrl.
8	"mediatek,mt2712-pinctrl", compatible with mt2712 pinctrl.
9	"mediatek,mt6397-pinctrl", compatible with mt6397 pinctrl.
10	"mediatek,mt7623-pinctrl", compatible with mt7623 pinctrl.
11	"mediatek,mt8127-pinctrl", compatible with mt8127 pinctrl.
12	"mediatek,mt8135-pinctrl", compatible with mt8135 pinctrl.
13	"mediatek,mt8173-pinctrl", compatible with mt8173 pinctrl.
14- pins-are-numbered: Specify the subnodes are using numbered pinmux to
15  specify pins.
16- gpio-controller : Marks the device node as a gpio controller.
17- #gpio-cells: number of cells in GPIO specifier. Since the generic GPIO
18  binding is used, the amount of cells must be specified as 2. See the below
19  mentioned gpio binding representation for description of particular cells.
20
21	Eg: <&pio 6 0>
22	<[phandle of the gpio controller node]
23	[line number within the gpio controller]
24	[flags]>
25
26	Values for gpio specifier:
27	- Line number: is a value between 0 to 202.
28	- Flags:  bit field of flags, as defined in <dt-bindings/gpio/gpio.h>.
29            Only the following flags are supported:
30            0 - GPIO_ACTIVE_HIGH
31            1 - GPIO_ACTIVE_LOW
32
33Optional properties:
34- mediatek,pctl-regmap: Should be a phandle of the syscfg node.
35- reg: physicall address base for EINT registers
36- interrupt-controller: Marks the device node as an interrupt controller
37- #interrupt-cells: Should be two.
38- interrupts : The interrupt outputs from the controller.
39
40Please refer to pinctrl-bindings.txt in this directory for details of the
41common pinctrl bindings used by client devices.
42
43Subnode format
44A pinctrl node should contain at least one subnodes representing the
45pinctrl groups available on the machine. Each subnode will list the
46pins it needs, and how they should be configured, with regard to muxer
47configuration, pullups, drive strength, input enable/disable and input schmitt.
48
49    node {
50	pinmux = <PIN_NUMBER_PINMUX>;
51	GENERIC_PINCONFIG;
52    };
53
54Required properties:
55- pinmux: integer array, represents gpio pin number and mux setting.
56    Supported pin number and mux varies for different SoCs, and are defined
57    as macros in boot/dts/<soc>-pinfunc.h directly.
58
59Optional properties:
60- GENERIC_PINCONFIG: is the generic pinconfig options to use, bias-disable,
61    bias-pull-down, bias-pull-up, input-enable, input-disable, output-low, output-high,
62    input-schmitt-enable, input-schmitt-disable and drive-strength are valid.
63
64    Some special pins have extra pull up strength, there are R0 and R1 pull-up
65    resistors available, but for user, it's only need to set R1R0 as 00, 01, 10 or 11.
66    So when config bias-pull-up, it support arguments for those special pins.
67    Some macros have been defined for this usage, such as MTK_PUPD_SET_R1R0_00.
68    See dt-bindings/pinctrl/mt65xx.h.
69
70    When config drive-strength, it can support some arguments, such as
71    MTK_DRIVE_4mA, MTK_DRIVE_6mA, etc. See dt-bindings/pinctrl/mt65xx.h.
72
73Examples:
74
75#include "mt8135-pinfunc.h"
76
77...
78{
79	syscfg_pctl_a: syscfg-pctl-a@10005000 {
80		compatible = "mediatek,mt8135-pctl-a-syscfg", "syscon";
81		reg = <0 0x10005000 0 0x1000>;
82	};
83
84	syscfg_pctl_b: syscfg-pctl-b@1020c020 {
85		compatible = "mediatek,mt8135-pctl-b-syscfg", "syscon";
86		reg = <0 0x1020C020 0 0x1000>;
87	};
88
89	pinctrl@1c20800 {
90		compatible = "mediatek,mt8135-pinctrl";
91		reg = <0 0x1000B000 0 0x1000>;
92		mediatek,pctl-regmap = <&syscfg_pctl_a &syscfg_pctl_b>;
93		pins-are-numbered;
94		gpio-controller;
95		#gpio-cells = <2>;
96		interrupt-controller;
97		#interrupt-cells = <2>;
98		interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
99				<GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
100				<GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
101
102		i2c0_pins_a: i2c0@0 {
103			pins1 {
104				pinmux = <MT8135_PIN_100_SDA0__FUNC_SDA0>,
105					 <MT8135_PIN_101_SCL0__FUNC_SCL0>;
106				bias-disable;
107			};
108		};
109
110		i2c1_pins_a: i2c1@0 {
111			pins {
112				pinmux = <MT8135_PIN_195_SDA1__FUNC_SDA1>,
113					 <MT8135_PIN_196_SCL1__FUNC_SCL1>;
114				bias-pull-up = <55>;
115			};
116		};
117
118		i2c2_pins_a: i2c2@0 {
119			pins1 {
120				pinmux = <MT8135_PIN_193_SDA2__FUNC_SDA2>;
121				bias-pull-down;
122			};
123
124			pins2 {
125				pinmux = <MT8135_PIN_49_WATCHDOG__FUNC_GPIO49>;
126				bias-pull-up;
127			};
128		};
129
130		i2c3_pins_a: i2c3@0 {
131			pins1 {
132				pinmux = <MT8135_PIN_40_DAC_CLK__FUNC_GPIO40>,
133					 <MT8135_PIN_41_DAC_WS__FUNC_GPIO41>;
134				bias-pull-up = <55>;
135			};
136
137			pins2 {
138				pinmux = <MT8135_PIN_35_SCL3__FUNC_SCL3>,
139					 <MT8135_PIN_36_SDA3__FUNC_SDA3>;
140				output-low;
141				bias-pull-up = <55>;
142			};
143
144			pins3 {
145				pinmux = <MT8135_PIN_57_JTCK__FUNC_GPIO57>,
146					 <MT8135_PIN_60_JTDI__FUNC_JTDI>;
147				drive-strength = <32>;
148			};
149		};
150
151		...
152	}
153};
154