1TI PCI Controllers
2
3PCIe DesignWare Controller
4 - compatible: Should be "ti,dra7-pcie" for RC
5	       Should be "ti,dra7-pcie-ep" for EP
6 - phys : list of PHY specifiers (used by generic PHY framework)
7 - phy-names : must be "pcie-phy0", "pcie-phy1", "pcie-phyN".. based on the
8	       number of PHYs as specified in *phys* property.
9 - ti,hwmods : Name of the hwmod associated to the pcie, "pcie<X>",
10	       where <X> is the instance number of the pcie from the HW spec.
11 - num-lanes as specified in ../designware-pcie.txt
12
13HOST MODE
14=========
15 - reg : Two register ranges as listed in the reg-names property
16 - reg-names : The first entry must be "ti-conf" for the TI-specific registers
17	       The second entry must be "rc-dbics" for the DesignWare PCIe
18	       registers
19	       The third entry must be "config" for the PCIe configuration space
20 - interrupts : Two interrupt entries must be specified. The first one is for
21		main interrupt line and the second for MSI interrupt line.
22 - #address-cells,
23   #size-cells,
24   #interrupt-cells,
25   device_type,
26   ranges,
27   interrupt-map-mask,
28   interrupt-map : as specified in ../designware-pcie.txt
29
30DEVICE MODE
31===========
32 - reg : Four register ranges as listed in the reg-names property
33 - reg-names : "ti-conf" for the TI-specific registers
34	       "ep_dbics" for the standard configuration registers as
35		they are locally accessed within the DIF CS space
36	       "ep_dbics2" for the standard configuration registers as
37		they are locally accessed within the DIF CS2 space
38	       "addr_space" used to map remote RC address space
39 - interrupts : one interrupt entries must be specified for main interrupt.
40 - num-ib-windows : number of inbound address translation windows
41 - num-ob-windows : number of outbound address translation windows
42 - ti,syscon-unaligned-access: phandle to the syscon DT node. The 1st argument
43			       should contain the register offset within syscon
44			       and the 2nd argument should contain the bit field
45			       for setting the bit to enable unaligned
46			       access.
47
48Optional Property:
49 - gpios : Should be added if a GPIO line is required to drive PERST# line
50
51NOTE: Two DT nodes may be added for each PCI controller; one for host
52mode and another for device mode. So in order for PCI to
53work in host mode, EP mode DT node should be disabled and in order to PCI to
54work in EP mode, host mode DT node should be disabled. Host mode and EP
55mode are mutually exclusive.
56
57Example:
58axi {
59	compatible = "simple-bus";
60	#size-cells = <1>;
61	#address-cells = <1>;
62	ranges = <0x51000000 0x51000000 0x3000
63		  0x0	     0x20000000 0x10000000>;
64	pcie@51000000 {
65		compatible = "ti,dra7-pcie";
66		reg = <0x51000000 0x2000>, <0x51002000 0x14c>, <0x1000 0x2000>;
67		reg-names = "rc_dbics", "ti_conf", "config";
68		interrupts = <0 232 0x4>, <0 233 0x4>;
69		#address-cells = <3>;
70		#size-cells = <2>;
71		device_type = "pci";
72		ranges = <0x81000000 0 0          0x03000 0 0x00010000
73			  0x82000000 0 0x20013000 0x13000 0 0xffed000>;
74		#interrupt-cells = <1>;
75		num-lanes = <1>;
76		ti,hwmods = "pcie1";
77		phys = <&pcie1_phy>;
78		phy-names = "pcie-phy0";
79		interrupt-map-mask = <0 0 0 7>;
80		interrupt-map = <0 0 0 1 &pcie_intc 1>,
81				<0 0 0 2 &pcie_intc 2>,
82				<0 0 0 3 &pcie_intc 3>,
83				<0 0 0 4 &pcie_intc 4>;
84		pcie_intc: interrupt-controller {
85			interrupt-controller;
86			#address-cells = <0>;
87			#interrupt-cells = <1>;
88		};
89	};
90};
91