1HiSilicon Hip05 and Hip06 PCIe host bridge DT description
2
3HiSilicon PCIe host controller is based on the Synopsys DesignWare PCI core.
4It shares common functions with the PCIe DesignWare core driver and inherits
5common properties defined in
6Documentation/devicetree/bindings/pci/designware-pcie.txt.
7
8Additional properties are described here:
9
10Required properties
11- compatible: Should contain "hisilicon,hip05-pcie" or "hisilicon,hip06-pcie".
12- reg: Should contain rc_dbi, config registers location and length.
13- reg-names: Must include the following entries:
14  "rc_dbi": controller configuration registers;
15  "config": PCIe configuration space registers.
16- msi-parent: Should be its_pcie which is an ITS receiving MSI interrupts.
17- port-id: Should be 0, 1, 2 or 3.
18
19Optional properties:
20- status: Either "ok" or "disabled".
21- dma-coherent: Present if DMA operations are coherent.
22
23Hip05 Example (note that Hip06 is the same except compatible):
24	pcie@b0080000 {
25		compatible = "hisilicon,hip05-pcie", "snps,dw-pcie";
26		reg = <0 0xb0080000 0 0x10000>, <0x220 0x00000000 0 0x2000>;
27		reg-names = "rc_dbi", "config";
28		bus-range = <0  15>;
29		msi-parent = <&its_pcie>;
30		#address-cells = <3>;
31		#size-cells = <2>;
32		device_type = "pci";
33		dma-coherent;
34		ranges = <0x82000000 0 0x00000000 0x220 0x00000000 0 0x10000000>;
35		num-lanes = <8>;
36		port-id = <1>;
37		#interrupt-cells = <1>;
38		interrupt-map-mask = <0xf800 0 0 7>;
39		interrupt-map = <0x0 0 0 1 &mbigen_pcie 1 10
40				 0x0 0 0 2 &mbigen_pcie 2 11
41				 0x0 0 0 3 &mbigen_pcie 3 12
42				 0x0 0 0 4 &mbigen_pcie 4 13>;
43	};
44
45HiSilicon Hip06/Hip07 PCIe host bridge DT (almost-ECAM) description.
46
47Some BIOSes place the host controller in a mode where it is ECAM
48compliant for all devices other than the root complex. In such cases,
49the host controller should be described as below.
50
51The properties and their meanings are identical to those described in
52host-generic-pci.txt except as listed below.
53
54Properties of the host controller node that differ from
55host-generic-pci.txt:
56
57- compatible     : Must be "hisilicon,hip06-pcie-ecam", or
58		   "hisilicon,hip07-pcie-ecam"
59
60- reg            : Two entries: First the ECAM configuration space for any
61		   other bus underneath the root bus. Second, the base
62		   and size of the HiSilicon host bridge registers include
63		   the RC's own config space.
64
65Example:
66	pcie0: pcie@a0090000 {
67		compatible = "hisilicon,hip06-pcie-ecam";
68		reg = <0 0xb0000000 0 0x2000000>,  /*  ECAM configuration space */
69		      <0 0xa0090000 0 0x10000>; /* host bridge registers */
70		bus-range = <0  31>;
71		msi-map = <0x0000 &its_dsa 0x0000 0x2000>;
72		msi-map-mask = <0xffff>;
73		#address-cells = <3>;
74		#size-cells = <2>;
75		device_type = "pci";
76		dma-coherent;
77		ranges = <0x02000000 0 0xb2000000 0x0 0xb2000000 0 0x5ff0000
78			  0x01000000 0 0 0 0xb7ff0000 0 0x10000>;
79		#interrupt-cells = <1>;
80		interrupt-map-mask = <0xf800 0 0 7>;
81		interrupt-map = <0x0 0 0 1 &mbigen_pcie0 650 4
82				 0x0 0 0 2 &mbigen_pcie0 650 4
83				 0x0 0 0 3 &mbigen_pcie0 650 4
84				 0x0 0 0 4 &mbigen_pcie0 650 4>;
85	};
86