1* Synopsys DesignWare PCIe interface
2
3Required properties:
4- compatible:
5	"snps,dw-pcie" for RC mode;
6	"snps,dw-pcie-ep" for EP mode;
7- reg: Should contain the configuration address space.
8- reg-names: Must be "config" for the PCIe configuration space.
9    (The old way of getting the configuration address space from "ranges"
10    is deprecated and should be avoided.)
11- num-lanes: number of lanes to use
12RC mode:
13- #address-cells: set to <3>
14- #size-cells: set to <2>
15- device_type: set to "pci"
16- ranges: ranges for the PCI memory and I/O regions
17- #interrupt-cells: set to <1>
18- interrupt-map-mask and interrupt-map: standard PCI
19	properties to define the mapping of the PCIe interface to interrupt
20	numbers.
21EP mode:
22- num-ib-windows: number of inbound address translation windows
23- num-ob-windows: number of outbound address translation windows
24
25Optional properties:
26- num-lanes: number of lanes to use (this property should be specified unless
27  the link is brought already up in BIOS)
28- reset-gpio: GPIO pin number of power good signal
29- clocks: Must contain an entry for each entry in clock-names.
30	See ../clocks/clock-bindings.txt for details.
31- clock-names: Must include the following entries:
32	- "pcie"
33	- "pcie_bus"
34RC mode:
35- num-viewport: number of view ports configured in hardware. If a platform
36  does not specify it, the driver assumes 2.
37- bus-range: PCI bus numbers covered (it is recommended for new devicetrees
38  to specify this property, to keep backwards compatibility a range of
39  0x00-0xff is assumed if not present)
40
41EP mode:
42- max-functions: maximum number of functions that can be configured
43
44Example configuration:
45
46	pcie: pcie@dfc00000 {
47		compatible = "snps,dw-pcie";
48		reg = <0xdfc00000 0x0001000>, /* IP registers */
49		      <0xd0000000 0x0002000>; /* Configuration space */
50		reg-names = "dbi", "config";
51		#address-cells = <3>;
52		#size-cells = <2>;
53		device_type = "pci";
54		ranges = <0x81000000 0 0x00000000 0xde000000 0 0x00010000
55			  0x82000000 0 0xd0400000 0xd0400000 0 0x0d000000>;
56		interrupts = <25>, <24>;
57		#interrupt-cells = <1>;
58		num-lanes = <1>;
59	};
60or
61	pcie: pcie@dfc00000 {
62		compatible = "snps,dw-pcie-ep";
63		reg = <0xdfc00000 0x0001000>, /* IP registers 1 */
64		      <0xdfc01000 0x0001000>, /* IP registers 2 */
65		      <0xd0000000 0x2000000>; /* Configuration space */
66		reg-names = "dbi", "dbi2", "addr_space";
67		num-ib-windows = <6>;
68		num-ob-windows = <2>;
69		num-lanes = <1>;
70	};
71