1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/opp/opp-v2-kryo-cpu.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm Technologies, Inc. NVMEM OPP
8
9maintainers:
10  - Ilia Lin <ilia.lin@kernel.org>
11
12allOf:
13  - $ref: opp-v2-base.yaml#
14
15description: |
16  In certain Qualcomm Technologies, Inc. SoCs like APQ8096 and MSM8996,
17  the CPU frequencies subset and voltage value of each OPP varies based on
18  the silicon variant in use.
19  Qualcomm Technologies, Inc. Process Voltage Scaling Tables
20  defines the voltage and frequency value based on the speedbin blown in
21  the efuse combination.
22  The qcom-cpufreq-nvmem driver reads the efuse value from the SoC to provide
23  the OPP framework with required information (existing HW bitmap).
24  This is used to determine the voltage and frequency value for each OPP of
25  operating-points-v2 table when it is parsed by the OPP framework.
26
27properties:
28  compatible:
29    const: operating-points-v2-kryo-cpu
30
31  nvmem-cells:
32    description: |
33      A phandle pointing to a nvmem-cells node representing the
34      efuse registers that has information about the
35      speedbin that is used to select the right frequency/voltage
36      value pair.
37
38  opp-shared: true
39
40patternProperties:
41  '^opp-?[0-9]+$':
42    type: object
43    additionalProperties: false
44
45    properties:
46      opp-hz: true
47
48      opp-microvolt: true
49
50      opp-supported-hw:
51        description: |
52          A single 32 bit bitmap value, representing compatible HW.
53          Bitmap for MSM8996 format:
54          0:  MSM8996, speedbin 0
55          1:  MSM8996, speedbin 1
56          2:  MSM8996, speedbin 2
57          3:  MSM8996, speedbin 3
58          4-31:  unused
59
60          Bitmap for MSM8996SG format (speedbin shifted of 4 left):
61          0-3:  unused
62          4:  MSM8996SG, speedbin 0
63          5:  MSM8996SG, speedbin 1
64          6:  MSM8996SG, speedbin 2
65          7-31:  unused
66        enum: [0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7,
67               0x9, 0xd, 0xe, 0xf,
68               0x10, 0x20, 0x30, 0x70]
69
70      clock-latency-ns: true
71
72      required-opps: true
73
74    required:
75      - opp-hz
76
77required:
78  - compatible
79
80if:
81  required:
82    - nvmem-cells
83then:
84  patternProperties:
85    '^opp-?[0-9]+$':
86      required:
87        - opp-supported-hw
88
89additionalProperties: false
90
91examples:
92  - |
93    / {
94        model = "Qualcomm Technologies, Inc. DB820c";
95        compatible = "arrow,apq8096-db820c", "qcom,apq8096-sbc", "qcom,apq8096";
96        #address-cells = <2>;
97        #size-cells = <2>;
98
99        cpus {
100            #address-cells = <2>;
101            #size-cells = <0>;
102
103            CPU0: cpu@0 {
104                device_type = "cpu";
105                compatible = "qcom,kryo";
106                reg = <0x0 0x0>;
107                enable-method = "psci";
108                cpu-idle-states = <&CPU_SLEEP_0>;
109                capacity-dmips-mhz = <1024>;
110                clocks = <&kryocc 0>;
111                operating-points-v2 = <&cluster0_opp>;
112                power-domains = <&cpr>;
113                power-domain-names = "cpr";
114                #cooling-cells = <2>;
115                next-level-cache = <&L2_0>;
116                L2_0: l2-cache {
117                    compatible = "cache";
118                    cache-level = <2>;
119                    cache-unified;
120                };
121            };
122
123            CPU1: cpu@1 {
124                device_type = "cpu";
125                compatible = "qcom,kryo";
126                reg = <0x0 0x1>;
127                enable-method = "psci";
128                cpu-idle-states = <&CPU_SLEEP_0>;
129                capacity-dmips-mhz = <1024>;
130                clocks = <&kryocc 0>;
131                operating-points-v2 = <&cluster0_opp>;
132                power-domains = <&cpr>;
133                power-domain-names = "cpr";
134                #cooling-cells = <2>;
135                next-level-cache = <&L2_0>;
136            };
137
138            CPU2: cpu@100 {
139                device_type = "cpu";
140                compatible = "qcom,kryo";
141                reg = <0x0 0x100>;
142                enable-method = "psci";
143                cpu-idle-states = <&CPU_SLEEP_0>;
144                capacity-dmips-mhz = <1024>;
145                clocks = <&kryocc 1>;
146                operating-points-v2 = <&cluster1_opp>;
147                power-domains = <&cpr>;
148                power-domain-names = "cpr";
149                #cooling-cells = <2>;
150                next-level-cache = <&L2_1>;
151                L2_1: l2-cache {
152                    compatible = "cache";
153                    cache-level = <2>;
154                    cache-unified;
155                };
156            };
157
158            CPU3: cpu@101 {
159                device_type = "cpu";
160                compatible = "qcom,kryo";
161                reg = <0x0 0x101>;
162                enable-method = "psci";
163                cpu-idle-states = <&CPU_SLEEP_0>;
164                capacity-dmips-mhz = <1024>;
165                clocks = <&kryocc 1>;
166                operating-points-v2 = <&cluster1_opp>;
167                power-domains = <&cpr>;
168                power-domain-names = "cpr";
169                #cooling-cells = <2>;
170                next-level-cache = <&L2_1>;
171            };
172
173            cpu-map {
174                cluster0 {
175                    core0 {
176                        cpu = <&CPU0>;
177                    };
178
179                    core1 {
180                        cpu = <&CPU1>;
181                    };
182                };
183
184                cluster1 {
185                    core0 {
186                        cpu = <&CPU2>;
187                    };
188
189                    core1 {
190                        cpu = <&CPU3>;
191                    };
192                };
193            };
194        };
195
196        cluster0_opp: opp-table-0 {
197            compatible = "operating-points-v2-kryo-cpu";
198            nvmem-cells = <&speedbin_efuse>;
199            opp-shared;
200
201            opp-307200000 {
202                opp-hz = /bits/ 64 <307200000>;
203                opp-microvolt = <905000 905000 1140000>;
204                opp-supported-hw = <0x7>;
205                clock-latency-ns = <200000>;
206                required-opps = <&cpr_opp1>;
207            };
208            opp-1401600000 {
209                opp-hz = /bits/ 64 <1401600000>;
210                opp-microvolt = <1140000 905000 1140000>;
211                opp-supported-hw = <0x5>;
212                clock-latency-ns = <200000>;
213                required-opps = <&cpr_opp2>;
214            };
215            opp-1593600000 {
216                opp-hz = /bits/ 64 <1593600000>;
217                opp-microvolt = <1140000 905000 1140000>;
218                opp-supported-hw = <0x1>;
219                clock-latency-ns = <200000>;
220                required-opps = <&cpr_opp3>;
221            };
222        };
223
224        cluster1_opp: opp-table-1 {
225            compatible = "operating-points-v2-kryo-cpu";
226            nvmem-cells = <&speedbin_efuse>;
227            opp-shared;
228
229            opp-307200000 {
230                opp-hz = /bits/ 64 <307200000>;
231                opp-microvolt = <905000 905000 1140000>;
232                opp-supported-hw = <0x7>;
233                clock-latency-ns = <200000>;
234                required-opps = <&cpr_opp1>;
235            };
236            opp-1804800000 {
237                opp-hz = /bits/ 64 <1804800000>;
238                opp-microvolt = <1140000 905000 1140000>;
239                opp-supported-hw = <0x6>;
240                clock-latency-ns = <200000>;
241                required-opps = <&cpr_opp4>;
242            };
243            opp-1900800000 {
244                opp-hz = /bits/ 64 <1900800000>;
245                opp-microvolt = <1140000 905000 1140000>;
246                opp-supported-hw = <0x4>;
247                clock-latency-ns = <200000>;
248                required-opps = <&cpr_opp5>;
249            };
250            opp-2150400000 {
251                opp-hz = /bits/ 64 <2150400000>;
252                opp-microvolt = <1140000 905000 1140000>;
253                opp-supported-hw = <0x1>;
254                clock-latency-ns = <200000>;
255                required-opps = <&cpr_opp6>;
256            };
257        };
258
259        smem {
260            compatible = "qcom,smem";
261            memory-region = <&smem_mem>;
262            hwlocks = <&tcsr_mutex 3>;
263        };
264
265        soc {
266            #address-cells = <1>;
267            #size-cells = <1>;
268
269            qfprom: qfprom@74000 {
270                compatible = "qcom,msm8996-qfprom", "qcom,qfprom";
271                reg = <0x00074000 0x8ff>;
272                #address-cells = <1>;
273                #size-cells = <1>;
274
275                speedbin_efuse: speedbin@133 {
276                    reg = <0x133 0x1>;
277                    bits = <5 3>;
278                };
279            };
280        };
281    };
282