1* Renesas Electronics SH EtherMAC
2
3This file provides information on what the device node for the SH EtherMAC
4interface contains.
5
6Required properties:
7- compatible: Must contain one or more of the following:
8	      "renesas,gether-r8a7740" if the device is a part of R8A7740 SoC.
9	      "renesas,ether-r8a7743"  if the device is a part of R8A7743 SoC.
10	      "renesas,ether-r8a7745"  if the device is a part of R8A7745 SoC.
11	      "renesas,ether-r8a7778"  if the device is a part of R8A7778 SoC.
12	      "renesas,ether-r8a7779"  if the device is a part of R8A7779 SoC.
13	      "renesas,ether-r8a7790"  if the device is a part of R8A7790 SoC.
14	      "renesas,ether-r8a7791"  if the device is a part of R8A7791 SoC.
15	      "renesas,ether-r8a7793"  if the device is a part of R8A7793 SoC.
16	      "renesas,ether-r8a7794"  if the device is a part of R8A7794 SoC.
17	      "renesas,gether-r8a77980" if the device is a part of R8A77980 SoC.
18	      "renesas,ether-r7s72100" if the device is a part of R7S72100 SoC.
19	      "renesas,ether-r7s9210" if the device is a part of R7S9210 SoC.
20	      "renesas,rcar-gen1-ether" for a generic R-Car Gen1 device.
21	      "renesas,rcar-gen2-ether" for a generic R-Car Gen2 or RZ/G1
22	                                device.
23
24	      When compatible with the generic version, nodes must list
25	      the SoC-specific version corresponding to the platform
26	      first followed by the generic version.
27
28- reg: offset and length of (1) the E-DMAC/feLic register block (required),
29       (2) the TSU register block (optional).
30- interrupts: interrupt specifier for the sole interrupt.
31- phy-mode: see ethernet.txt file in the same directory.
32- phy-handle: see ethernet.txt file in the same directory.
33- #address-cells: number of address cells for the MDIO bus, must be equal to 1.
34- #size-cells: number of size cells on the MDIO bus, must be equal to 0.
35- clocks: clock phandle and specifier pair.
36- pinctrl-0: phandle, referring to a default pin configuration node.
37
38Optional properties:
39- pinctrl-names: pin configuration state name ("default").
40- renesas,no-ether-link: boolean, specify when a board does not provide a proper
41			 Ether LINK signal.
42- renesas,ether-link-active-low: boolean, specify when the Ether LINK signal is
43				 active-low instead of normal active-high.
44
45Example (Lager board):
46
47	ethernet@ee700000 {
48		compatible = "renesas,ether-r8a7790",
49		             "renesas,rcar-gen2-ether";
50		reg = <0 0xee700000 0 0x400>;
51		interrupt-parent = <&gic>;
52		interrupts = <0 162 IRQ_TYPE_LEVEL_HIGH>;
53		clocks = <&mstp8_clks R8A7790_CLK_ETHER>;
54		phy-mode = "rmii";
55		phy-handle = <&phy1>;
56		pinctrl-0 = <&ether_pins>;
57		pinctrl-names = "default";
58		renesas,ether-link-active-low;
59		#address-cells = <1>;
60		#size-cells = <0>;
61
62		phy1: ethernet-phy@1 {
63			reg = <1>;
64			interrupt-parent = <&irqc0>;
65			interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
66			pinctrl-0 = <&phy1_pins>;
67			pinctrl-names = "default";
68		};
69	};
70