1* NAND chip and NAND controller generic binding
2
3NAND controller/NAND chip representation:
4
5The NAND controller should be represented with its own DT node, and all
6NAND chips attached to this controller should be defined as children nodes
7of the NAND controller. This representation should be enforced even for
8simple controllers supporting only one chip.
9
10Mandatory NAND controller properties:
11- #address-cells: depends on your controller. Should at least be 1 to
12		  encode the CS line id.
13- #size-cells: depends on your controller. Put zero unless you need a
14	       mapping between CS lines and dedicated memory regions
15
16Optional NAND controller properties
17- ranges: only needed if you need to define a mapping between CS lines and
18	  memory regions
19
20Optional NAND chip properties:
21
22- nand-ecc-mode : String, operation mode of the NAND ecc mode.
23		  Supported values are: "none", "soft", "hw", "hw_syndrome",
24		  "hw_oob_first", "on-die".
25		  Deprecated values:
26		  "soft_bch": use "soft" and nand-ecc-algo instead
27- nand-ecc-algo: string, algorithm of NAND ECC.
28		 Valid values are: "hamming", "bch", "rs".
29- nand-bus-width : 8 or 16 bus width if not present 8
30- nand-on-flash-bbt: boolean to enable on flash bbt option if not present false
31
32- nand-ecc-strength: integer representing the number of bits to correct
33		     per ECC step.
34
35- nand-ecc-step-size: integer representing the number of data bytes
36		      that are covered by a single ECC step.
37
38- nand-ecc-maximize: boolean used to specify that you want to maximize ECC
39		     strength. The maximum ECC strength is both controller and
40		     chip dependent. The controller side has to select the ECC
41		     config providing the best strength and taking the OOB area
42		     size constraint into account.
43		     This is particularly useful when only the in-band area is
44		     used by the upper layers, and you want to make your NAND
45		     as reliable as possible.
46- nand-is-boot-medium: Whether the NAND chip is a boot medium. Drivers might use
47		       this information to select ECC algorithms supported by
48		       the boot ROM or similar restrictions.
49
50- nand-rb: shall contain the native Ready/Busy ids.
51
52The ECC strength and ECC step size properties define the correction capability
53of a controller. Together, they say a controller can correct "{strength} bit
54errors per {size} bytes".
55
56The interpretation of these parameters is implementation-defined, so not all
57implementations must support all possible combinations. However, implementations
58are encouraged to further specify the value(s) they support.
59
60Example:
61
62	nand-controller {
63		#address-cells = <1>;
64		#size-cells = <0>;
65
66		/* controller specific properties */
67
68		nand@0 {
69			reg = <0>;
70			nand-ecc-mode = "soft";
71			nand-ecc-algo = "bch";
72
73			/* controller specific properties */
74		};
75	};
76