1* MTK MMC controller
2
3The MTK  MSDC can act as a MMC controller
4to support MMC, SD, and SDIO types of memory cards.
5
6This file documents differences between the core properties in mmc.txt
7and the properties used by the msdc driver.
8
9Required properties:
10- compatible: value should be either of the following.
11	"mediatek,mt8135-mmc": for mmc host ip compatible with mt8135
12	"mediatek,mt8173-mmc": for mmc host ip compatible with mt8173
13	"mediatek,mt8183-mmc": for mmc host ip compatible with mt8183
14	"mediatek,mt8516-mmc": for mmc host ip compatible with mt8516
15	"mediatek,mt2701-mmc": for mmc host ip compatible with mt2701
16	"mediatek,mt2712-mmc": for mmc host ip compatible with mt2712
17	"mediatek,mt7622-mmc": for MT7622 SoC
18	"mediatek,mt7623-mmc", "mediatek,mt2701-mmc": for MT7623 SoC
19	"mediatek,mt7620-mmc", for MT7621 SoC (and others)
20
21- reg: physical base address of the controller and length
22- interrupts: Should contain MSDC interrupt number
23- clocks: Should contain phandle for the clock feeding the MMC controller
24- clock-names: Should contain the following:
25	"source" - source clock (required)
26	"hclk" - HCLK which used for host (required)
27	"source_cg" - independent source clock gate (required for MT2712)
28	"bus_clk" - bus clock used for internal register access (required for MT2712 MSDC0/3)
29- pinctrl-names: should be "default", "state_uhs"
30- pinctrl-0: should contain default/high speed pin ctrl
31- pinctrl-1: should contain uhs mode pin ctrl
32- vmmc-supply: power to the Core
33- vqmmc-supply: power to the IO
34
35Optional properties:
36- assigned-clocks: PLL of the source clock
37- assigned-clock-parents: parent of source clock, used for HS400 mode to get 400Mhz source clock
38- hs400-ds-delay: HS400 DS delay setting
39- mediatek,hs200-cmd-int-delay: HS200 command internal delay setting.
40				This field has total 32 stages.
41				The value is an integer from 0 to 31.
42- mediatek,hs400-cmd-int-delay: HS400 command internal delay setting
43				This field has total 32 stages.
44				The value is an integer from 0 to 31.
45- mediatek,hs400-cmd-resp-sel-rising:  HS400 command response sample selection
46				       If present,HS400 command responses are sampled on rising edges.
47				       If not present,HS400 command responses are sampled on falling edges.
48- mediatek,latch-ck: Some SoCs do not support enhance_rx, need set correct latch-ck to avoid data crc
49		     error caused by stop clock(fifo full)
50		     Valid range = [0:0x7]. if not present, default value is 0.
51		     applied to compatible "mediatek,mt2701-mmc".
52
53Examples:
54mmc0: mmc@11230000 {
55	compatible = "mediatek,mt8173-mmc", "mediatek,mt8135-mmc";
56	reg = <0 0x11230000 0 0x108>;
57	interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_LOW>;
58	vmmc-supply = <&mt6397_vemc_3v3_reg>;
59	vqmmc-supply = <&mt6397_vio18_reg>;
60	clocks = <&pericfg CLK_PERI_MSDC30_0>,
61	         <&topckgen CLK_TOP_MSDC50_0_H_SEL>;
62	clock-names = "source", "hclk";
63	pinctrl-names = "default", "state_uhs";
64	pinctrl-0 = <&mmc0_pins_default>;
65	pinctrl-1 = <&mmc0_pins_uhs>;
66	assigned-clocks = <&topckgen CLK_TOP_MSDC50_0_SEL>;
67	assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_D2>;
68	hs400-ds-delay = <0x14015>;
69	mediatek,hs200-cmd-int-delay = <26>;
70	mediatek,hs400-cmd-int-delay = <14>;
71	mediatek,hs400-cmd-resp-sel-rising;
72};
73