1Allwinner V3s Camera Sensor Interface 2------------------------------------- 3 4Allwinner V3s SoC features a CSI module(CSI1) with parallel interface. 5 6Required properties: 7 - compatible: value must be one of: 8 * "allwinner,sun6i-a31-csi" 9 * "allwinner,sun8i-a83t-csi" 10 * "allwinner,sun8i-h3-csi" 11 * "allwinner,sun8i-v3s-csi" 12 * "allwinner,sun50i-a64-csi" 13 - reg: base address and size of the memory-mapped region. 14 - interrupts: interrupt associated to this IP 15 - clocks: phandles to the clocks feeding the CSI 16 * bus: the CSI interface clock 17 * mod: the CSI module clock 18 * ram: the CSI DRAM clock 19 - clock-names: the clock names mentioned above 20 - resets: phandles to the reset line driving the CSI 21 22The CSI node should contain one 'port' child node with one child 'endpoint' 23node, according to the bindings defined in 24Documentation/devicetree/bindings/media/video-interfaces.txt. 25 26Endpoint node properties for CSI 27--------------------------------- 28See the video-interfaces.txt for a detailed description of these properties. 29- remote-endpoint : (required) a phandle to the bus receiver's endpoint 30 node 31- bus-width: : (required) must be 8, 10, 12 or 16 32- pclk-sample : (optional) (default: sample on falling edge) 33- hsync-active : (required; parallel-only) 34- vsync-active : (required; parallel-only) 35 36Example: 37 38csi1: csi@1cb4000 { 39 compatible = "allwinner,sun8i-v3s-csi"; 40 reg = <0x01cb4000 0x1000>; 41 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 42 clocks = <&ccu CLK_BUS_CSI>, 43 <&ccu CLK_CSI1_SCLK>, 44 <&ccu CLK_DRAM_CSI>; 45 clock-names = "bus", "mod", "ram"; 46 resets = <&ccu RST_BUS_CSI>; 47 48 port { 49 /* Parallel bus endpoint */ 50 csi1_ep: endpoint { 51 remote-endpoint = <&adv7611_ep>; 52 bus-width = <16>; 53 54 /* If hsync-active/vsync-active are missing, 55 embedded BT.656 sync is used */ 56 hsync-active = <0>; /* Active low */ 57 vsync-active = <0>; /* Active low */ 58 pclk-sample = <1>; /* Rising */ 59 }; 60 }; 61}; 62