1* Synopsys DesignWare APB GPIO controller
2
3Required properties:
4- compatible : Should contain "snps,dw-apb-gpio"
5- reg : Address and length of the register set for the device.
6- #address-cells : should be 1 (for addressing port subnodes).
7- #size-cells : should be 0 (port subnodes).
8
9The GPIO controller has a configurable number of ports, each of which are
10represented as child nodes with the following properties:
11
12Required properties:
13- compatible : "snps,dw-apb-gpio-port"
14- gpio-controller : Marks the device node as a gpio controller.
15- #gpio-cells : Should be two.  The first cell is the pin number and
16  the second cell is used to specify the gpio polarity:
17      0 = active high
18      1 = active low
19- reg : The integer port index of the port, a single cell.
20
21Optional properties:
22- interrupt-controller : The first port may be configured to be an interrupt
23controller.
24- #interrupt-cells : Specifies the number of cells needed to encode an
25  interrupt.  Shall be set to 2.  The first cell defines the interrupt number,
26  the second encodes the triger flags encoded as described in
27  Documentation/devicetree/bindings/interrupt-controller/interrupts.txt
28- interrupts : The interrupts to the parent controller raised when GPIOs
29  generate the interrupts. If the controller provides one combined interrupt
30  for all GPIOs, specify a single interrupt. If the controller provides one
31  interrupt for each GPIO, provide a list of interrupts that correspond to each
32  of the GPIO pins. When specifying multiple interrupts, if any are unconnected,
33  use the interrupts-extended property to specify the interrupts and set the
34  interrupt controller handle for unused interrupts to 0.
35- snps,nr-gpios : The number of pins in the port, a single cell.
36- resets : Reset line for the controller.
37
38Example:
39
40gpio: gpio@20000 {
41	compatible = "snps,dw-apb-gpio";
42	reg = <0x20000 0x1000>;
43	#address-cells = <1>;
44	#size-cells = <0>;
45
46	porta: gpio-controller@0 {
47		compatible = "snps,dw-apb-gpio-port";
48		gpio-controller;
49		#gpio-cells = <2>;
50		snps,nr-gpios = <8>;
51		reg = <0>;
52		interrupt-controller;
53		#interrupt-cells = <2>;
54		interrupt-parent = <&vic1>;
55		interrupts = <0>;
56	};
57
58	portb: gpio-controller@1 {
59		compatible = "snps,dw-apb-gpio-port";
60		gpio-controller;
61		#gpio-cells = <2>;
62		snps,nr-gpios = <8>;
63		reg = <1>;
64	};
65};
66