1Allwinner A10 Display Pipeline 2============================== 3 4The Allwinner A10 Display pipeline is composed of several components 5that are going to be documented below: 6 7For all connections between components up to the TCONs in the display 8pipeline, when there are multiple components of the same type at the 9same depth, the local endpoint ID must be the same as the remote 10component's index. For example, if the remote endpoint is Frontend 1, 11then the local endpoint ID must be 1. 12 13 Frontend 0 [0] ------- [0] Backend 0 [0] ------- [0] TCON 0 14 [1] -- -- [1] [1] -- -- [1] 15 \ / \ / 16 X X 17 / \ / \ 18 [0] -- -- [0] [0] -- -- [0] 19 Frontend 1 [1] ------- [1] Backend 1 [1] ------- [1] TCON 1 20 21For a two pipeline system such as the one depicted above, the lines 22represent the connections between the components, while the numbers 23within the square brackets corresponds to the ID of the local endpoint. 24 25The same rule also applies to DE 2.0 mixer-TCON connections: 26 27 Mixer 0 [0] ----------- [0] TCON 0 28 [1] ---- ---- [1] 29 \ / 30 X 31 / \ 32 [0] ---- ---- [0] 33 Mixer 1 [1] ----------- [1] TCON 1 34 35HDMI Encoder 36------------ 37 38The HDMI Encoder supports the HDMI video and audio outputs, and does 39CEC. It is one end of the pipeline. 40 41Required properties: 42 - compatible: value must be one of: 43 * allwinner,sun4i-a10-hdmi 44 * allwinner,sun5i-a10s-hdmi 45 * allwinner,sun6i-a31-hdmi 46 - reg: base address and size of memory-mapped region 47 - interrupts: interrupt associated to this IP 48 - clocks: phandles to the clocks feeding the HDMI encoder 49 * ahb: the HDMI interface clock 50 * mod: the HDMI module clock 51 * ddc: the HDMI ddc clock (A31 only) 52 * pll-0: the first video PLL 53 * pll-1: the second video PLL 54 - clock-names: the clock names mentioned above 55 - resets: phandle to the reset control for the HDMI encoder (A31 only) 56 - dmas: phandles to the DMA channels used by the HDMI encoder 57 * ddc-tx: The channel for DDC transmission 58 * ddc-rx: The channel for DDC reception 59 * audio-tx: The channel used for audio transmission 60 - dma-names: the channel names mentioned above 61 62 - ports: A ports node with endpoint definitions as defined in 63 Documentation/devicetree/bindings/media/video-interfaces.txt. The 64 first port should be the input endpoint. The second should be the 65 output, usually to an HDMI connector. 66 67DWC HDMI TX Encoder 68------------------- 69 70The HDMI transmitter is a Synopsys DesignWare HDMI 1.4 TX controller IP 71with Allwinner's own PHY IP. It supports audio and video outputs and CEC. 72 73These DT bindings follow the Synopsys DWC HDMI TX bindings defined in 74Documentation/devicetree/bindings/display/bridge/dw_hdmi.txt with the 75following device-specific properties. 76 77Required properties: 78 79 - compatible: value must be one of: 80 * "allwinner,sun8i-a83t-dw-hdmi" 81 - reg: base address and size of memory-mapped region 82 - reg-io-width: See dw_hdmi.txt. Shall be 1. 83 - interrupts: HDMI interrupt number 84 - clocks: phandles to the clocks feeding the HDMI encoder 85 * iahb: the HDMI bus clock 86 * isfr: the HDMI register clock 87 * tmds: TMDS clock 88 - clock-names: the clock names mentioned above 89 - resets: phandle to the reset controller 90 - reset-names: must be "ctrl" 91 - phys: phandle to the DWC HDMI PHY 92 - phy-names: must be "phy" 93 94 - ports: A ports node with endpoint definitions as defined in 95 Documentation/devicetree/bindings/media/video-interfaces.txt. The 96 first port should be the input endpoint. The second should be the 97 output, usually to an HDMI connector. 98 99DWC HDMI PHY 100------------ 101 102Required properties: 103 - compatible: value must be one of: 104 * allwinner,sun8i-a83t-hdmi-phy 105 * allwinner,sun8i-h3-hdmi-phy 106 * allwinner,sun50i-a64-hdmi-phy 107 - reg: base address and size of memory-mapped region 108 - clocks: phandles to the clocks feeding the HDMI PHY 109 * bus: the HDMI PHY interface clock 110 * mod: the HDMI PHY module clock 111 - clock-names: the clock names mentioned above 112 - resets: phandle to the reset controller driving the PHY 113 - reset-names: must be "phy" 114 115H3 and A64 HDMI PHY require additional clocks: 116 - pll-0: parent of phy clock 117 - pll-1: second possible phy clock parent (A64 only) 118 119TV Encoder 120---------- 121 122The TV Encoder supports the composite and VGA output. It is one end of 123the pipeline. 124 125Required properties: 126 - compatible: value should be "allwinner,sun4i-a10-tv-encoder". 127 - reg: base address and size of memory-mapped region 128 - clocks: the clocks driving the TV encoder 129 - resets: phandle to the reset controller driving the encoder 130 131- ports: A ports node with endpoint definitions as defined in 132 Documentation/devicetree/bindings/media/video-interfaces.txt. The 133 first port should be the input endpoint. 134 135TCON 136---- 137 138The TCON acts as a timing controller for RGB, LVDS and TV interfaces. 139 140Required properties: 141 - compatible: value must be either: 142 * allwinner,sun4i-a10-tcon 143 * allwinner,sun5i-a13-tcon 144 * allwinner,sun6i-a31-tcon 145 * allwinner,sun6i-a31s-tcon 146 * allwinner,sun7i-a20-tcon 147 * allwinner,sun8i-a33-tcon 148 * allwinner,sun8i-a83t-tcon-lcd 149 * allwinner,sun8i-a83t-tcon-tv 150 * allwinner,sun8i-r40-tcon-tv 151 * allwinner,sun8i-v3s-tcon 152 * allwinner,sun9i-a80-tcon-lcd 153 * allwinner,sun9i-a80-tcon-tv 154 - reg: base address and size of memory-mapped region 155 - interrupts: interrupt associated to this IP 156 - clocks: phandles to the clocks feeding the TCON. 157 - 'ahb': the interface clocks 158 - 'tcon-ch0': The clock driving the TCON channel 0, if supported 159 - resets: phandles to the reset controllers driving the encoder 160 - "lcd": the reset line for the TCON 161 - "edp": the reset line for the eDP block (A80 only) 162 163 - clock-names: the clock names mentioned above 164 - reset-names: the reset names mentioned above 165 - clock-output-names: Name of the pixel clock created, if TCON supports 166 channel 0. 167 168- ports: A ports node with endpoint definitions as defined in 169 Documentation/devicetree/bindings/media/video-interfaces.txt. The 170 first port should be the input endpoint, the second one the output 171 172 The output may have multiple endpoints. TCON can have 1 or 2 channels, 173 usually with the first channel being used for the panels interfaces 174 (RGB, LVDS, etc.), and the second being used for the outputs that 175 require another controller (TV Encoder, HDMI, etc.). The endpoints 176 will take an extra property, allwinner,tcon-channel, to specify the 177 channel the endpoint is associated to. If that property is not 178 present, the endpoint number will be used as the channel number. 179 180For TCONs with channel 0, there is one more clock required: 181 - 'tcon-ch0': The clock driving the TCON channel 0 182For TCONs with channel 1, there is one more clock required: 183 - 'tcon-ch1': The clock driving the TCON channel 1 184 185When TCON support LVDS (all TCONs except TV TCONs on A83T, R40 and those found 186in A13, H3, H5 and V3s SoCs), you need one more reset line: 187 - 'lvds': The reset line driving the LVDS logic 188 189And on the A23, A31, A31s and A33, you need one more clock line: 190 - 'lvds-alt': An alternative clock source, separate from the TCON channel 0 191 clock, that can be used to drive the LVDS clock 192 193TCON TOP 194-------- 195 196TCON TOPs main purpose is to configure whole display pipeline. It determines 197relationships between mixers and TCONs, selects source TCON for HDMI, muxes 198LCD and TV encoder GPIO output, selects TV encoder clock source and contains 199additional TV TCON and DSI gates. 200 201It allows display pipeline to be configured in very different ways: 202 203 / LCD0/LVDS0 204 / [0] TCON-LCD0 205 | \ MIPI DSI 206 mixer0 | 207 \ / [1] TCON-LCD1 - LCD1/LVDS1 208 TCON-TOP 209 / \ [2] TCON-TV0 [0] - TVE0/RGB 210 mixer1 | \ 211 | TCON-TOP - HDMI 212 | / 213 \ [3] TCON-TV1 [1] - TVE1/RGB 214 215Note that both TCON TOP references same physical unit. Both mixers can be 216connected to any TCON. 217 218Required properties: 219 - compatible: value must be one of: 220 * allwinner,sun8i-r40-tcon-top 221 - reg: base address and size of the memory-mapped region. 222 - clocks: phandle to the clocks feeding the TCON TOP 223 * bus: TCON TOP interface clock 224 * tcon-tv0: TCON TV0 clock 225 * tve0: TVE0 clock 226 * tcon-tv1: TCON TV1 clock 227 * tve1: TVE0 clock 228 * dsi: MIPI DSI clock 229 - clock-names: clock name mentioned above 230 - resets: phandle to the reset line driving the TCON TOP 231 - #clock-cells : must contain 1 232 - clock-output-names: Names of clocks created for TCON TV0 channel clock, 233 TCON TV1 channel clock and DSI channel clock, in that order. 234 235- ports: A ports node with endpoint definitions as defined in 236 Documentation/devicetree/bindings/media/video-interfaces.txt. 6 ports should 237 be defined: 238 * port 0 is input for mixer0 mux 239 * port 1 is output for mixer0 mux 240 * port 2 is input for mixer1 mux 241 * port 3 is output for mixer1 mux 242 * port 4 is input for HDMI mux 243 * port 5 is output for HDMI mux 244 All output endpoints for mixer muxes and input endpoints for HDMI mux should 245 have reg property with the id of the target TCON, as shown in above graph 246 (0-3 for mixer muxes and 0-1 for HDMI mux). All ports should have only one 247 endpoint connected to remote endpoint. 248 249DRC 250--- 251 252The DRC (Dynamic Range Controller), found in the latest Allwinner SoCs 253(A31, A23, A33, A80), allows to dynamically adjust pixel 254brightness/contrast based on histogram measurements for LCD content 255adaptive backlight control. 256 257 258Required properties: 259 - compatible: value must be one of: 260 * allwinner,sun6i-a31-drc 261 * allwinner,sun6i-a31s-drc 262 * allwinner,sun8i-a33-drc 263 * allwinner,sun9i-a80-drc 264 - reg: base address and size of the memory-mapped region. 265 - interrupts: interrupt associated to this IP 266 - clocks: phandles to the clocks feeding the DRC 267 * ahb: the DRC interface clock 268 * mod: the DRC module clock 269 * ram: the DRC DRAM clock 270 - clock-names: the clock names mentioned above 271 - resets: phandles to the reset line driving the DRC 272 273- ports: A ports node with endpoint definitions as defined in 274 Documentation/devicetree/bindings/media/video-interfaces.txt. The 275 first port should be the input endpoints, the second one the outputs 276 277Display Engine Backend 278---------------------- 279 280The display engine backend exposes layers and sprites to the 281system. 282 283Required properties: 284 - compatible: value must be one of: 285 * allwinner,sun4i-a10-display-backend 286 * allwinner,sun5i-a13-display-backend 287 * allwinner,sun6i-a31-display-backend 288 * allwinner,sun7i-a20-display-backend 289 * allwinner,sun8i-a33-display-backend 290 * allwinner,sun9i-a80-display-backend 291 - reg: base address and size of the memory-mapped region. 292 - interrupts: interrupt associated to this IP 293 - clocks: phandles to the clocks feeding the frontend and backend 294 * ahb: the backend interface clock 295 * mod: the backend module clock 296 * ram: the backend DRAM clock 297 - clock-names: the clock names mentioned above 298 - resets: phandles to the reset controllers driving the backend 299 300- ports: A ports node with endpoint definitions as defined in 301 Documentation/devicetree/bindings/media/video-interfaces.txt. The 302 first port should be the input endpoints, the second one the output 303 304On the A33, some additional properties are required: 305 - reg needs to have an additional region corresponding to the SAT 306 - reg-names need to be set, with "be" and "sat" 307 - clocks and clock-names need to have a phandle to the SAT bus 308 clocks, whose name will be "sat" 309 - resets and reset-names need to have a phandle to the SAT bus 310 resets, whose name will be "sat" 311 312DEU 313--- 314 315The DEU (Detail Enhancement Unit), found in the Allwinner A80 SoC, 316can sharpen the display content in both luma and chroma channels. 317 318Required properties: 319 - compatible: value must be one of: 320 * allwinner,sun9i-a80-deu 321 - reg: base address and size of the memory-mapped region. 322 - interrupts: interrupt associated to this IP 323 - clocks: phandles to the clocks feeding the DEU 324 * ahb: the DEU interface clock 325 * mod: the DEU module clock 326 * ram: the DEU DRAM clock 327 - clock-names: the clock names mentioned above 328 - resets: phandles to the reset line driving the DEU 329 330- ports: A ports node with endpoint definitions as defined in 331 Documentation/devicetree/bindings/media/video-interfaces.txt. The 332 first port should be the input endpoints, the second one the outputs 333 334Display Engine Frontend 335----------------------- 336 337The display engine frontend does formats conversion, scaling, 338deinterlacing and color space conversion. 339 340Required properties: 341 - compatible: value must be one of: 342 * allwinner,sun4i-a10-display-frontend 343 * allwinner,sun5i-a13-display-frontend 344 * allwinner,sun6i-a31-display-frontend 345 * allwinner,sun7i-a20-display-frontend 346 * allwinner,sun8i-a33-display-frontend 347 * allwinner,sun9i-a80-display-frontend 348 - reg: base address and size of the memory-mapped region. 349 - interrupts: interrupt associated to this IP 350 - clocks: phandles to the clocks feeding the frontend and backend 351 * ahb: the backend interface clock 352 * mod: the backend module clock 353 * ram: the backend DRAM clock 354 - clock-names: the clock names mentioned above 355 - resets: phandles to the reset controllers driving the backend 356 357- ports: A ports node with endpoint definitions as defined in 358 Documentation/devicetree/bindings/media/video-interfaces.txt. The 359 first port should be the input endpoints, the second one the outputs 360 361Display Engine 2.0 Mixer 362------------------------ 363 364The DE2 mixer have many functionalities, currently only layer blending is 365supported. 366 367Required properties: 368 - compatible: value must be one of: 369 * allwinner,sun8i-a83t-de2-mixer-0 370 * allwinner,sun8i-a83t-de2-mixer-1 371 * allwinner,sun8i-h3-de2-mixer-0 372 * allwinner,sun8i-v3s-de2-mixer 373 - reg: base address and size of the memory-mapped region. 374 - clocks: phandles to the clocks feeding the mixer 375 * bus: the mixer interface clock 376 * mod: the mixer module clock 377 - clock-names: the clock names mentioned above 378 - resets: phandles to the reset controllers driving the mixer 379 380- ports: A ports node with endpoint definitions as defined in 381 Documentation/devicetree/bindings/media/video-interfaces.txt. The 382 first port should be the input endpoints, the second one the output 383 384 385Display Engine Pipeline 386----------------------- 387 388The display engine pipeline (and its entry point, since it can be 389either directly the backend or the frontend) is represented as an 390extra node. 391 392Required properties: 393 - compatible: value must be one of: 394 * allwinner,sun4i-a10-display-engine 395 * allwinner,sun5i-a10s-display-engine 396 * allwinner,sun5i-a13-display-engine 397 * allwinner,sun6i-a31-display-engine 398 * allwinner,sun6i-a31s-display-engine 399 * allwinner,sun7i-a20-display-engine 400 * allwinner,sun8i-a33-display-engine 401 * allwinner,sun8i-a83t-display-engine 402 * allwinner,sun8i-h3-display-engine 403 * allwinner,sun8i-r40-display-engine 404 * allwinner,sun8i-v3s-display-engine 405 * allwinner,sun9i-a80-display-engine 406 407 - allwinner,pipelines: list of phandle to the display engine 408 frontends (DE 1.0) or mixers (DE 2.0) available. 409 410Example: 411 412panel: panel { 413 compatible = "olimex,lcd-olinuxino-43-ts"; 414 #address-cells = <1>; 415 #size-cells = <0>; 416 417 port { 418 #address-cells = <1>; 419 #size-cells = <0>; 420 421 panel_input: endpoint { 422 remote-endpoint = <&tcon0_out_panel>; 423 }; 424 }; 425}; 426 427connector { 428 compatible = "hdmi-connector"; 429 type = "a"; 430 431 port { 432 hdmi_con_in: endpoint { 433 remote-endpoint = <&hdmi_out_con>; 434 }; 435 }; 436}; 437 438hdmi: hdmi@1c16000 { 439 compatible = "allwinner,sun5i-a10s-hdmi"; 440 reg = <0x01c16000 0x1000>; 441 interrupts = <58>; 442 clocks = <&ccu CLK_AHB_HDMI>, <&ccu CLK_HDMI>, 443 <&ccu CLK_PLL_VIDEO0_2X>, 444 <&ccu CLK_PLL_VIDEO1_2X>; 445 clock-names = "ahb", "mod", "pll-0", "pll-1"; 446 dmas = <&dma SUN4I_DMA_NORMAL 16>, 447 <&dma SUN4I_DMA_NORMAL 16>, 448 <&dma SUN4I_DMA_DEDICATED 24>; 449 dma-names = "ddc-tx", "ddc-rx", "audio-tx"; 450 451 ports { 452 #address-cells = <1>; 453 #size-cells = <0>; 454 455 port@0 { 456 #address-cells = <1>; 457 #size-cells = <0>; 458 reg = <0>; 459 460 hdmi_in_tcon0: endpoint { 461 remote-endpoint = <&tcon0_out_hdmi>; 462 }; 463 }; 464 465 port@1 { 466 #address-cells = <1>; 467 #size-cells = <0>; 468 reg = <1>; 469 470 hdmi_out_con: endpoint { 471 remote-endpoint = <&hdmi_con_in>; 472 }; 473 }; 474 }; 475}; 476 477tve0: tv-encoder@1c0a000 { 478 compatible = "allwinner,sun4i-a10-tv-encoder"; 479 reg = <0x01c0a000 0x1000>; 480 clocks = <&ahb_gates 34>; 481 resets = <&tcon_ch0_clk 0>; 482 483 port { 484 #address-cells = <1>; 485 #size-cells = <0>; 486 487 tve0_in_tcon0: endpoint@0 { 488 reg = <0>; 489 remote-endpoint = <&tcon0_out_tve0>; 490 }; 491 }; 492}; 493 494tcon0: lcd-controller@1c0c000 { 495 compatible = "allwinner,sun5i-a13-tcon"; 496 reg = <0x01c0c000 0x1000>; 497 interrupts = <44>; 498 resets = <&tcon_ch0_clk 1>; 499 reset-names = "lcd"; 500 clocks = <&ahb_gates 36>, 501 <&tcon_ch0_clk>, 502 <&tcon_ch1_clk>; 503 clock-names = "ahb", 504 "tcon-ch0", 505 "tcon-ch1"; 506 clock-output-names = "tcon-pixel-clock"; 507 508 ports { 509 #address-cells = <1>; 510 #size-cells = <0>; 511 512 tcon0_in: port@0 { 513 #address-cells = <1>; 514 #size-cells = <0>; 515 reg = <0>; 516 517 tcon0_in_be0: endpoint@0 { 518 reg = <0>; 519 remote-endpoint = <&be0_out_tcon0>; 520 }; 521 }; 522 523 tcon0_out: port@1 { 524 #address-cells = <1>; 525 #size-cells = <0>; 526 reg = <1>; 527 528 tcon0_out_panel: endpoint@0 { 529 reg = <0>; 530 remote-endpoint = <&panel_input>; 531 }; 532 533 tcon0_out_tve0: endpoint@1 { 534 reg = <1>; 535 remote-endpoint = <&tve0_in_tcon0>; 536 }; 537 }; 538 }; 539}; 540 541fe0: display-frontend@1e00000 { 542 compatible = "allwinner,sun5i-a13-display-frontend"; 543 reg = <0x01e00000 0x20000>; 544 interrupts = <47>; 545 clocks = <&ahb_gates 46>, <&de_fe_clk>, 546 <&dram_gates 25>; 547 clock-names = "ahb", "mod", 548 "ram"; 549 resets = <&de_fe_clk>; 550 551 ports { 552 #address-cells = <1>; 553 #size-cells = <0>; 554 555 fe0_out: port@1 { 556 #address-cells = <1>; 557 #size-cells = <0>; 558 reg = <1>; 559 560 fe0_out_be0: endpoint { 561 remote-endpoint = <&be0_in_fe0>; 562 }; 563 }; 564 }; 565}; 566 567be0: display-backend@1e60000 { 568 compatible = "allwinner,sun5i-a13-display-backend"; 569 reg = <0x01e60000 0x10000>; 570 interrupts = <47>; 571 clocks = <&ahb_gates 44>, <&de_be_clk>, 572 <&dram_gates 26>; 573 clock-names = "ahb", "mod", 574 "ram"; 575 resets = <&de_be_clk>; 576 577 ports { 578 #address-cells = <1>; 579 #size-cells = <0>; 580 581 be0_in: port@0 { 582 #address-cells = <1>; 583 #size-cells = <0>; 584 reg = <0>; 585 586 be0_in_fe0: endpoint@0 { 587 reg = <0>; 588 remote-endpoint = <&fe0_out_be0>; 589 }; 590 }; 591 592 be0_out: port@1 { 593 #address-cells = <1>; 594 #size-cells = <0>; 595 reg = <1>; 596 597 be0_out_tcon0: endpoint@0 { 598 reg = <0>; 599 remote-endpoint = <&tcon0_in_be0>; 600 }; 601 }; 602 }; 603}; 604 605display-engine { 606 compatible = "allwinner,sun5i-a13-display-engine"; 607 allwinner,pipelines = <&fe0>; 608}; 609
