1Marvell Armada AP806 System Controller
2======================================
3
4The AP806 is one of the two core HW blocks of the Marvell Armada 7K/8K
5SoCs. It contains system controllers, which provide several registers
6giving access to numerous features: clocks, pin-muxing and many other
7SoC configuration items. This DT binding allows to describe these
8system controllers.
9
10For the top level node:
11 - compatible: must be: "syscon", "simple-mfd";
12 - reg: register area of the AP806 system controller
13
14SYSTEM CONTROLLER 0
15===================
16
17Clocks:
18-------
19
20
21The Device Tree node representing the AP806 system controller provides
22a number of clocks:
23
24 - 0: clock of CPU cluster 0
25 - 1: clock of CPU cluster 1
26 - 2: fixed PLL at 1200 Mhz
27 - 3: MSS clock, derived from the fixed PLL
28
29Required properties:
30
31 - compatible: must be: "marvell,ap806-clock"
32 - #clock-cells: must be set to 1
33
34Pinctrl:
35--------
36
37For common binding part and usage, refer to
38Documentation/devicetree/bindings/pinctrl/marvell,mvebu-pinctrl.txt.
39
40Required properties:
41- compatible must be "marvell,ap806-pinctrl",
42
43Available mpp pins/groups and functions:
44Note: brackets (x) are not part of the mpp name for marvell,function and given
45only for more detailed description in this document.
46
47name	pins	functions
48================================================================================
49mpp0	0	gpio, sdio(clk), spi0(clk)
50mpp1	1	gpio, sdio(cmd), spi0(miso)
51mpp2	2	gpio, sdio(d0), spi0(mosi)
52mpp3	3	gpio, sdio(d1), spi0(cs0n)
53mpp4	4	gpio, sdio(d2), i2c0(sda)
54mpp5	5	gpio, sdio(d3), i2c0(sdk)
55mpp6	6	gpio, sdio(ds)
56mpp7	7	gpio, sdio(d4), uart1(rxd)
57mpp8	8	gpio, sdio(d5), uart1(txd)
58mpp9	9	gpio, sdio(d6), spi0(cs1n)
59mpp10	10	gpio, sdio(d7)
60mpp11	11	gpio, uart0(txd)
61mpp12	12	gpio, sdio(pw_off), sdio(hw_rst)
62mpp13	13	gpio
63mpp14	14	gpio
64mpp15	15	gpio
65mpp16	16	gpio
66mpp17	17	gpio
67mpp18	18	gpio
68mpp19	19	gpio, uart0(rxd), sdio(pw_off)
69
70GPIO:
71-----
72For common binding part and usage, refer to
73Documentation/devicetree/bindings/gpio/gpio-mvebu.txt.
74
75Required properties:
76
77- compatible: "marvell,armada-8k-gpio"
78
79- offset: offset address inside the syscon block
80
81Example:
82ap_syscon: system-controller@6f4000 {
83	compatible = "syscon", "simple-mfd";
84	reg = <0x6f4000 0x1000>;
85
86	ap_clk: clock {
87		compatible = "marvell,ap806-clock";
88		#clock-cells = <1>;
89	};
90
91	ap_pinctrl: pinctrl {
92		compatible = "marvell,ap806-pinctrl";
93	};
94
95	ap_gpio: gpio {
96		compatible = "marvell,armada-8k-gpio";
97		offset = <0x1040>;
98		ngpios = <19>;
99		gpio-controller;
100		#gpio-cells = <2>;
101		gpio-ranges = <&ap_pinctrl 0 0 19>;
102	};
103};
104
105SYSTEM CONTROLLER 1
106===================
107
108Thermal:
109--------
110
111For common binding part and usage, refer to
112Documentation/devicetree/bindings/thermal/thermal.txt
113
114The thermal IP can probe the temperature all around the processor. It
115may feature several channels, each of them wired to one sensor.
116
117Required properties:
118- compatible: must be one of:
119  * marvell,armada-ap806-thermal
120- reg: register range associated with the thermal functions.
121
122Optional properties:
123- #thermal-sensor-cells: shall be <1> when thermal-zones subnodes refer
124  to this IP and represents the channel ID. There is one sensor per
125  channel. O refers to the thermal IP internal channel, while positive
126  IDs refer to each CPU.
127
128Example:
129ap_syscon1: system-controller@6f8000 {
130	compatible = "syscon", "simple-mfd";
131	reg = <0x6f8000 0x1000>;
132
133	ap_thermal: thermal-sensor@80 {
134		compatible = "marvell,armada-ap806-thermal";
135		reg = <0x80 0x10>;
136		#thermal-sensor-cells = <1>;
137	};
138};
139